opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
   4         * i386-tbl.h: Re-generate.
   5
   6 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
   9         (vpbroadcastw, rdpid): Drop NoRex64.
  10         * i386-tbl.h: Re-generate.
  11
  12 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
  15         store templates, adding D.
  16         * i386-tbl.h: Re-generate.
  17
  18 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  19
  20         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
  21         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
  22         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
  23         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
  24         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
  25         Fold load and store templates where possible, adding D. Drop
  26         IgnoreSize where it was pointlessly present. Drop redundant
  27         *word.
  28         * i386-tbl.h: Re-generate.
  29
  30 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
  33         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
  34         (intel_operand_size): Handle v_bndmk_mode.
  35         (OP_E_memory): Likewise. Produce (bad) when also riprel.
  36
  37 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
  38
  39         * disassemble.c (ARCH_s12z): Define if ARCH_all.
  40
  41 2018-08-31  Kito Cheng  <kito@andestech.com>
  42
  43         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
  44         compressed floating point instructions.
  45
  46 2018-08-30  Kito Cheng  <kito@andestech.com>
  47
  48         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
  49         riscv_opcode.xlen_requirement.
  50         * riscv-opc.c (riscv_opcodes): Update for struct change.
  51
  52 2018-08-29  Martin Aberg  <maberg@gaisler.com>
  53
  54         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
  55         psr (PWRPSR) instruction.
  56
  57 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  58
  59         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
  60
  61 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  62
  63         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
  64
  65 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  66
  67         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
  68         loongson3a as an alias of gs464 for compatibility.
  69         * mips-opc.c (mips_opcodes): Change Comments.
  70
  71 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  72
  73         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
  74         option.
  75         (print_mips_disassembler_options): Document -M loongson-ext.
  76         * mips-opc.c (LEXT2): New macro.
  77         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
  78
  79 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  80
  81          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
  82          descriptors.
  83          (parse_mips_ase_option): Handle -M loongson-ext option.
  84          (print_mips_disassembler_options): Document -M loongson-ext.
  85          * mips-opc.c (IL3A): Delete.
  86          * mips-opc.c (LEXT): New macro.
  87          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
  88          instructions.
  89
  90 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  91
  92         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
  93         descriptors.
  94         (parse_mips_ase_option): Handle -M loongson-cam option.
  95         (print_mips_disassembler_options): Document -M loongson-cam.
  96         * mips-opc.c (LCAM): New macro.
  97         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
  98         instructions.
  99
 100 2018-08-21  Alan Modra  <amodra@gmail.com>
 101
 102         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 103         (skip_optional_operands): Count optional operands, and update
 104         ppc_optional_operand_value call.
 105         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 106         (extract_vlensi): Likewise.
 107         (extract_fxm): Return default value for missing optional operand.
 108         (extract_ls, extract_raq, extract_tbr): Likewise.
 109         (insert_sxl, extract_sxl): New functions.
 110         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 111         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 112         flag and extra entry.
 113         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 114         extract_sxl.
 115
 116 2018-08-20  Alan Modra  <amodra@gmail.com>
 117
 118         * sh-opc.h (MASK): Simplify.
 119
 120 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 121
 122         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 123         BM_RESERVED0 or BM_RESERVED1
 124         (bm_rel_decode, bm_n_bytes): Ditto.
 125
 126 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 127
 128         * s12z.h: Delete.
 129
 130 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 131
 132         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 133         address with the addr32 prefix and without base nor index
 134         registers.
 135
 136 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 139         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 140         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 141         (cpu_flags): Add CpuCMOV and CpuFXSR.
 142         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 143         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 144         * i386-init.h: Regenerated.
 145         * i386-tbl.h: Likewise.
 146
 147 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 148
 149         * arc-regs.h: Update auxiliary registers.
 150
 151 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 154         (RegIP, RegIZ): Define.
 155         * i386-reg.tbl: Adjust comments.
 156         (rip): Use Qword instead of BaseIndex. Use RegIP.
 157         (eip): Use Dword instead of BaseIndex. Use RegIP.
 158         (riz): Add Qword. Use RegIZ.
 159         (eiz): Add Dword. Use RegIZ.
 160         * i386-tbl.h: Re-generate.
 161
 162 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 165         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 166         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 167         * i386-tbl.h: Re-generate.
 168
 169 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-gen.c (operand_types): Remove Mem field.
 172         * i386-opc.h (union i386_operand_type): Remove mem field.
 173         * i386-init.h, i386-tbl.h: Re-generate.
 174
 175 2018-08-01  Alan Modra  <amodra@gmail.com>
 176
 177         * po/POTFILES.in: Regenerate.
 178
 179 2018-07-31  Nick Clifton  <nickc@redhat.com>
 180
 181         * po/sv.po: Updated Swedish translation.
 182
 183 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 186         * i386-init.h, i386-tbl.h: Re-generate.
 187
 188 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 189
 190         * i386-opc.h (ZEROING_MASKING) Rename to ...
 191         (DYNAMIC_MASKING): ... this. Adjust comment.
 192         * i386-opc.tbl (MaskingMorZ): Define.
 193         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 194         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 195         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 196         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 197         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 198         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 199         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 200         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 201         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 202
 203 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-opc.tbl: Use element rather than vector size for AVX512*
 206         scatter/gather insns.
 207         * i386-tbl.h: Re-generate.
 208
 209 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 210
 211         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 212         (cpu_flags): Drop CpuVREX.
 213         * i386-opc.h (CpuVREX): Delete.
 214         (union i386_cpu_flags): Remove cpuvrex.
 215         * i386-init.h, i386-tbl.h: Re-generate.
 216
 217 2018-07-30  Jim Wilson  <jimw@sifive.com>
 218
 219         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 220         fields.
 221         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 222
 223 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 224
 225         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 226         * Makefile.in: Regenerated.
 227         * configure.ac: Add C-SKY.
 228         * configure: Regenerated.
 229         * csky-dis.c: New file.
 230         * csky-opc.h: New file.
 231         * disassemble.c (ARCH_csky): Define.
 232         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 233         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 234
 235 2018-07-27  Alan Modra  <amodra@gmail.com>
 236
 237         * ppc-opc.c (insert_sprbat): Correct function parameter and
 238         return type.
 239         (extract_sprbat): Likewise, variable too.
 240
 241 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 242             Alan Modra  <amodra@gmail.com>
 243
 244         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 245         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 246         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 247         support disjointed BAT.
 248         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 249         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 250         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 251
 252 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 253             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 254
 255         * i386-gen.c (adjust_broadcast_modifier): New function.
 256         (process_i386_opcode_modifier): Add an argument for operands.
 257         Adjust the Broadcast value based on operands.
 258         (output_i386_opcode): Pass operand_types to
 259         process_i386_opcode_modifier.
 260         (process_i386_opcodes): Pass NULL as operands to
 261         process_i386_opcode_modifier.
 262         * i386-opc.h (BYTE_BROADCAST): New.
 263         (WORD_BROADCAST): Likewise.
 264         (DWORD_BROADCAST): Likewise.
 265         (QWORD_BROADCAST): Likewise.
 266         (i386_opcode_modifier): Expand broadcast to 3 bits.
 267         * i386-tbl.h: Regenerated.
 268
 269 2018-07-24  Alan Modra  <amodra@gmail.com>
 270
 271         PR 23430
 272         * or1k-desc.h: Regenerate.
 273
 274 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 277         vcvtusi2ss, and vcvtusi2sd.
 278         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 279         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 280         * i386-tbl.h: Re-generate.
 281
 282 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 283
 284         * arc-opc.c (extract_w6): Fix extending the sign.
 285
 286 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 287
 288         * arc-tbl.h (vewt): Allow it for ARC EM family.
 289
 290 2018-07-23  Alan Modra  <amodra@gmail.com>
 291
 292         PR 23419
 293         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 294         opcode variants for mtspr/mfspr encodings.
 295
 296 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 297             Maciej W. Rozycki  <macro@mips.com>
 298
 299         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 300         loongson3a descriptors.
 301         (parse_mips_ase_option): Handle -M loongson-mmi option.
 302         (print_mips_disassembler_options): Document -M loongson-mmi.
 303         * mips-opc.c (LMMI): New macro.
 304         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 305         instructions.
 306
 307 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 310         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 311         IgnoreSize and [XYZ]MMword where applicable.
 312         * i386-tbl.h: Re-generate.
 313
 314 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 317         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 318         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 319         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 320         * i386-tbl.h: Re-generate.
 321
 322 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 325         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 326         VPCLMULQDQ templates into their respective AVX512VL counterparts
 327         where possible, using Disp8ShiftVL and CheckRegSize instead of
 328         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 329         * i386-tbl.h: Re-generate.
 330
 331 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 334         AVX512VL counterparts where possible, using Disp8ShiftVL and
 335         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 336         IgnoreSize) as appropriate.
 337         * i386-tbl.h: Re-generate.
 338
 339 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 340
 341         * i386-opc.tbl: Fold AVX512BW templates into their respective
 342         AVX512VL counterparts where possible, using Disp8ShiftVL and
 343         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 344         IgnoreSize) as appropriate.
 345         * i386-tbl.h: Re-generate.
 346
 347 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.tbl: Fold AVX512CD templates into their respective
 350         AVX512VL counterparts where possible, using Disp8ShiftVL and
 351         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 352         IgnoreSize) as appropriate.
 353         * i386-tbl.h: Re-generate.
 354
 355 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-opc.h (DISP8_SHIFT_VL): New.
 358         * i386-opc.tbl (Disp8ShiftVL):  Define.
 359         (various): Fold AVX512VL templates into their respective
 360         AVX512F counterparts where possible, using Disp8ShiftVL and
 361         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 362         IgnoreSize) as appropriate.
 363         * i386-tbl.h: Re-generate.
 364
 365 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 366
 367         * Makefile.am: Change dependencies and rule for
 368         $(srcdir)/i386-init.h.
 369         * Makefile.in: Re-generate.
 370         * i386-gen.c (process_i386_opcodes): New local variable
 371         "marker". Drop opening of input file. Recognize marker and line
 372         number directives.
 373         * i386-opc.tbl (OPCODE_I386_H): Define.
 374         (i386-opc.h): Include it.
 375         (None): Undefine.
 376
 377 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 378
 379         PR gas/23418
 380         * i386-opc.h (Byte): Update comments.
 381         (Word): Likewise.
 382         (Dword): Likewise.
 383         (Fword): Likewise.
 384         (Qword): Likewise.
 385         (Tbyte): Likewise.
 386         (Xmmword): Likewise.
 387         (Ymmword): Likewise.
 388         (Zmmword): Likewise.
 389         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 390         vcvttps2uqq.
 391         * i386-tbl.h: Regenerated.
 392
 393 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 394
 395         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 396         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 397         * aarch64-asm-2.c: Regenerate.
 398         * aarch64-dis-2.c: Regenerate.
 399         * aarch64-opc-2.c: Regenerate.
 400
 401 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 402
 403         PR binutils/23192
 404         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 405         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 406         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 407         sqdmulh, sqrdmulh): Use Em16.
 408
 409 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 410
 411         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 412         csdb together with them.
 413         (thumb32_opcodes): Likewise.
 414
 415 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 418         requiring 32-bit registers as operands 2 and 3. Improve
 419         comments.
 420         (mwait, mwaitx): Fold templates. Improve comments.
 421         OPERAND_TYPE_INOUTPORTREG.
 422         * i386-tbl.h: Re-generate.
 423
 424 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-gen.c (operand_type_init): Remove
 427         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 428         OPERAND_TYPE_INOUTPORTREG.
 429         * i386-init.h: Re-generate.
 430
 431 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 434         (wrssq, wrussq): Add Qword.
 435         * i386-tbl.h: Re-generate.
 436
 437 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-opc.h: Rename OTMax to OTNum.
 440         (OTNumOfUints): Adjust calculation.
 441         (OTUnused): Directly alias to OTNum.
 442
 443 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 444
 445         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 446         `reg_xys'.
 447         (lea_reg_xys): Likewise.
 448         (print_insn_loop_primitive): Rename `reg' local variable to
 449         `reg_dxy'.
 450
 451 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 452
 453         PR binutils/23242
 454         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 455
 456 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 457
 458         PR binutils/23369
 459         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 460         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 461
 462 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 463
 464         PR tdep/8282
 465         * mips-dis.c (mips_option_arg_t): New enumeration.
 466         (mips_options): New variable.
 467         (disassembler_options_mips): New function.
 468         (print_mips_disassembler_options): Reimplement in terms of
 469         `disassembler_options_mips'.
 470         * arm-dis.c (disassembler_options_arm): Adapt to using the
 471         `disasm_options_and_args_t' structure.
 472         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 473         * s390-dis.c (disassembler_options_s390): Likewise.
 474
 475 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 476
 477         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 478         expected result.
 479         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 480         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 481         * testsuite/ld-arm/tls-longplt.d: Likewise.
 482
 483 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 484
 485         PR binutils/23192
 486         * aarch64-asm-2.c: Regenerate.
 487         * aarch64-dis-2.c: Likewise.
 488         * aarch64-opc-2.c: Likewise.
 489         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 490         * aarch64-opc.c (operand_general_constraint_met_p,
 491         aarch64_print_operand): Likewise.
 492         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 493         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 494         fmlal2, fmlsl2.
 495         (AARCH64_OPERANDS): Add Em2.
 496
 497 2018-06-26  Nick Clifton  <nickc@redhat.com>
 498
 499         * po/uk.po: Updated Ukranian translation.
 500         * po/de.po: Updated German translation.
 501         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 502
 503 2018-06-26  Nick Clifton  <nickc@redhat.com>
 504
 505         * nfp-dis.c: Fix spelling mistake.
 506
 507 2018-06-24  Nick Clifton  <nickc@redhat.com>
 508
 509         * configure: Regenerate.
 510         * po/opcodes.pot: Regenerate.
 511
 512 2018-06-24  Nick Clifton  <nickc@redhat.com>
 513
 514         2.31 branch created.
 515
 516 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 517
 518         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 519         * aarch64-asm-2.c: Regenerate.
 520         * aarch64-dis-2.c: Likewise.
 521
 522 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 523
 524         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 525         `-M ginv' option description.
 526
 527 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 528
 529         PR gas/23305
 530         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 531         la and lla.
 532
 533 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 534
 535         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 536         * configure.ac: Remove AC_PREREQ.
 537         * Makefile.in: Re-generate.
 538         * aclocal.m4: Re-generate.
 539         * configure: Re-generate.
 540
 541 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 542
 543         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 544         mips64r6 descriptors.
 545         (parse_mips_ase_option): Handle -Mginv option.
 546         (print_mips_disassembler_options): Document -Mginv.
 547         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 548         (GINV): New macro.
 549         (mips_opcodes): Define ginvi and ginvt.
 550
 551 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 552             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 553
 554         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 555         * mips-opc.c (CRC, CRC64): New macros.
 556         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 557         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 558         crc32cd for CRC64.
 559
 560 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 561
 562         PR 20319
 563         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 564         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 565
 566 2018-06-06  Alan Modra  <amodra@gmail.com>
 567
 568         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 569         setjmp.  Move init for some other vars later too.
 570
 571 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 572
 573         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 574         (dis_private): Add new fields for property section tracking.
 575         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 576         (xtensa_instruction_fits): New functions.
 577         (fetch_data): Bump minimal fetch size to 4.
 578         (print_insn_xtensa): Make struct dis_private static.
 579         Load and prepare property table on section change.
 580         Don't disassemble literals. Don't disassemble instructions that
 581         cross property table boundaries.
 582
 583 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 584
 585         * configure: Regenerated.
 586
 587 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 590         * i386-tbl.h: Re-generate.
 591
 592 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl (sldt, str): Add NoRex64.
 595         * i386-tbl.h: Re-generate.
 596
 597 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl (invpcid): Add Oword.
 600         * i386-tbl.h: Re-generate.
 601
 602 2018-06-01  Alan Modra  <amodra@gmail.com>
 603
 604         * sysdep.h (_bfd_error_handler): Don't declare.
 605         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 606         * rl78-decode.opc: Likewise.
 607         * msp430-decode.c: Regenerate.
 608         * rl78-decode.c: Regenerate.
 609
 610 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 611
 612         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 613         * i386-init.h : Regenerated.
 614
 615 2018-05-25  Alan Modra  <amodra@gmail.com>
 616
 617         * Makefile.in: Regenerate.
 618         * po/POTFILES.in: Regenerate.
 619
 620 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 621
 622         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 623         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 624         (insert_bab, extract_bab, insert_btab, extract_btab,
 625         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 626         (BAT, BBA VBA RBS XB6S): Delete macros.
 627         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 628         (BB, BD, RBX, XC6): Update for new macros.
 629         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 630         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 631         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 632         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 633
 634 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 635
 636         * Makefile.am: Add support for s12z architecture.
 637         * configure.ac: Likewise.
 638         * disassemble.c: Likewise.
 639         * disassemble.h: Likewise.
 640         * Makefile.in: Regenerate.
 641         * configure: Regenerate.
 642         * s12z-dis.c: New file.
 643         * s12z.h: New file.
 644
 645 2018-05-18  Alan Modra  <amodra@gmail.com>
 646
 647         * nfp-dis.c: Don't #include libbfd.h.
 648         (init_nfp3200_priv): Use bfd_get_section_contents.
 649         (nit_nfp6000_mecsr_sec): Likewise.
 650
 651 2018-05-17  Nick Clifton  <nickc@redhat.com>
 652
 653         * po/zh_CN.po: Updated simplified Chinese translation.
 654
 655 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 656
 657         PR binutils/23109
 658         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 659         * aarch64-dis-2.c: Regenerate.
 660
 661 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 662
 663         PR binutils/21446
 664         * aarch64-asm.c (opintl.h): Include.
 665         (aarch64_ins_sysreg): Enforce read/write constraints.
 666         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 667         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 668         (F_REG_READ, F_REG_WRITE): New.
 669         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 670         AARCH64_OPND_SYSREG.
 671         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 672         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 673         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 674         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 675         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 676         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 677         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 678         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 679         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 680         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 681         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 682         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 683         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 684         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 685         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 686         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 687         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 688
 689 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 690
 691         PR binutils/21446
 692         * aarch64-dis.c (no_notes: New.
 693         (parse_aarch64_dis_option): Support notes.
 694         (aarch64_decode_insn, print_operands): Likewise.
 695         (print_aarch64_disassembler_options): Document notes.
 696         * aarch64-opc.c (aarch64_print_operand): Support notes.
 697
 698 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 699
 700         PR binutils/21446
 701         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 702         and take error struct.
 703         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 704         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 705         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 706         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 707         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 708         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 709         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 710         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 711         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 712         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 713         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 714         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 715         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 716         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 717         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 718         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 719         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 720         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 721         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 722         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 723         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 724         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 725         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 726         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 727         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 728         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 729         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 730         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 731         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 732         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 733         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 734         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 735         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 736         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 737         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 738         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 739         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 740         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 741         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 742         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 743         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 744         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 745         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 746         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 747         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 748         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 749         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 750         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 751         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 752         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 753         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 754         (determine_disassembling_preference, aarch64_decode_insn,
 755         print_insn_aarch64_word, print_insn_data): Take errors struct.
 756         (print_insn_aarch64): Use errors.
 757         * aarch64-asm-2.c: Regenerate.
 758         * aarch64-dis-2.c: Regenerate.
 759         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 760         boolean in aarch64_insert_operan.
 761         (print_operand_extractor): Likewise.
 762         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 763
 764 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 765
 766         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 767
 768 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 771
 772 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 773
 774         * cr16-opc.c (cr16_instruction): Comment typo fix.
 775         * hppa-dis.c (print_insn_hppa): Likewise.
 776
 777 2018-05-08  Jim Wilson  <jimw@sifive.com>
 778
 779         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 780         (match_c_slli64, match_srxi_as_c_srxi): New.
 781         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 782         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 783         <c.slli, c.srli, c.srai>: Use match_s_slli.
 784         <c.slli64, c.srli64, c.srai64>: New.
 785
 786 2018-05-08  Alan Modra  <amodra@gmail.com>
 787
 788         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 789         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 790         partition opcode space for index lookup.
 791
 792 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 793
 794         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 795         <insn_length>: ...with this.  Update usage.
 796         Remove duplicate call to *info->memory_error_func.
 797
 798 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 799             H.J. Lu  <hongjiu.lu@intel.com>
 800
 801         * i386-dis.c (Gva): New.
 802         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 803         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 804         (prefix_table): New instructions (see prefix above).
 805         (mod_table): New instructions (see prefix above).
 806         (OP_G): Handle va_mode.
 807         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 808         CPU_MOVDIR64B_FLAGS.
 809         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 810         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 811         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 812         * i386-opc.tbl: Add movidir{i,64b}.
 813         * i386-init.h: Regenerated.
 814         * i386-tbl.h: Likewise.
 815
 816 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 819         AddrPrefixOpReg.
 820         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 821         (AddrPrefixOpReg): This.
 822         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 823         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 824
 825 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 826
 827         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 828         (vle_num_opcodes): Likewise.
 829         (spe2_num_opcodes): Likewise.
 830         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 831         initialization loop.
 832         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 833         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 834         only once.
 835
 836 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 837
 838         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 839
 840 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 841
 842         Makefile.am: Added nfp-dis.c.
 843         configure.ac: Added bfd_nfp_arch.
 844         disassemble.h: Added print_insn_nfp prototype.
 845         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 846         nfp-dis.c: New, for NFP support.
 847         po/POTFILES.in: Added nfp-dis.c to the list.
 848         Makefile.in: Regenerate.
 849         configure: Regenerate.
 850
 851 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 852
 853         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 854         templates into their base ones.
 855         * i386-tlb.h: Re-generate.
 856
 857 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 858
 859         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 860         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 861         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 862         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 863         * i386-init.h: Re-generate.
 864
 865 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 866
 867         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 868         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 869         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 870         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 871         comment.
 872         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 873         and CpuRegMask.
 874         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 875         CpuRegMask: Delete.
 876         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 877         cpuregzmm, and cpuregmask.
 878         * i386-init.h: Re-generate.
 879         * i386-tbl.h: Re-generate.
 880
 881 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 884         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 885         * i386-init.h: Re-generate.
 886
 887 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 888
 889         * i386-gen.c (VexImmExt): Delete.
 890         * i386-opc.h (VexImmExt, veximmext): Delete.
 891         * i386-opc.tbl: Drop all VexImmExt uses.
 892         * i386-tlb.h: Re-generate.
 893
 894 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 895
 896         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 897         register-only forms.
 898         * i386-tlb.h: Re-generate.
 899
 900 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 901
 902         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 903
 904 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 905
 906         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 907         PREFIX_0F1C.
 908         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 909         (cpu_flags): Add CpuCLDEMOTE.
 910         * i386-init.h: Regenerate.
 911         * i386-opc.h (enum): Add CpuCLDEMOTE,
 912         (i386_cpu_flags): Add cpucldemote.
 913         * i386-opc.tbl: Add cldemote.
 914         * i386-tbl.h: Regenerate.
 915
 916 2018-04-16  Alan Modra  <amodra@gmail.com>
 917
 918         * Makefile.am: Remove sh5 and sh64 support.
 919         * configure.ac: Likewise.
 920         * disassemble.c: Likewise.
 921         * disassemble.h: Likewise.
 922         * sh-dis.c: Likewise.
 923         * sh64-dis.c: Delete.
 924         * sh64-opc.c: Delete.
 925         * sh64-opc.h: Delete.
 926         * Makefile.in: Regenerate.
 927         * configure: Regenerate.
 928         * po/POTFILES.in: Regenerate.
 929
 930 2018-04-16  Alan Modra  <amodra@gmail.com>
 931
 932         * Makefile.am: Remove w65 support.
 933         * configure.ac: Likewise.
 934         * disassemble.c: Likewise.
 935         * disassemble.h: Likewise.
 936         * w65-dis.c: Delete.
 937         * w65-opc.h: Delete.
 938         * Makefile.in: Regenerate.
 939         * configure: Regenerate.
 940         * po/POTFILES.in: Regenerate.
 941
 942 2018-04-16  Alan Modra  <amodra@gmail.com>
 943
 944         * configure.ac: Remove we32k support.
 945         * configure: Regenerate.
 946
 947 2018-04-16  Alan Modra  <amodra@gmail.com>
 948
 949         * Makefile.am: Remove m88k support.
 950         * configure.ac: Likewise.
 951         * disassemble.c: Likewise.
 952         * disassemble.h: Likewise.
 953         * m88k-dis.c: Delete.
 954         * Makefile.in: Regenerate.
 955         * configure: Regenerate.
 956         * po/POTFILES.in: Regenerate.
 957
 958 2018-04-16  Alan Modra  <amodra@gmail.com>
 959
 960         * Makefile.am: Remove i370 support.
 961         * configure.ac: Likewise.
 962         * disassemble.c: Likewise.
 963         * disassemble.h: Likewise.
 964         * i370-dis.c: Delete.
 965         * i370-opc.c: Delete.
 966         * Makefile.in: Regenerate.
 967         * configure: Regenerate.
 968         * po/POTFILES.in: Regenerate.
 969
 970 2018-04-16  Alan Modra  <amodra@gmail.com>
 971
 972         * Makefile.am: Remove h8500 support.
 973         * configure.ac: Likewise.
 974         * disassemble.c: Likewise.
 975         * disassemble.h: Likewise.
 976         * h8500-dis.c: Delete.
 977         * h8500-opc.h: Delete.
 978         * Makefile.in: Regenerate.
 979         * configure: Regenerate.
 980         * po/POTFILES.in: Regenerate.
 981
 982 2018-04-16  Alan Modra  <amodra@gmail.com>
 983
 984         * configure.ac: Remove tahoe support.
 985         * configure: Regenerate.
 986
 987 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 988
 989         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 990         umwait.
 991         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 992         64-bit mode.
 993         * i386-tbl.h: Regenerated.
 994
 995 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 996
 997         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 998         PREFIX_MOD_1_0FAE_REG_6.
 999         (va_mode): New.
1000         (OP_E_register): Use va_mode.
1001         * i386-dis-evex.h (prefix_table):
1002         New instructions (see prefixes above).
1003         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1004         (cpu_flags): Likewise.
1005         * i386-opc.h (enum): Likewise.
1006         (i386_cpu_flags): Likewise.
1007         * i386-opc.tbl: Add umonitor, umwait, tpause.
1008         * i386-init.h: Regenerate.
1009         * i386-tbl.h: Likewise.
1010
1011 2018-04-11  Alan Modra  <amodra@gmail.com>
1012
1013         * opcodes/i860-dis.c: Delete.
1014         * opcodes/i960-dis.c: Delete.
1015         * Makefile.am: Remove i860 and i960 support.
1016         * configure.ac: Likewise.
1017         * disassemble.c: Likewise.
1018         * disassemble.h: Likewise.
1019         * Makefile.in: Regenerate.
1020         * configure: Regenerate.
1021         * po/POTFILES.in: Regenerate.
1022
1023 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1024
1025         PR binutils/23025
1026         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1027         to 0.
1028         (print_insn): Clear vex instead of vex.evex.
1029
1030 2018-04-04  Nick Clifton  <nickc@redhat.com>
1031
1032         * po/es.po: Updated Spanish translation.
1033
1034 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1035
1036         * i386-gen.c (opcode_modifiers): Delete VecESize.
1037         * i386-opc.h (VecESize): Delete.
1038         (struct i386_opcode_modifier): Delete vecesize.
1039         * i386-opc.tbl: Drop VecESize.
1040         * i386-tlb.h: Re-generate.
1041
1042 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1045         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1046         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1047         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1048         * i386-tlb.h: Re-generate.
1049
1050 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1051
1052         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1053         Fold AVX512 forms
1054         * i386-tlb.h: Re-generate.
1055
1056 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1057
1058         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1059         (vex_len_table): Drop Y for vcvt*2si.
1060         (putop): Replace plain 'Y' handling by abort().
1061
1062 2018-03-28  Nick Clifton  <nickc@redhat.com>
1063
1064         PR 22988
1065         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1066         instructions with only a base address register.
1067         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1068         handle AARHC64_OPND_SVE_ADDR_R.
1069         (aarch64_print_operand): Likewise.
1070         * aarch64-asm-2.c: Regenerate.
1071         * aarch64_dis-2.c: Regenerate.
1072         * aarch64-opc-2.c: Regenerate.
1073
1074 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1075
1076         * i386-opc.tbl: Drop VecESize from register only insn forms and
1077         memory forms not allowing broadcast.
1078         * i386-tlb.h: Re-generate.
1079
1080 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1083         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1084         sha256*): Drop Disp<N>.
1085
1086 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1087
1088         * i386-dis.c (EbndS, bnd_swap_mode): New.
1089         (prefix_table): Use EbndS.
1090         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1091         * i386-opc.tbl (bndmov): Move misplaced Load.
1092         * i386-tlb.h: Re-generate.
1093
1094 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1097         templates allowing memory operands and folded ones for register
1098         only flavors.
1099         * i386-tlb.h: Re-generate.
1100
1101 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1102
1103         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1104         256-bit templates. Drop redundant leftover Disp<N>.
1105         * i386-tlb.h: Re-generate.
1106
1107 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1108
1109         * riscv-opc.c (riscv_insn_types): New.
1110
1111 2018-03-13  Nick Clifton  <nickc@redhat.com>
1112
1113         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1114
1115 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1116
1117         * i386-opc.tbl: Add Optimize to clr.
1118         * i386-tbl.h: Regenerated.
1119
1120 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1121
1122         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1123         * i386-opc.h (OldGcc): Removed.
1124         (i386_opcode_modifier): Remove oldgcc.
1125         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1126         instructions for old (<= 2.8.1) versions of gcc.
1127         * i386-tbl.h: Regenerated.
1128
1129 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1130
1131         * i386-opc.h (EVEXDYN): New.
1132         * i386-opc.tbl: Fold various AVX512VL templates.
1133         * i386-tlb.h: Re-generate.
1134
1135 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1136
1137         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1138         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1139         vpexpandd, vpexpandq): Fold AFX512VF templates.
1140         * i386-tlb.h: Re-generate.
1141
1142 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1143
1144         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1145         Fold 128- and 256-bit VEX-encoded templates.
1146         * i386-tlb.h: Re-generate.
1147
1148 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1149
1150         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1151         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1152         vpexpandd, vpexpandq): Fold AVX512F templates.
1153         * i386-tlb.h: Re-generate.
1154
1155 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1156
1157         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1158         64-bit templates. Drop Disp<N>.
1159         * i386-tlb.h: Re-generate.
1160
1161 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1164         and 256-bit templates.
1165         * i386-tlb.h: Re-generate.
1166
1167 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1168
1169         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1170         * i386-tlb.h: Re-generate.
1171
1172 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1173
1174         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1175         Drop NoAVX.
1176         * i386-tlb.h: Re-generate.
1177
1178 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1179
1180         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1181         * i386-tlb.h: Re-generate.
1182
1183 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-gen.c (opcode_modifiers): Delete FloatD.
1186         * i386-opc.h (FloatD): Delete.
1187         (struct i386_opcode_modifier): Delete floatd.
1188         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1189         FloatD by D.
1190         * i386-tlb.h: Re-generate.
1191
1192 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1193
1194         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1195
1196 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1197
1198         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1199         * i386-tlb.h: Re-generate.
1200
1201 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1204         forms.
1205         * i386-tlb.h: Re-generate.
1206
1207 2018-03-07  Alan Modra  <amodra@gmail.com>
1208
1209         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1210         bfd_arch_rs6000.
1211         * disassemble.h (print_insn_rs6000): Delete.
1212         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1213         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1214         (print_insn_rs6000): Delete.
1215
1216 2018-03-03  Alan Modra  <amodra@gmail.com>
1217
1218         * sysdep.h (opcodes_error_handler): Define.
1219         (_bfd_error_handler): Declare.
1220         * Makefile.am: Remove stray #.
1221         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1222         EDIT" comment.
1223         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1224         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1225         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1226         opcodes_error_handler to print errors.  Standardize error messages.
1227         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1228         and include opintl.h.
1229         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1230         * i386-gen.c: Standardize error messages.
1231         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1232         * Makefile.in: Regenerate.
1233         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1234         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1235         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1236         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1237         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1238         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1239         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1240         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1241         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1242         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1243         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1244         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1245         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1246
1247 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1248
1249         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1250         vpsub[bwdq] instructions.
1251         * i386-tbl.h: Regenerated.
1252
1253 2018-03-01  Alan Modra  <amodra@gmail.com>
1254
1255         * configure.ac (ALL_LINGUAS): Sort.
1256         * configure: Regenerate.
1257
1258 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1259
1260         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1261         macro by assignements.
1262
1263 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1264
1265         PR gas/22871
1266         * i386-gen.c (opcode_modifiers): Add Optimize.
1267         * i386-opc.h (Optimize): New enum.
1268         (i386_opcode_modifier): Add optimize.
1269         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1270         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1271         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1272         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1273         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1274         vpxord and vpxorq.
1275         * i386-tbl.h: Regenerated.
1276
1277 2018-02-26  Alan Modra  <amodra@gmail.com>
1278
1279         * crx-dis.c (getregliststring): Allocate a large enough buffer
1280         to silence false positive gcc8 warning.
1281
1282 2018-02-22  Shea Levy <shea@shealevy.com>
1283
1284         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1285
1286 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1287
1288         * i386-opc.tbl: Add {rex},
1289         * i386-tbl.h: Regenerated.
1290
1291 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1292
1293         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1294         (mips16_opcodes): Replace `M' with `m' for "restore".
1295
1296 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1297
1298         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1299
1300 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1301
1302         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1303         variable to `function_index'.
1304
1305 2018-02-13  Nick Clifton  <nickc@redhat.com>
1306
1307         PR 22823
1308         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1309         about truncation of printing.
1310
1311 2018-02-12  Henry Wong <henry@stuffedcow.net>
1312
1313         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1314
1315 2018-02-05  Nick Clifton  <nickc@redhat.com>
1316
1317         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1318
1319 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1320
1321         * i386-dis.c (enum): Add pconfig.
1322         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1323         (cpu_flags): Add CpuPCONFIG.
1324         * i386-opc.h (enum): Add CpuPCONFIG.
1325         (i386_cpu_flags): Add cpupconfig.
1326         * i386-opc.tbl: Add PCONFIG instruction.
1327         * i386-init.h: Regenerate.
1328         * i386-tbl.h: Likewise.
1329
1330 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1331
1332         * i386-dis.c (enum): Add PREFIX_0F09.
1333         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1334         (cpu_flags): Add CpuWBNOINVD.
1335         * i386-opc.h (enum): Add CpuWBNOINVD.
1336         (i386_cpu_flags): Add cpuwbnoinvd.
1337         * i386-opc.tbl: Add WBNOINVD instruction.
1338         * i386-init.h: Regenerate.
1339         * i386-tbl.h: Likewise.
1340
1341 2018-01-17  Jim Wilson  <jimw@sifive.com>
1342
1343         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1344
1345 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1346
1347         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1348         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1349         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1350         (cpu_flags): Add CpuIBT, CpuSHSTK.
1351         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1352         (i386_cpu_flags): Add cpuibt, cpushstk.
1353         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1354         * i386-init.h: Regenerate.
1355         * i386-tbl.h: Likewise.
1356
1357 2018-01-16  Nick Clifton  <nickc@redhat.com>
1358
1359         * po/pt_BR.po: Updated Brazilian Portugese translation.
1360         * po/de.po: Updated German translation.
1361
1362 2018-01-15  Jim Wilson  <jimw@sifive.com>
1363
1364         * riscv-opc.c (match_c_nop): New.
1365         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1366
1367 2018-01-15  Nick Clifton  <nickc@redhat.com>
1368
1369         * po/uk.po: Updated Ukranian translation.
1370
1371 2018-01-13  Nick Clifton  <nickc@redhat.com>
1372
1373         * po/opcodes.pot: Regenerated.
1374
1375 2018-01-13  Nick Clifton  <nickc@redhat.com>
1376
1377         * configure: Regenerate.
1378
1379 2018-01-13  Nick Clifton  <nickc@redhat.com>
1380
1381         2.30 branch created.
1382
1383 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1384
1385         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1386         * i386-tbl.h: Regenerate.
1387
1388 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1389
1390         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1391         * i386-tbl.h: Re-generate.
1392
1393 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1394
1395         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1396         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1397         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1398         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1399         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1400         Disp8MemShift of AVX512VL forms.
1401         * i386-tbl.h: Re-generate.
1402
1403 2018-01-09  Jim Wilson  <jimw@sifive.com>
1404
1405         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1406         then the hi_addr value is zero.
1407
1408 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1409
1410         * arm-dis.c (arm_opcodes): Add csdb.
1411         (thumb32_opcodes): Add csdb.
1412
1413 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1414
1415         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1416         * aarch64-asm-2.c: Regenerate.
1417         * aarch64-dis-2.c: Regenerate.
1418         * aarch64-opc-2.c: Regenerate.
1419
1420 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1421
1422         PR gas/22681
1423         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1424         Remove AVX512 vmovd with 64-bit operands.
1425         * i386-tbl.h: Regenerated.
1426
1427 2018-01-05  Jim Wilson  <jimw@sifive.com>
1428
1429         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1430         jalr.
1431
1432 2018-01-03  Alan Modra  <amodra@gmail.com>
1433
1434         Update year range in copyright notice of all files.
1435
1436 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1437
1438         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1439         and OPERAND_TYPE_REGZMM entries.
1440
1441 For older changes see ChangeLog-2017
1442 \f
1443 Copyright (C) 2018 Free Software Foundation, Inc.
1444
1445 Copying and distribution of this file, with or without modification,
1446 are permitted in any medium without royalty provided the copyright
1447 notice and this notice are preserved.
1448
1449 Local Variables:
1450 mode: change-log
1451 left-margin: 8
1452 fill-column: 74
1453 version-control: never
1454 End: