opcodes/ChangeLog

   1 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
   4         matching for INSN2_SHORT_ONLY opcode table entries.
   5         * mips16-opc.c (SH): New macro.
   6         (mips16_opcodes): Set SH in `pinfo2' for non-extensible
   7         instruction entries: "nop", "addu", "and", "break", "cmp",
   8         "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
   9         "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
  10         "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
  11         "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
  12         "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
  13         "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
  14         "seh", "sew", "zeb", "zeh", "zew" and "extend".
  15
  16 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  17
  18         * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
  19         encoding support.
  20
  21 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  22
  23         * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
  24         "extend".
  25
  26 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  27
  28         * mips-dis.c (set_default_mips_dis_options): Use
  29         HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
  30         call to `bfd_mips_elf_get_abiflags'.
  31         * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
  32         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
  33         * aclocal.m4: Regenerate.
  34         * configure: Regenerate.
  35         * config.in: Regenerate.
  36         * Makefile.in: Regenerate.
  37
  38 2016-12-23  Tristan Gingold  <gingold@adacore.com>
  39
  40         * configure: Regenerate.
  41
  42 2016-12-23  Tristan Gingold  <gingold@adacore.com>
  43
  44         * po/opcodes.pot: Regenerate.
  45
  46 2016-12-21  Andrew Waterman  <andrew@sifive.com>
  47
  48         * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
  49
  50 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  51
  52         * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
  53         ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
  54         (print_insn_mips16): Check opcode entries for validity against
  55         the ISA level and ASE set selected.
  56
  57 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  58
  59         * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
  60         `insn' together, with `extend' as the high-order 16 bits.
  61         (match_kind): New enum.
  62         (print_insn_mips16): Rework for 32-bit instruction matching.
  63         Do not dump EXTEND prefixes here.
  64         * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
  65         Recode `match' and `mask' fields as 32-bit in absolute "jal" and
  66         "jalx" entries.
  67
  68 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  69
  70         * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
  71         than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
  72         INSN_MACRO entries.
  73
  74 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  75
  76         * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
  77         than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
  78         opcode).
  79
  80 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  81
  82         * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
  83         "*.aqrl".
  84
  85 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  86
  87         * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
  88         INSN_ALIAS.
  89
  90 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  91
  92         * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
  93         format.
  94
  95 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  96
  97         * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
  98         XLEN when none is provided.
  99
 100 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 101
 102         * riscv-opc.c: Formatting fixes.
 103
 104 2016-12-20  Alan Modra  <amodra@gmail.com>
 105
 106         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
 107         * Makefile.in: Regenerate.
 108         * po/POTFILES.in: Regenerate.
 109
 110 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
 111
 112         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
 113         Only examine ELF file structures here.
 114
 115 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
 116
 117         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
 118         `bfd_mips_elf_get_abiflags' here.
 119
 120 2016-12-16  Nick Clifton  <nickc@redhat.com>
 121
 122         * arm-dis.c (print_insn_thumb32): Fix compile time warning
 123         computing value_in_comment.
 124
 125 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 126
 127         * mips-dis.c (mips_convert_abiflags_ases): New function.
 128         (set_default_mips_dis_options): Also infer ASE flags from ELF
 129         file structures.
 130
 131 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 132
 133         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
 134         header flag interpretation code.
 135
 136 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 137
 138         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
 139         `pinfo2' with SP-relative "sd" entries.
 140
 141 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 142
 143         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
 144         compact jumps.
 145
 146 2016-12-13 Renlin Li <renlin.li@arm.com>
 147
 148         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
 149         qualifier.
 150         (operand_general_constraint_met_p): Remove case for CP_REG.
 151         (aarch64_print_operand): Print CRn, CRm operand using imm field.
 152         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
 153         (QL_SYSL): Likewise.
 154         (aarch64_opcode_table): Change CRn, CRm operand class and type.
 155         * aarch64-opc-2.c : Regenerate.
 156         * aarch64-asm-2.c : Likewise.
 157         * aarch64-dis-2.c : Likewise.
 158
 159 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 160
 161         * rx-dis.c: Include <setjmp.h>
 162         (struct private): New.
 163         (rx_get_byte): Check return value of read_memory_func, and
 164         call memory_error_func and OPCODES_SIGLONGJMP on error.
 165         (print_insn_rx): Call OPCODES_SIGSETJMP.
 166
 167 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 168
 169         * rl78-dis.c: Include <setjmp.h>.
 170         (struct private): New.
 171         (rl78_get_byte): Check return value of read_memory_func, and
 172         call memory_error_func and OPCODES_SIGLONGJMP on error.
 173         (print_insn_rl78_common): Call OPCODES_SIGJMP.
 174
 175 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 176
 177         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
 178
 179 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 180
 181         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
 182         than UINT.
 183
 184 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 185
 186         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
 187         to separate `extend' and its uninterpreted argument output.
 188         Separate hexadecimal halves of undecoded extended instructions
 189         output.
 190
 191 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 192
 193         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
 194         indentation space across.
 195
 196 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 197
 198         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
 199         adjustment for PC-relative operations following MIPS16e compact
 200         jumps or undefined RR/J(AL)R(C) encodings.
 201
 202 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 203
 204         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
 205         variable to `reglane_index'.
 206
 207 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
 208
 209         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 210
 211 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 212
 213         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 214
 215 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 216
 217         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 218         members.
 219
 220 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 221
 222         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 223
 224 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 225
 226         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 227         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 228
 229 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 230
 231         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 232
 233 2016-12-01  Nick Clifton  <nickc@redhat.com>
 234
 235         PR binutils/20893
 236         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 237         opcode designator.
 238
 239 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 240
 241         * arc-opc.c (insert_ra_chk): New function.
 242         (insert_rb_chk): Likewise.
 243         (insert_rad): Update text error message.
 244         (insert_rcd): Likewise.
 245         (insert_rhv2): Likewise.
 246         (insert_r0): Likewise.
 247         (insert_r1): Likewise.
 248         (insert_r2): Likewise.
 249         (insert_r3): Likewise.
 250         (insert_sp): Likewise.
 251         (insert_gp): Likewise.
 252         (insert_pcl): Likewise.
 253         (insert_blink): Likewise.
 254         (insert_ilink1): Likewise.
 255         (insert_ilink2): Likewise.
 256         (insert_ras): Likewise.
 257         (insert_rbs): Likewise.
 258         (insert_rcs): Likewise.
 259         (insert_simm3s): Likewise.
 260         (insert_rrange): Likewise.
 261         (insert_fpel): Likewise.
 262         (insert_blinkel): Likewise.
 263         (insert_pcel): Likewise.
 264         (insert_nps_3bit_dst): Likewise.
 265         (insert_nps_3bit_dst_short): Likewise.
 266         (insert_nps_3bit_src2_short): Likewise.
 267         (insert_nps_bitop_size_2b): Likewise.
 268         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 269         (RA_CHK): Define.
 270         (RB): Adjust.
 271         (RB_CHK): Define.
 272         (RC): Adjust.
 273         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 274         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 275         Change first insn argument to check for LP_COUNT usage.
 276         (rem): Likewise.
 277         (ld, ldd): All instructions are LOAD class.  Change first insn
 278         argument to check for LP_COUNT usage.
 279         (st, std): All instructions are STORE class.
 280         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 281         Change first insn argument to check for LP_COUNT usage.
 282         (mov): All instructions are MOVE class.  Change first insn
 283         argument to check for LP_COUNT usage.
 284
 285 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 286
 287         * arc-dis.c (is_compatible_p): Remove function.
 288         (skip_this_opcode): Don't add any decoding class to decode list.
 289         Remove warning.
 290         (find_format_from_table): Go through all opcodes, and warn if we
 291         use a guessed mnemonic.
 292
 293 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 294             Amit Pawar  <amit.pawar@amd.com>
 295
 296         PR binutils/20637
 297         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 298         instructions.
 299
 300 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 301
 302         * configure: Regenerate.
 303
 304 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 305
 306         * sparc-opc.c (HWS_V8): Definition moved from
 307         gas/config/tc-sparc.c.
 308         (HWS_V9): Likewise.
 309         (HWS_VA): Likewise.
 310         (HWS_VB): Likewise.
 311         (HWS_VC): Likewise.
 312         (HWS_VD): Likewise.
 313         (HWS_VE): Likewise.
 314         (HWS_VV): Likewise.
 315         (HWS_VM): Likewise.
 316         (HWS2_VM): Likewise.
 317         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 318         existing entries.
 319
 320 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 321
 322         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 323         instructions.
 324
 325 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 326
 327         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 328         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 329         (aarch64_opcode_table): Add fcmla and fcadd.
 330         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 331         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 332         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 333         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 334         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 335         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 336         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 337         (operand_general_constraint_met_p): Rotate and index range check.
 338         (aarch64_print_operand): Handle rotate operand.
 339         * aarch64-asm-2.c: Regenerate.
 340         * aarch64-dis-2.c: Likewise.
 341         * aarch64-opc-2.c: Likewise.
 342
 343 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 344
 345         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 346         * aarch64-asm-2.c: Regenerate.
 347         * aarch64-dis-2.c: Regenerate.
 348         * aarch64-opc-2.c: Regenerate.
 349
 350 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 351
 352         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 353         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 354         * aarch64-asm-2.c: Regenerate.
 355         * aarch64-dis-2.c: Regenerate.
 356         * aarch64-opc-2.c: Regenerate.
 357
 358 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 359
 360         * aarch64-tbl.h (QL_X1NIL): New.
 361         (arch64_opcode_table): Add ldraa, ldrab.
 362         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 363         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 364         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 365         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 366         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 367         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 368         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 369         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 370         (aarch64_print_operand): Likewise.
 371         * aarch64-asm-2.c: Regenerate.
 372         * aarch64-dis-2.c: Regenerate.
 373         * aarch64-opc-2.c: Regenerate.
 374
 375 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 376
 377         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 378         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 379         * aarch64-asm-2.c: Regenerate.
 380         * aarch64-dis-2.c: Regenerate.
 381         * aarch64-opc-2.c: Regenerate.
 382
 383 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 384
 385         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 386         (AARCH64_OPERANDS): Add Rm_SP.
 387         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 388         * aarch64-asm-2.c: Regenerate.
 389         * aarch64-dis-2.c: Regenerate.
 390         * aarch64-opc-2.c: Regenerate.
 391
 392 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 393
 394         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 395         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 396         autdzb, xpaci, xpacd.
 397         * aarch64-asm-2.c: Regenerate.
 398         * aarch64-dis-2.c: Regenerate.
 399         * aarch64-opc-2.c: Regenerate.
 400
 401 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 402
 403         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 404         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 405         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 406         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 407
 408 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 409
 410         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 411         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 412         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 413         autibsp.
 414         * aarch64-asm-2.c: Regenerate.
 415         * aarch64-dis-2.c: Regenerate.
 416
 417 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 418
 419         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 420
 421 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 422
 423         PR binutils/20799
 424         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 425         * i386-dis.c (EdqwS): Removed.
 426         (dqw_swap_mode): Likewise.
 427         (intel_operand_size): Don't check dqw_swap_mode.
 428         (OP_E_register): Likewise.
 429         (OP_E_memory): Likewise.
 430         (OP_G): Likewise.
 431         (OP_EX): Likewise.
 432         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 433         * i386-tbl.h: Regerated.
 434
 435 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 436
 437         * i386-opc.tbl: Merge AVX512F vmovq.
 438         * i386-tbl.h: Regerated.
 439
 440 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 441
 442         PR binutils/20701
 443         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 444         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 445         (three_byte_table): Remove THREE_BYTE_0F7A.
 446
 447 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         PR binutils/20775
 450         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 451         (FGRPd9_4): Replace 1 with 2.
 452         (FGRPd9_5): Replace 2 with 3.
 453         (FGRPd9_6): Replace 3 with 4.
 454         (FGRPd9_7): Replace 4 with 5.
 455         (FGRPda_5): Replace 5 with 6.
 456         (FGRPdb_4): Replace 6 with 7.
 457         (FGRPde_3): Replace 7 with 8.
 458         (FGRPdf_4): Replace 8 with 9.
 459         (fgrps): Add an entry for Bad_Opcode.
 460
 461 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 462
 463         * arc-opc.c (arc_flag_operands): Add F_DI14.
 464         (arc_flag_classes): Add C_DI14.
 465         * arc-nps400-tbl.h: Add new exc instructions.
 466
 467 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 468
 469         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 470         major opcode 0xa.
 471         * arc-nps-400-tbl.h: Add dcmac instruction.
 472         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 473         (insert_nps_rbdouble_64): Added.
 474         (extract_nps_rbdouble_64): Added.
 475         (insert_nps_proto_size): Added.
 476         (extract_nps_proto_size): Added.
 477
 478 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 479
 480         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 481         relating to long instruction processing, add new limm field.
 482         (OPCODE): Rename to...
 483         (OPCODE_32BIT_INSN): ...this.
 484         (OPCODE_AC): Delete.
 485         (skip_this_opcode): Handle different instruction lengths, update
 486         macro name.
 487         (special_flag_p): Update parameter type.
 488         (find_format_from_table): Update for more instruction lengths.
 489         (find_format_long_instructions): Delete.
 490         (find_format): Update for more instruction lengths.
 491         (arc_insn_length): Likewise.
 492         (extract_operand_value): Update for more instruction lengths.
 493         (operand_iterator_next): Remove code relating to long
 494         instructions.
 495         (arc_opcode_to_insn_type): New function.
 496         (print_insn_arc):Update for more instructions lengths.
 497         * arc-ext.c (extInstruction_t): Change argument type.
 498         * arc-ext.h (extInstruction_t): Change argument type.
 499         * arc-fxi.h: Change type unsigned to unsigned long long
 500         extensively throughout.
 501         * arc-nps400-tbl.h: Add long instructions taken from
 502         arc_long_opcodes table in arc-opc.c.
 503         * arc-opc.c: Update parameter types on insert/extract handlers.
 504         (arc_long_opcodes): Delete.
 505         (arc_num_long_opcodes): Delete.
 506         (arc_opcode_len): Update for more instruction lengths.
 507
 508 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 509
 510         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 511
 512 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 513
 514         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 515         with arc_opcode_len.
 516         (find_format_long_instructions): Likewise.
 517         * arc-opc.c (arc_opcode_len): New function.
 518
 519 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 520
 521         * arc-nps400-tbl.h: Fix some instruction masks.
 522
 523 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 524
 525         * i386-dis.c (REG_82): Removed.
 526         (X86_64_82_REG_0): Likewise.
 527         (X86_64_82_REG_1): Likewise.
 528         (X86_64_82_REG_2): Likewise.
 529         (X86_64_82_REG_3): Likewise.
 530         (X86_64_82_REG_4): Likewise.
 531         (X86_64_82_REG_5): Likewise.
 532         (X86_64_82_REG_6): Likewise.
 533         (X86_64_82_REG_7): Likewise.
 534         (X86_64_82): New.
 535         (dis386): Use X86_64_82 instead of REG_82.
 536         (reg_table): Remove REG_82.
 537         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 538         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 539         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 540         X86_64_82_REG_7.
 541
 542 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 543
 544         PR binutils/20754
 545         * i386-dis.c (REG_82): New.
 546         (X86_64_82_REG_0): Likewise.
 547         (X86_64_82_REG_1): Likewise.
 548         (X86_64_82_REG_2): Likewise.
 549         (X86_64_82_REG_3): Likewise.
 550         (X86_64_82_REG_4): Likewise.
 551         (X86_64_82_REG_5): Likewise.
 552         (X86_64_82_REG_6): Likewise.
 553         (X86_64_82_REG_7): Likewise.
 554         (dis386): Use REG_82.
 555         (reg_table): Add REG_82.
 556         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 557         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 558         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 559
 560 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 561
 562         * i386-dis.c (REG_82): Renamed to ...
 563         (REG_83): This.
 564         (dis386): Updated.
 565         (reg_table): Likewise.
 566
 567 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 568
 569         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 570         * i386-dis-evex.h (evex_table): Updated.
 571         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 572         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 573         (cpu_flags): Add CpuAVX512_4VNNIW.
 574         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 575         (i386_cpu_flags): Add cpuavx512_4vnniw.
 576         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 577         * i386-init.h: Regenerate.
 578         * i386-tbl.h: Ditto.
 579
 580 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 581
 582         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 583         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 584         * i386-dis-evex.h (evex_table): Updated.
 585         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 586         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 587         (cpu_flags): Add CpuAVX512_4FMAPS.
 588         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 589         * i386-opc.h (AVX512_4FMAP): New.
 590         (i386_cpu_flags): Add cpuavx512_4fmaps.
 591         (ImplicitQuadGroup): New.
 592         (i386_opcode_modifier): Add implicitquadgroup.
 593         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 594         * i386-init.h: Regenerate.
 595         * i386-tbl.h: Ditto.
 596
 597 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 598             Andrew Waterman <andrew@sifive.com>
 599
 600         Add support for RISC-V architecture.
 601         * configure.ac: Add entry for bfd_riscv_arch.
 602         * configure: Regenerate.
 603         * disassemble.c (disassembler): Add support for riscv.
 604         (disassembler_usage): Likewise.
 605         * riscv-dis.c: New file.
 606         * riscv-opc.c: New file.
 607
 608 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 609
 610         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 611         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 612         (rm_table): Update the RM_0FAE_REG_7 entry.
 613         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 614         (cpu_flags): Remove CpuPCOMMIT.
 615         * i386-opc.h (CpuPCOMMIT): Removed.
 616         (i386_cpu_flags): Remove cpupcommit.
 617         * i386-opc.tbl: Remove pcommit.
 618         * i386-init.h: Regenerated.
 619         * i386-tbl.h: Likewise.
 620
 621 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 622
 623         PR binutis/20705
 624         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 625         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 626         32-bit mode.  Don't check vex.register_specifier in 32-bit
 627         mode.
 628         (OP_VEX): Check for invalid mask registers.
 629
 630 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 631
 632         PR binutis/20699
 633         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 634         sizeflag.
 635
 636 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 637
 638         PR binutis/20704
 639         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 640
 641 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 642
 643         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 644         local variable to `index_regno'.
 645
 646 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 647
 648         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 649
 650 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 651
 652         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 653         usage on ISA basis.
 654
 655 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 656
 657         PR target/20666
 658         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 659
 660 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 661
 662         PR target/20667
 663         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 664         available.
 665
 666 2016-10-07  Alan Modra  <amodra@gmail.com>
 667
 668         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 669
 670 2016-10-06  Alan Modra  <amodra@gmail.com>
 671
 672         * aarch64-opc.c: Spell fall through comments consistently.
 673         * i386-dis.c: Likewise.
 674         * aarch64-dis.c: Add missing fall through comments.
 675         * aarch64-opc.c: Likewise.
 676         * arc-dis.c: Likewise.
 677         * arm-dis.c: Likewise.
 678         * i386-dis.c: Likewise.
 679         * m68k-dis.c: Likewise.
 680         * mep-asm.c: Likewise.
 681         * ns32k-dis.c: Likewise.
 682         * sh-dis.c: Likewise.
 683         * tic4x-dis.c: Likewise.
 684         * tic6x-dis.c: Likewise.
 685         * vax-dis.c: Likewise.
 686
 687 2016-10-06  Alan Modra  <amodra@gmail.com>
 688
 689         * arc-ext.c (create_map): Add missing break.
 690         * msp430-decode.opc (encode_as): Likewise.
 691         * msp430-decode.c: Regenerate.
 692
 693 2016-10-06  Alan Modra  <amodra@gmail.com>
 694
 695         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 696         * crx-dis.c (print_insn_crx): Likewise.
 697
 698 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 699
 700         PR binutils/20657
 701         * i386-dis.c (putop): Don't assign alt twice.
 702
 703 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 704
 705         PR target/20553
 706         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 707
 708 2016-09-29  Alan Modra  <amodra@gmail.com>
 709
 710         * ppc-opc.c (L): Make compulsory.
 711         (LOPT): New, optional form of L.
 712         (HTM_R): Define as LOPT.
 713         (L0, L1): Delete.
 714         (L32OPT): New, optional for 32-bit L.
 715         (L2OPT): New, 2-bit L for dcbf.
 716         (SVC_LEC): Update.
 717         (L2): Define.
 718         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 719         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 720         <dcbf>: Use L2OPT.
 721         <tlbiel, tlbie>: Use LOPT.
 722         <wclr, wclrall>: Use L2.
 723
 724 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 725
 726         * Makefile.in: Regenerate.
 727         * configure: Likewise.
 728
 729 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 730
 731         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 732         (EXTINSN2OP): Use EXTINSN2OPF.
 733         (bspeekm, bspop, modapp): New extension instructions.
 734         * arc-opc.c (F_DNZ_ND): Define.
 735         (F_DNZ_D): Likewise.
 736         (F_SIZEB1): Changed.
 737         (C_DNZ_D): Define.
 738         (C_HARD): Changed.
 739         * arc-tbl.h (dbnz): New instruction.
 740         (prealloc): Allow it for ARC EM.
 741         (xbfu): Likewise.
 742
 743 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 744
 745         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 746         after commas in addresses.
 747         (aarch64_print_operand): Likewise.
 748
 749 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 750
 751         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 752         rather than "should be" or "expected to be" in error messages.
 753
 754 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 755
 756         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 757         (print_mnemonic_name): ...here.
 758         (print_comment): New function.
 759         (print_aarch64_insn): Call it.
 760         * aarch64-opc.c (aarch64_conds): Add SVE names.
 761         (aarch64_print_operand): Print alternative condition names in
 762         a comment.
 763
 764 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 765
 766         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 767         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 768         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 769         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 770         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 771         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 772         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 773         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 774         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 775         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 776         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 777         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 778         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 779         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 780         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 781         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 782         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 783         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 784         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 785         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 786         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 787         (aarch64_feature_sve): New variable.
 788         (SVE): New macro.
 789         (_SVE_INSN): Likewise.
 790         (aarch64_opcode_table): Add SVE instructions.
 791         * aarch64-opc.h (extract_fields): Declare.
 792         * aarch64-opc-2.c: Regenerate.
 793         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 794         * aarch64-asm-2.c: Regenerate.
 795         * aarch64-dis.c (extract_fields): Make global.
 796         (do_misc_decoding): Handle the new SVE aarch64_ops.
 797         * aarch64-dis-2.c: Regenerate.
 798
 799 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 800
 801         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 802         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 803         aarch64_field_kinds.
 804         * aarch64-opc.c (fields): Add corresponding entries.
 805         * aarch64-asm.c (aarch64_get_variant): New function.
 806         (aarch64_encode_variant_using_iclass): Likewise.
 807         (aarch64_opcode_encode): Call it.
 808         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 809         (aarch64_opcode_decode): Call it.
 810
 811 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 812
 813         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 814         and FP register operands.
 815         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 816         (FLD_SVE_Vn): New aarch64_field_kinds.
 817         * aarch64-opc.c (fields): Add corresponding entries.
 818         (aarch64_print_operand): Handle the new SVE core and FP register
 819         operands.
 820         * aarch64-opc-2.c: Regenerate.
 821         * aarch64-asm-2.c: Likewise.
 822         * aarch64-dis-2.c: Likewise.
 823
 824 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 825
 826         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 827         immediate operands.
 828         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 829         * aarch64-opc.c (fields): Add corresponding entry.
 830         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 831         operands.
 832         (aarch64_print_operand): Likewise.
 833         * aarch64-opc-2.c: Regenerate.
 834         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 835         (ins_sve_float_zero_one): New inserters.
 836         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 837         (aarch64_ins_sve_float_half_two): Likewise.
 838         (aarch64_ins_sve_float_zero_one): Likewise.
 839         * aarch64-asm-2.c: Regenerate.
 840         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 841         (ext_sve_float_zero_one): New extractors.
 842         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 843         (aarch64_ext_sve_float_half_two): Likewise.
 844         (aarch64_ext_sve_float_zero_one): Likewise.
 845         * aarch64-dis-2.c: Regenerate.
 846
 847 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 848
 849         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 850         integer immediate operands.
 851         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 852         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 853         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 854         * aarch64-opc.c (fields): Add corresponding entries.
 855         (operand_general_constraint_met_p): Handle the new SVE integer
 856         immediate operands.
 857         (aarch64_print_operand): Likewise.
 858         (aarch64_sve_dupm_mov_immediate_p): New function.
 859         * aarch64-opc-2.c: Regenerate.
 860         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 861         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 862         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 863         (aarch64_ins_limm): ...here.
 864         (aarch64_ins_inv_limm): New function.
 865         (aarch64_ins_sve_aimm): Likewise.
 866         (aarch64_ins_sve_asimm): Likewise.
 867         (aarch64_ins_sve_limm_mov): Likewise.
 868         (aarch64_ins_sve_shlimm): Likewise.
 869         (aarch64_ins_sve_shrimm): Likewise.
 870         * aarch64-asm-2.c: Regenerate.
 871         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 872         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 873         * aarch64-dis.c (decode_limm): New function, split out from...
 874         (aarch64_ext_limm): ...here.
 875         (aarch64_ext_inv_limm): New function.
 876         (decode_sve_aimm): Likewise.
 877         (aarch64_ext_sve_aimm): Likewise.
 878         (aarch64_ext_sve_asimm): Likewise.
 879         (aarch64_ext_sve_limm_mov): Likewise.
 880         (aarch64_top_bit): Likewise.
 881         (aarch64_ext_sve_shlimm): Likewise.
 882         (aarch64_ext_sve_shrimm): Likewise.
 883         * aarch64-dis-2.c: Regenerate.
 884
 885 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 886
 887         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 888         operands.
 889         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 890         the AARCH64_MOD_MUL_VL entry.
 891         (value_aligned_p): Cope with non-power-of-two alignments.
 892         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 893         (print_immediate_offset_address): Likewise.
 894         (aarch64_print_operand): Likewise.
 895         * aarch64-opc-2.c: Regenerate.
 896         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 897         (ins_sve_addr_ri_s9xvl): New inserters.
 898         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 899         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 900         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 901         * aarch64-asm-2.c: Regenerate.
 902         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 903         (ext_sve_addr_ri_s9xvl): New extractors.
 904         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 905         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 906         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 907         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 908         * aarch64-dis-2.c: Regenerate.
 909
 910 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 911
 912         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 913         address operands.
 914         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 915         (FLD_SVE_xs_22): New aarch64_field_kinds.
 916         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 917         (get_operand_specific_data): New function.
 918         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 919         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 920         (operand_general_constraint_met_p): Handle the new SVE address
 921         operands.
 922         (sve_reg): New array.
 923         (get_addr_sve_reg_name): New function.
 924         (aarch64_print_operand): Handle the new SVE address operands.
 925         * aarch64-opc-2.c: Regenerate.
 926         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 927         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 928         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 929         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 930         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 931         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 932         (aarch64_ins_sve_addr_zi_u5): Likewise.
 933         (aarch64_ins_sve_addr_zz): Likewise.
 934         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 935         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 936         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 937         * aarch64-asm-2.c: Regenerate.
 938         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 939         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 940         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 941         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 942         (aarch64_ext_sve_addr_ri_u6): Likewise.
 943         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 944         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 945         (aarch64_ext_sve_addr_zi_u5): Likewise.
 946         (aarch64_ext_sve_addr_zz): Likewise.
 947         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 948         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 949         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 950         * aarch64-dis-2.c: Regenerate.
 951
 952 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 953
 954         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 955         AARCH64_OPND_SVE_PATTERN_SCALED.
 956         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 957         * aarch64-opc.c (fields): Add a corresponding entry.
 958         (set_multiplier_out_of_range_error): New function.
 959         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 960         (operand_general_constraint_met_p): Handle
 961         AARCH64_OPND_SVE_PATTERN_SCALED.
 962         (print_register_offset_address): Use PRIi64 to print the
 963         shift amount.
 964         (aarch64_print_operand): Likewise.  Handle
 965         AARCH64_OPND_SVE_PATTERN_SCALED.
 966         * aarch64-opc-2.c: Regenerate.
 967         * aarch64-asm.h (ins_sve_scale): New inserter.
 968         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 969         * aarch64-asm-2.c: Regenerate.
 970         * aarch64-dis.h (ext_sve_scale): New inserter.
 971         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 972         * aarch64-dis-2.c: Regenerate.
 973
 974 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 975
 976         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 977         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 978         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 979         (FLD_SVE_prfop): Likewise.
 980         * aarch64-opc.c: Include libiberty.h.
 981         (aarch64_sve_pattern_array): New variable.
 982         (aarch64_sve_prfop_array): Likewise.
 983         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 984         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 985         AARCH64_OPND_SVE_PRFOP.
 986         * aarch64-asm-2.c: Regenerate.
 987         * aarch64-dis-2.c: Likewise.
 988         * aarch64-opc-2.c: Likewise.
 989
 990 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 991
 992         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 993         AARCH64_OPND_QLF_P_[ZM].
 994         (aarch64_print_operand): Print /z and /m where appropriate.
 995
 996 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 997
 998         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 999         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
1000         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
1001         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
1002         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
1003         * aarch64-opc.c (fields): Add corresponding entries here.
1004         (operand_general_constraint_met_p): Check that SVE register lists
1005         have the correct length.  Check the ranges of SVE index registers.
1006         Check for cases where p8-p15 are used in 3-bit predicate fields.
1007         (aarch64_print_operand): Handle the new SVE operands.
1008         * aarch64-opc-2.c: Regenerate.
1009         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
1010         * aarch64-asm.c (aarch64_ins_sve_index): New function.
1011         (aarch64_ins_sve_reglist): Likewise.
1012         * aarch64-asm-2.c: Regenerate.
1013         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
1014         * aarch64-dis.c (aarch64_ext_sve_index): New function.
1015         (aarch64_ext_sve_reglist): Likewise.
1016         * aarch64-dis-2.c: Regenerate.
1017
1018 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1019
1020         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1021         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1022         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1023         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1024         tied operands.
1025
1026 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1027
1028         * aarch64-opc.c (get_offset_int_reg_name): New function.
1029         (print_immediate_offset_address): Likewise.
1030         (print_register_offset_address): Take the base and offset
1031         registers as parameters.
1032         (aarch64_print_operand): Update caller accordingly.  Use
1033         print_immediate_offset_address.
1034
1035 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1036
1037         * aarch64-opc.c (BANK): New macro.
1038         (R32, R64): Take a register number as argument
1039         (int_reg): Use BANK.
1040
1041 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1042
1043         * aarch64-opc.c (print_register_list): Add a prefix parameter.
1044         (aarch64_print_operand): Update accordingly.
1045
1046 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1047
1048         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1049         for FPIMM.
1050         * aarch64-asm.h (ins_fpimm): New inserter.
1051         * aarch64-asm.c (aarch64_ins_fpimm): New function.
1052         * aarch64-asm-2.c: Regenerate.
1053         * aarch64-dis.h (ext_fpimm): New extractor.
1054         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1055         (aarch64_ext_fpimm): New function.
1056         * aarch64-dis-2.c: Regenerate.
1057
1058 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1059
1060         * aarch64-asm.c: Include libiberty.h.
1061         (insert_fields): New function.
1062         (aarch64_ins_imm): Use it.
1063         * aarch64-dis.c (extract_fields): New function.
1064         (aarch64_ext_imm): Use it.
1065
1066 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1067
1068         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1069         with an esize parameter.
1070         (operand_general_constraint_met_p): Update accordingly.
1071         Fix misindented code.
1072         * aarch64-asm.c (aarch64_ins_limm): Update call to
1073         aarch64_logical_immediate_p.
1074
1075 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1076
1077         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1078
1079 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1080
1081         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1082
1083 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
1084
1085         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1086
1087 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
1088
1089         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1090         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1091         xor3>: Delete mnemonics.
1092         <cp_abort>: Rename mnemonic from ...
1093         <cpabort>: ...to this.
1094         <setb>: Change to a X form instruction.
1095         <sync>: Change to 1 operand form.
1096         <copy>: Delete mnemonic.
1097         <copy_first>: Rename mnemonic from ...
1098         <copy>: ...to this.
1099         <paste, paste.>: Delete mnemonics.
1100         <paste_last>: Rename mnemonic from ...
1101         <paste.>: ...to this.
1102
1103 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1104
1105         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1106
1107 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1108
1109         * s390-mkopc.c (main): Support alternate arch strings.
1110
1111 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1112
1113         * s390-opc.txt: Fix kmctr instruction type.
1114
1115 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1116
1117         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1118         * i386-init.h: Regenerated.
1119
1120 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1121
1122         * opcodes/arc-dis.c (print_insn_arc): Changed.
1123
1124 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1125
1126         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1127         camellia_fl.
1128
1129 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1130
1131         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1132         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1133         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1134
1135 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1136
1137         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1138         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1139         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1140         PREFIX_MOD_3_0FAE_REG_4.
1141         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1142         PREFIX_MOD_3_0FAE_REG_4.
1143         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1144         (cpu_flags): Add CpuPTWRITE.
1145         * i386-opc.h (CpuPTWRITE): New.
1146         (i386_cpu_flags): Add cpuptwrite.
1147         * i386-opc.tbl: Add ptwrite instruction.
1148         * i386-init.h: Regenerated.
1149         * i386-tbl.h: Likewise.
1150
1151 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1152
1153         * arc-dis.h: Wrap around in extern "C".
1154
1155 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1156
1157         * aarch64-tbl.h (V8_2_INSN): New macro.
1158         (aarch64_opcode_table): Use it.
1159
1160 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1161
1162         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1163         CORE_INSN, __FP_INSN and SIMD_INSN.
1164
1165 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1166
1167         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1168         (aarch64_opcode_table): Update uses accordingly.
1169
1170 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1171         Kwok Cheung Yeung  <kcy@codesourcery.com>
1172
1173         opcodes/
1174         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1175         'e_cmplwi' to 'e_cmpli' instead.
1176         (OPVUPRT, OPVUPRT_MASK): Define.
1177         (powerpc_opcodes): Add E200Z4 insns.
1178         (vle_opcodes): Add context save/restore insns.
1179
1180 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1181
1182         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1183         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1184         "j".
1185
1186 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1187
1188         * arc-nps400-tbl.h: Change block comments to GNU format.
1189         * arc-dis.c: Add new globals addrtypenames,
1190         addrtypenames_max, and addtypeunknown.
1191         (get_addrtype): New function.
1192         (print_insn_arc): Print colons and address types when
1193         required.
1194         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1195         define insert and extract functions for all address types.
1196         (arc_operands): Add operands for colon and all address
1197         types.
1198         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1199         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1200         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1201         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1202         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1203         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1204
1205 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1206
1207         * configure: Regenerated.
1208
1209 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1210
1211         * arc-dis.c (skipclass): New structure.
1212         (decodelist): New variable.
1213         (is_compatible_p): New function.
1214         (new_element): Likewise.
1215         (skip_class_p): Likewise.
1216         (find_format_from_table): Use skip_class_p function.
1217         (find_format): Decode first the extension instructions.
1218         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1219         e_flags.
1220         (parse_option): New function.
1221         (parse_disassembler_options): Likewise.
1222         (print_arc_disassembler_options): Likewise.
1223         (print_insn_arc): Use parse_disassembler_options function.  Proper
1224         select ARCv2 cpu variant.
1225         * disassemble.c (disassembler_usage): Add ARC disassembler
1226         options.
1227
1228 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1229
1230         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1231         annotation from the "nal" entry and reorder it beyond "bltzal".
1232
1233 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1234
1235         * sparc-opc.c (ldtxa): New macro.
1236         (sparc_opcodes): Use the macro defined above to add entries for
1237         the LDTXA instructions.
1238         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1239         instruction.
1240
1241 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1242
1243         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1244         and "jmpc".
1245
1246 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1247
1248         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1249         (movzb): Adjust to cover all permitted suffixes.
1250         (movzw): New.
1251         * i386-tbl.h: Re-generate.
1252
1253 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1256         (lgdt): Remove Tbyte from non-64-bit variant.
1257         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1258         xsaves64, xsavec64): Remove Disp16.
1259         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1260         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1261         64-bit variants.
1262         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1263         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1264         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1265         64-bit variants.
1266         * i386-tbl.h: Re-generate.
1267
1268 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1269
1270         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1271         * i386-tbl.h: Re-generate.
1272
1273 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1274
1275         * arm-dis.c (print_insn): Fix typo in comment.
1276
1277 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1278
1279         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1280         range of ldst_elemlist operands.
1281         (print_register_list): Use PRIi64 to print the index.
1282         (aarch64_print_operand): Likewise.
1283
1284 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1285
1286         * mcore-opc.h: Remove sentinal.
1287         * mcore-dis.c (print_insn_mcore): Adjust.
1288
1289 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1290
1291         * arc-opc.c: Correct description of availability of NPS400
1292         features.
1293
1294 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1295
1296         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1297         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1298         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1299         xor3>: New mnemonics.
1300         <setb>: Change to a VX form instruction.
1301         (insert_sh6): Add support for rldixor.
1302         (extract_sh6): Likewise.
1303
1304 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1305
1306         * arc-ext.h: Wrap in extern C.
1307
1308 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1309
1310         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1311         Use same method for determining instruction length on ARC700 and
1312         NPS-400.
1313         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1314         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1315         with the NPS400 subclass.
1316         * arc-opc.c: Likewise.
1317
1318 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1319
1320         * sparc-opc.c (rdasr): New macro.
1321         (wrasr): Likewise.
1322         (rdpr): Likewise.
1323         (wrpr): Likewise.
1324         (rdhpr): Likewise.
1325         (wrhpr): Likewise.
1326         (sparc_opcodes): Use the macros above to fix and expand the
1327         definition of read/write instructions from/to
1328         asr/privileged/hyperprivileged instructions.
1329         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1330         %hva_mask_nz.  Prefer softint_set and softint_clear over
1331         set_softint and clear_softint.
1332         (print_insn_sparc): Support %ver in Rd.
1333
1334 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1335
1336         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1337         architecture according to the hardware capabilities they require.
1338
1339 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1340
1341         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1342         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1343         bfd_mach_sparc_v9{c,d,e,v,m}.
1344         * sparc-opc.c (MASK_V9C): Define.
1345         (MASK_V9D): Likewise.
1346         (MASK_V9E): Likewise.
1347         (MASK_V9V): Likewise.
1348         (MASK_V9M): Likewise.
1349         (v6): Add MASK_V9{C,D,E,V,M}.
1350         (v6notlet): Likewise.
1351         (v7): Likewise.
1352         (v8): Likewise.
1353         (v9): Likewise.
1354         (v9andleon): Likewise.
1355         (v9a): Likewise.
1356         (v9b): Likewise.
1357         (v9c): Define.
1358         (v9d): Likewise.
1359         (v9e): Likewise.
1360         (v9v): Likewise.
1361         (v9m): Likewise.
1362         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1363
1364 2016-06-15  Nick Clifton  <nickc@redhat.com>
1365
1366         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1367         constants to match expected behaviour.
1368         (nds32_parse_opcode): Likewise.  Also for whitespace.
1369
1370 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1371
1372         * arc-opc.c (extract_rhv1): Extract value from insn.
1373
1374 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1375
1376         * arc-nps400-tbl.h: Add ldbit instruction.
1377         * arc-opc.c: Add flag classes required for ldbit.
1378
1379 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1380
1381         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1382         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1383         support the above instructions.
1384
1385 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1386
1387         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1388         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1389         csma, cbba, zncv, and hofs.
1390         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1391         support the above instructions.
1392
1393 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1394
1395         * arc-nps400-tbl.h: Add andab and orab instructions.
1396
1397 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1398
1399         * arc-nps400-tbl.h: Add addl-like instructions.
1400
1401 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1402
1403         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1404
1405 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1406
1407         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1408         instructions.
1409
1410 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1411
1412         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1413         variable.
1414         (init_disasm): Handle new command line option "insnlength".
1415         (print_s390_disassembler_options): Mention new option in help
1416         output.
1417         (print_insn_s390): Use the encoded insn length when dumping
1418         unknown instructions.
1419
1420 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1421
1422         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1423          to the address and set as symbol address for LDS/ STS immediate operands.
1424
1425 2016-06-07  Alan Modra  <amodra@gmail.com>
1426
1427         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1428         cpu for "vle" to e500.
1429         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1430         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1431         (PPCNONE): Delete, substitute throughout.
1432         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1433         except for major opcode 4 and 31.
1434         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1435
1436 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1437
1438         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1439         ARM_EXT_RAS in relevant entries.
1440
1441 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1442
1443         PR binutils/20196
1444         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1445         opcodes for E6500.
1446
1447 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1448
1449         PR binutis/18386
1450         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1451         (indir_v_mode): New.
1452         Add comments for '&'.
1453         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1454         (putop): Handle '&'.
1455         (intel_operand_size): Handle indir_v_mode.
1456         (OP_E_register): Likewise.
1457         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1458         64-bit indirect call/jmp for AMD64.
1459         * i386-tbl.h: Regenerated
1460
1461 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1462
1463         * arc-dis.c (struct arc_operand_iterator): New structure.
1464         (find_format_from_table): All the old content from find_format,
1465         with some minor adjustments, and parameter renaming.
1466         (find_format_long_instructions): New function.
1467         (find_format): Rewritten.
1468         (arc_insn_length): Add LSB parameter.
1469         (extract_operand_value): New function.
1470         (operand_iterator_next): New function.
1471         (print_insn_arc): Use new functions to find opcode, and iterator
1472         over operands.
1473         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1474         (extract_nps_3bit_dst_short): New function.
1475         (insert_nps_3bit_src2_short): New function.
1476         (extract_nps_3bit_src2_short): New function.
1477         (insert_nps_bitop1_size): New function.
1478         (extract_nps_bitop1_size): New function.
1479         (insert_nps_bitop2_size): New function.
1480         (extract_nps_bitop2_size): New function.
1481         (insert_nps_bitop_mod4_msb): New function.
1482         (extract_nps_bitop_mod4_msb): New function.
1483         (insert_nps_bitop_mod4_lsb): New function.
1484         (extract_nps_bitop_mod4_lsb): New function.
1485         (insert_nps_bitop_dst_pos3_pos4): New function.
1486         (extract_nps_bitop_dst_pos3_pos4): New function.
1487         (insert_nps_bitop_ins_ext): New function.
1488         (extract_nps_bitop_ins_ext): New function.
1489         (arc_operands): Add new operands.
1490         (arc_long_opcodes): New global array.
1491         (arc_num_long_opcodes): New global.
1492         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1493
1494 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1495
1496         * nds32-asm.h: Add extern "C".
1497         * sh-opc.h: Likewise.
1498
1499 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1500
1501         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1502         0,b,limm to the rflt instruction.
1503
1504 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1505
1506         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1507         constant.
1508
1509 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1510
1511         PR gas/20145
1512         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1513         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1514         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1515         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1516         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1517         * i386-init.h: Regenerated.
1518
1519 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1520
1521         PR gas/20145
1522         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1523         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1524         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1525         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1526         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1527         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1528         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1529         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1530         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1531         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1532         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1533         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1534         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1535         CpuRegMask for AVX512.
1536         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1537         and CpuRegMask.
1538         (set_bitfield_from_cpu_flag_init): New function.
1539         (set_bitfield): Remove const on f.  Call
1540         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1541         * i386-opc.h (CpuRegMMX): New.
1542         (CpuRegXMM): Likewise.
1543         (CpuRegYMM): Likewise.
1544         (CpuRegZMM): Likewise.
1545         (CpuRegMask): Likewise.
1546         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1547         and cpuregmask.
1548         * i386-init.h: Regenerated.
1549         * i386-tbl.h: Likewise.
1550
1551 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1552
1553         PR gas/20154
1554         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1555         (opcode_modifiers): Add AMD64 and Intel64.
1556         (main): Properly verify CpuMax.
1557         * i386-opc.h (CpuAMD64): Removed.
1558         (CpuIntel64): Likewise.
1559         (CpuMax): Set to CpuNo64.
1560         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1561         (AMD64): New.
1562         (Intel64): Likewise.
1563         (i386_opcode_modifier): Add amd64 and intel64.
1564         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1565         on call and jmp.
1566         * i386-init.h: Regenerated.
1567         * i386-tbl.h: Likewise.
1568
1569 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1570
1571         PR gas/20154
1572         * i386-gen.c (main): Fail if CpuMax is incorrect.
1573         * i386-opc.h (CpuMax): Set to CpuIntel64.
1574         * i386-tbl.h: Regenerated.
1575
1576 2016-05-27  Nick Clifton  <nickc@redhat.com>
1577
1578         PR target/20150
1579         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1580         (msp430dis_opcode_unsigned): New function.
1581         (msp430dis_opcode_signed): New function.
1582         (msp430_singleoperand): Use the new opcode reading functions.
1583         Only disassenmble bytes if they were successfully read.
1584         (msp430_doubleoperand): Likewise.
1585         (msp430_branchinstr): Likewise.
1586         (msp430x_callx_instr): Likewise.
1587         (print_insn_msp430): Check that it is safe to read bytes before
1588         attempting disassembly.  Use the new opcode reading functions.
1589
1590 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1591
1592         * ppc-opc.c (CY): New define.  Document it.
1593         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1594
1595 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1596
1597         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1598         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1599         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1600         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1601         CPU_ANY_AVX_FLAGS.
1602         * i386-init.h: Regenerated.
1603
1604 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1605
1606         PR gas/20141
1607         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1608         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1609         * i386-init.h: Regenerated.
1610
1611 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1612
1613         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1614         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1615         * i386-init.h: Regenerated.
1616
1617 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1618
1619         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1620         information.
1621         (print_insn_arc): Set insn_type information.
1622         * arc-opc.c (C_CC): Add F_CLASS_COND.
1623         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1624         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1625         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1626         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1627         (brne, brne_s, jeq_s, jne_s): Likewise.
1628
1629 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1630
1631         * arc-tbl.h (neg): New instruction variant.
1632
1633 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1634
1635         * arc-dis.c (find_format, find_format, get_auxreg)
1636         (print_insn_arc): Changed.
1637         * arc-ext.h (INSERT_XOP): Likewise.
1638
1639 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1640
1641         * tic54x-dis.c (sprint_mmr): Adjust.
1642         * tic54x-opc.c: Likewise.
1643
1644 2016-05-19  Alan Modra  <amodra@gmail.com>
1645
1646         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1647
1648 2016-05-19  Alan Modra  <amodra@gmail.com>
1649
1650         * ppc-opc.c: Formatting.
1651         (NSISIGNOPT): Define.
1652         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1653
1654 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1655
1656         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1657         replacing references to `micromips_ase' throughout.
1658         (_print_insn_mips): Don't use file-level microMIPS annotation to
1659         determine the disassembly mode with the symbol table.
1660
1661 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1662
1663         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1664
1665 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1666
1667         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1668         mips64r6.
1669         * mips-opc.c (D34): New macro.
1670         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1671
1672 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1673
1674         * i386-dis.c (prefix_table): Add RDPID instruction.
1675         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1676         (cpu_flags): Add RDPID bitfield.
1677         * i386-opc.h (enum): Add RDPID element.
1678         (i386_cpu_flags): Add RDPID field.
1679         * i386-opc.tbl: Add RDPID instruction.
1680         * i386-init.h: Regenerate.
1681         * i386-tbl.h: Regenerate.
1682
1683 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1684
1685         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1686         branch type of a symbol.
1687         (print_insn): Likewise.
1688
1689 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1690
1691         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1692         Mainline Security Extensions instructions.
1693         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1694         Extensions instructions.
1695         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1696         instructions.
1697         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1698         special registers.
1699
1700 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1701
1702         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1703
1704 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1705
1706         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1707         (arcExtMap_genOpcode): Likewise.
1708         * arc-opc.c (arg_32bit_rc): Define new variable.
1709         (arg_32bit_u6): Likewise.
1710         (arg_32bit_limm): Likewise.
1711
1712 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1713
1714         * aarch64-gen.c (VERIFIER): Define.
1715         * aarch64-opc.c (VERIFIER): Define.
1716         (verify_ldpsw): Use static linkage.
1717         * aarch64-opc.h (verify_ldpsw): Remove.
1718         * aarch64-tbl.h: Use VERIFIER for verifiers.
1719
1720 2016-04-28  Nick Clifton  <nickc@redhat.com>
1721
1722         PR target/19722
1723         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1724         * aarch64-opc.c (verify_ldpsw): New function.
1725         * aarch64-opc.h (verify_ldpsw): New prototype.
1726         * aarch64-tbl.h: Add initialiser for verifier field.
1727         (LDPSW): Set verifier to verify_ldpsw.
1728
1729 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1730
1731         PR binutils/19983
1732         PR binutils/19984
1733         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1734         smaller than address size.
1735
1736 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1737
1738         * alpha-dis.c: Regenerate.
1739         * crx-dis.c: Likewise.
1740         * disassemble.c: Likewise.
1741         * epiphany-opc.c: Likewise.
1742         * fr30-opc.c: Likewise.
1743         * frv-opc.c: Likewise.
1744         * ip2k-opc.c: Likewise.
1745         * iq2000-opc.c: Likewise.
1746         * lm32-opc.c: Likewise.
1747         * lm32-opinst.c: Likewise.
1748         * m32c-opc.c: Likewise.
1749         * m32r-opc.c: Likewise.
1750         * m32r-opinst.c: Likewise.
1751         * mep-opc.c: Likewise.
1752         * mt-opc.c: Likewise.
1753         * or1k-opc.c: Likewise.
1754         * or1k-opinst.c: Likewise.
1755         * tic80-opc.c: Likewise.
1756         * xc16x-opc.c: Likewise.
1757         * xstormy16-opc.c: Likewise.
1758
1759 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1760
1761         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1762         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1763         calcsd, and calcxd instructions.
1764         * arc-opc.c (insert_nps_bitop_size): Delete.
1765         (extract_nps_bitop_size): Delete.
1766         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1767         (extract_nps_qcmp_m3): Define.
1768         (extract_nps_qcmp_m2): Define.
1769         (extract_nps_qcmp_m1): Define.
1770         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1771         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1772         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1773         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1774         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1775         NPS_QCMP_M3.
1776
1777 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1778
1779         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1780
1781 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1782
1783         * Makefile.in: Regenerated with automake 1.11.6.
1784         * aclocal.m4: Likewise.
1785
1786 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1787
1788         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1789         instructions.
1790         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1791         (extract_nps_cmem_uimm16): New function.
1792         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1793
1794 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1795
1796         * arc-dis.c (arc_insn_length): New function.
1797         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1798         (find_format): Change insnLen parameter to unsigned.
1799
1800 2016-04-13  Nick Clifton  <nickc@redhat.com>
1801
1802         PR target/19937
1803         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1804         the LD.B and LD.BU instructions.
1805
1806 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1807
1808         * arc-dis.c (find_format): Check for extension flags.
1809         (print_flags): New function.
1810         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1811         .extAuxRegister.
1812         * arc-ext.c (arcExtMap_coreRegName): Use
1813         LAST_EXTENSION_CORE_REGISTER.
1814         (arcExtMap_coreReadWrite): Likewise.
1815         (dump_ARC_extmap): Update printing.
1816         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1817         (arc_aux_regs): Add cpu field.
1818         * arc-regs.h: Add cpu field, lower case name aux registers.
1819
1820 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1821
1822         * arc-tbl.h: Add rtsc, sleep with no arguments.
1823
1824 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1825
1826         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1827         Initialize.
1828         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1829         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1830         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1831         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1832         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1833         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1834         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1835         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1836         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1837         (arc_opcode arc_opcodes): Null terminate the array.
1838         (arc_num_opcodes): Remove.
1839         * arc-ext.h (INSERT_XOP): Define.
1840         (extInstruction_t): Likewise.
1841         (arcExtMap_instName): Delete.
1842         (arcExtMap_insn): New function.
1843         (arcExtMap_genOpcode): Likewise.
1844         * arc-ext.c (ExtInstruction): Remove.
1845         (create_map): Zero initialize instruction fields.
1846         (arcExtMap_instName): Remove.
1847         (arcExtMap_insn): New function.
1848         (dump_ARC_extmap): More info while debuging.
1849         (arcExtMap_genOpcode): New function.
1850         * arc-dis.c (find_format): New function.
1851         (print_insn_arc): Use find_format.
1852         (arc_get_disassembler): Enable dump_ARC_extmap only when
1853         debugging.
1854
1855 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1856
1857         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1858         instruction bits out.
1859
1860 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1861
1862         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1863         * arc-opc.c (arc_flag_operands): Add new flags.
1864         (arc_flag_classes): Add new classes.
1865
1866 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1867
1868         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1869
1870 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1871
1872         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1873         encode1, rflt, crc16, and crc32 instructions.
1874         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1875         (arc_flag_classes): Add C_NPS_R.
1876         (insert_nps_bitop_size_2b): New function.
1877         (extract_nps_bitop_size_2b): Likewise.
1878         (insert_nps_bitop_uimm8): Likewise.
1879         (extract_nps_bitop_uimm8): Likewise.
1880         (arc_operands): Add new operand entries.
1881
1882 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1883
1884         * arc-regs.h: Add a new subclass field.  Add double assist
1885         accumulator register values.
1886         * arc-tbl.h: Use DPA subclass to mark the double assist
1887         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1888         * arc-opc.c (RSP): Define instead of SP.
1889         (arc_aux_regs): Add the subclass field.
1890
1891 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1892
1893         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1894
1895 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1896
1897         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1898         NPS_R_SRC1.
1899
1900 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1901
1902         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1903         issues.  No functional changes.
1904
1905 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1906
1907         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1908         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1909         (RTT): Remove duplicate.
1910         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1911         (PCT_CONFIG*): Remove.
1912         (D1L, D1H, D2H, D2L): Define.
1913
1914 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1915
1916         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1917
1918 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1919
1920         * arc-tbl.h (invld07): Remove.
1921         * arc-ext-tbl.h: New file.
1922         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1923         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1924
1925 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1926
1927         Fix -Wstack-usage warnings.
1928         * aarch64-dis.c (print_operands): Substitute size.
1929         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1930
1931 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1932
1933         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1934         to get a proper diagnostic when an invalid ASR register is used.
1935
1936 2016-03-22  Nick Clifton  <nickc@redhat.com>
1937
1938         * configure: Regenerate.
1939
1940 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1941
1942         * arc-nps400-tbl.h: New file.
1943         * arc-opc.c: Add top level comment.
1944         (insert_nps_3bit_dst): New function.
1945         (extract_nps_3bit_dst): New function.
1946         (insert_nps_3bit_src2): New function.
1947         (extract_nps_3bit_src2): New function.
1948         (insert_nps_bitop_size): New function.
1949         (extract_nps_bitop_size): New function.
1950         (arc_flag_operands): Add nps400 entries.
1951         (arc_flag_classes): Add nps400 entries.
1952         (arc_operands): Add nps400 entries.
1953         (arc_opcodes): Add nps400 include.
1954
1955 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1956
1957         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1958         the new class enum values.
1959
1960 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1961
1962         * arc-dis.c (print_insn_arc): Handle nps400.
1963
1964 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1965
1966         * arc-opc.c (BASE): Delete.
1967
1968 2016-03-18  Nick Clifton  <nickc@redhat.com>
1969
1970         PR target/19721
1971         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1972         of MOV insn that aliases an ORR insn.
1973
1974 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1975
1976         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1977
1978 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1979
1980         * mcore-opc.h: Add const qualifiers.
1981         * microblaze-opc.h (struct op_code_struct): Likewise.
1982         * sh-opc.h: Likewise.
1983         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1984         (tic4x_print_op): Likewise.
1985
1986 2016-03-02  Alan Modra  <amodra@gmail.com>
1987
1988         * or1k-desc.h: Regenerate.
1989         * fr30-ibld.c: Regenerate.
1990         * rl78-decode.c: Regenerate.
1991
1992 2016-03-01  Nick Clifton  <nickc@redhat.com>
1993
1994         PR target/19747
1995         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1996
1997 2016-02-24  Renlin Li  <renlin.li@arm.com>
1998
1999         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
2000         (print_insn_coprocessor): Support fp16 instructions.
2001
2002 2016-02-24  Renlin Li  <renlin.li@arm.com>
2003
2004         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
2005         vminnm, vrint(mpna).
2006
2007 2016-02-24  Renlin Li  <renlin.li@arm.com>
2008
2009         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
2010         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
2011
2012 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
2013
2014         * i386-dis.c (print_insn): Parenthesize expression to prevent
2015         truncated addresses.
2016         (OP_J): Likewise.
2017
2018 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
2019             Janek van Oirschot  <jvanoirs@synopsys.com>
2020
2021         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2022         variable.
2023
2024 2016-02-04  Nick Clifton  <nickc@redhat.com>
2025
2026         PR target/19561
2027         * msp430-dis.c (print_insn_msp430): Add a special case for
2028         decoding an RRC instruction with the ZC bit set in the extension
2029         word.
2030
2031 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
2032
2033         * cgen-ibld.in (insert_normal): Rework calculation of shift.
2034         * epiphany-ibld.c: Regenerate.
2035         * fr30-ibld.c: Regenerate.
2036         * frv-ibld.c: Regenerate.
2037         * ip2k-ibld.c: Regenerate.
2038         * iq2000-ibld.c: Regenerate.
2039         * lm32-ibld.c: Regenerate.
2040         * m32c-ibld.c: Regenerate.
2041         * m32r-ibld.c: Regenerate.
2042         * mep-ibld.c: Regenerate.
2043         * mt-ibld.c: Regenerate.
2044         * or1k-ibld.c: Regenerate.
2045         * xc16x-ibld.c: Regenerate.
2046         * xstormy16-ibld.c: Regenerate.
2047
2048 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
2049
2050         * epiphany-dis.c: Regenerated from latest cpu files.
2051
2052 2016-02-01  Michael McConville  <mmcco@mykolab.com>
2053
2054         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2055         test bit.
2056
2057 2016-01-25  Renlin Li  <renlin.li@arm.com>
2058
2059         * arm-dis.c (mapping_symbol_for_insn): New function.
2060         (find_ifthen_state): Call mapping_symbol_for_insn().
2061
2062 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
2063
2064         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2065         of MSR UAO immediate operand.
2066
2067 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
2068
2069         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2070         instruction support.
2071
2072 2016-01-17  Alan Modra  <amodra@gmail.com>
2073
2074         * configure: Regenerate.
2075
2076 2016-01-14  Nick Clifton  <nickc@redhat.com>
2077
2078         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2079         instructions that can support stack pointer operations.
2080         * rl78-decode.c: Regenerate.
2081         * rl78-dis.c: Fix display of stack pointer in MOVW based
2082         instructions.
2083
2084 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
2085
2086         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2087         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
2088         erxtatus_el1 and erxaddr_el1.
2089
2090 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
2091
2092         * arm-dis.c (arm_opcodes): Add "esb".
2093         (thumb_opcodes): Likewise.
2094
2095 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
2096
2097         * ppc-opc.c <xscmpnedp>: Delete.
2098         <xvcmpnedp>: Likewise.
2099         <xvcmpnedp.>: Likewise.
2100         <xvcmpnesp>: Likewise.
2101         <xvcmpnesp.>: Likewise.
2102
2103 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
2104
2105         PR gas/13050
2106         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2107         addition to ISA_A.
2108
2109 2016-01-01  Alan Modra  <amodra@gmail.com>
2110
2111         Update year range in copyright notice of all files.
2112
2113 For older changes see ChangeLog-2015
2114 \f
2115 Copyright (C) 2016 Free Software Foundation, Inc.
2116
2117 Copying and distribution of this file, with or without modification,
2118 are permitted in any medium without royalty provided the copyright
2119 notice and this notice are preserved.
2120
2121 Local Variables:
2122 mode: change-log
2123 left-margin: 8
2124 fill-column: 74
2125 version-control: never
2126 End: