opcodes/ChangeLog

   1 2017-11-24  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
   4         "df" groups.
   5
   6 2017-11-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
   7
   8         * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
   9         * i386-tbl.h: Regenerate.
  10
  11 2017-11-23  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
  14         the 16-bit addressing case.
  15
  16 2017-11-23  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
  19         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
  20         * i386-opc.tbl (ud1, ud2b): Add operands.
  21         (ud0): New.
  22         * i386-tbl.h: Re-generate.
  23
  24 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  25
  26         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
  27         * i386-tbl.h: Regenerate.
  28
  29 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  30
  31         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
  32         * i386-tbl.h: Regenerate.
  33
  34 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  35
  36         *arc-opc (insert_rhv2): Check h-regs range.
  37
  38 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
  39
  40         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
  41         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
  42
  43 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  44
  45         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
  46         and AARCH64_FEATURE_F16.
  47
  48 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  49
  50         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
  51         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
  52         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
  53         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
  54         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
  55         (ldapur, ldapursw, stlur): New.
  56         * aarch64-dis-2.c: Regenerate.
  57
  58 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  59
  60         (get_valid_dis386): Never flag bad opcode when
  61         vex.register_specifier is beyond 7. Always store all four
  62         bits of it. Move 16-/32-bit override in EVEX handling after
  63         all to be overridden bits have been set.
  64         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  65         Use rex to determine GPR register set.
  66         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  67         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  68
  69 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  72         determine GPR register set.
  73
  74 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  77         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  78         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  79         pass.
  80         (OP_REG_VexI4): Drop low 4 bits check.
  81
  82 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-reg.tbl (axl): Remove Acc and Byte.
  85         * i386-tbl.h: Re-generate.
  86
  87 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  88
  89         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
  90         (vex_len_table): Use VPCOM.
  91
  92 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
  95         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
  96         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
  97         vpcmpw): Move up.
  98         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
  99         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
 100         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
 101         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
 102         vpcmpnltuw): New.
 103         * i386-tbl.h: Re-generate.
 104
 105 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
 108         smov, ssca, stos, ssto, xlat): Drop Disp*.
 109         * i386-tbl.h: Re-generate.
 110
 111 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
 114         xsaveopt64): Add No_qSuf.
 115         * i386-tbl.h: Re-generate.
 116
 117 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 118
 119         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
 120         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
 121         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
 122         sder32_el2, vncr_el2.
 123         (aarch64_sys_reg_supported_p): Likewise.
 124         (aarch64_pstatefields): Add dit register.
 125         (aarch64_pstatefield_supported_p): Likewise.
 126         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 127         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 128         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 129         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 130         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 131         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 132         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 133
 134 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 135
 136         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 137         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 138         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 139         (QL_STLW, QL_STLX): New.
 140
 141 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 142
 143         * aarch64-asm.h (ins_addr_offset): New.
 144         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 145         (aarch64_ins_addr_offset): New.
 146         * aarch64-asm-2.c: Regenerate.
 147         * aarch64-dis.h (ext_addr_offset): New.
 148         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 149         (aarch64_ext_addr_offset): New.
 150         * aarch64-dis-2.c: Regenerate.
 151         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 152         FLD_imm4_2 and FLD_SM3_imm2.
 153         * aarch64-opc.c (fields): Add FLD_imm6_2,
 154         FLD_imm4_2 and FLD_SM3_imm2.
 155         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 156         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 157         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 158         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 159         * aarch64-tbl.h
 160         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 161
 162 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 163
 164         * aarch64-tbl.h
 165         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 166         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 167         (aarch64_feature_fp_16_v8_2): New.
 168         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 169         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 170         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 171
 172 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 173
 174         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 175         (aarch64_feature_sha2, aarch64_feature_aes): New.
 176         (SHA2, AES): New.
 177         (AES_INSN, SHA2_INSN): New.
 178         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 179         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 180          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 181         Change to SHA2_INS.
 182
 183 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 184             Tamar Christina <tamar.christina@arm.com>
 185
 186         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 187         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 188
 189 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 190
 191         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 192
 193 2017-11-07  Alan Modra  <amodra@gmail.com>
 194
 195         * opintl.h: Formatting, comment fixes.
 196         (gettext, ngettext): Redefine when ENABLE_NLS.
 197         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 198         (_): Define using gettext.
 199         (textdomain, bindtextdomain): Use safer "do nothing".
 200
 201 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 202
 203         * arc-dis.c (print_hex): New variable.
 204         (parse_option): Check for hex option.
 205         (print_insn_arc): Use hexadecimal representation for short
 206         immediate values when requested.
 207         (print_arc_disassembler_options): Add hex option to the list.
 208
 209 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 210
 211         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 212         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 213         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 214         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 215         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 216         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 217         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 218         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 219         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 220         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 221         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 222         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 223         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 224         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 225         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 226         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 227         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 228         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 229         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 230         Changed opcodes.
 231         (prealloc, prefetch*): Place them before ld instruction.
 232         * arc-opc.c (skip_this_opcode): Add ARITH class.
 233
 234 2017-10-25  Alan Modra  <amodra@gmail.com>
 235
 236         PR 22348
 237         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 238         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 239         (imm4flag, size_changed): Likewise.
 240         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 241         (words, allWords, processing_argument_number): Likewise.
 242         (cst4flag, size_changed): Likewise.
 243         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 244         (crx_cst4_maps): Rename from cst4_maps.
 245         (crx_no_op_insn): Rename from no_op_insn.
 246
 247 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 248
 249         * riscv-opc.c (match_c_addi16sp) : New function.
 250         (match_c_addi4spn): New function.
 251         (match_c_lui): Don't allow 0-immediate encodings.
 252         (riscv_opcodes) <addi>: Use the above functions.
 253         <add>: Likewise.
 254         <c.addi4spn>: Likewise.
 255         <c.addi16sp>: Likewise.
 256
 257 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 258
 259         * i386-init.h: Regenerate
 260         * i386-tbl.h: Likewise
 261
 262 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 263
 264         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 265         (enum): Add EVEX_W_0F3854_P_2.
 266         * i386-dis-evex.h (evex_table): Updated.
 267         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 268         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 269         (cpu_flags): Add CpuAVX512_BITALG.
 270         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 271         (i386_cpu_flags): Add cpuavx512_bitalg..
 272         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 273         * i386-init.h: Regenerate.
 274         * i386-tbl.h: Likewise.
 275
 276 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 277
 278         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 279         * i386-dis-evex.h (evex_table): Updated.
 280         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 281         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 282         (cpu_flags): Add CpuAVX512_VNNI.
 283         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 284         (i386_cpu_flags): Add cpuavx512_vnni.
 285         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 286         * i386-init.h: Regenerate.
 287         * i386-tbl.h: Likewise.
 288
 289 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 290
 291         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 292         (enum): Remove VEX_LEN_0F3A44_P_2.
 293         (vex_len_table): Ditto.
 294         (enum): Remove VEX_W_0F3A44_P_2.
 295         (vew_w_table): Ditto.
 296         (prefix_table): Adjust instructions (see prefixes above).
 297         * i386-dis-evex.h (evex_table):
 298         Add new instructions (see prefixes above).
 299         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 300         (bitfield_cpu_flags): Ditto.
 301         * i386-opc.h (enum): Ditto.
 302         (i386_cpu_flags): Ditto.
 303         (CpuUnused): Comment out to avoid zero-width field problem.
 304         * i386-opc.tbl (vpclmulqdq): New instruction.
 305         * i386-init.h: Regenerate.
 306         * i386-tbl.h: Ditto.
 307
 308 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 309
 310         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 311         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 312         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 313         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 314         (vex_len_table): Ditto.
 315         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 316         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 317         (vew_w_table): Ditto.
 318         (prefix_table): Adjust instructions (see prefixes above).
 319         * i386-dis-evex.h (evex_table):
 320         Add new instructions (see prefixes above).
 321         * i386-gen.c (cpu_flag_init): Add VAES.
 322         (bitfield_cpu_flags): Ditto.
 323         * i386-opc.h (enum): Ditto.
 324         (i386_cpu_flags): Ditto.
 325         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 326         * i386-init.h: Regenerate.
 327         * i386-tbl.h: Ditto.
 328
 329 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 330
 331         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 332         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 333         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 334         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 335         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 336         (prefix_table): Updated (see prefixes above).
 337         (three_byte_table): Likewise.
 338         (vex_w_table): Likewise.
 339         * i386-dis-evex.h: Likewise.
 340         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 341         (cpu_flags): Add CpuGFNI.
 342         * i386-opc.h (enum): Add CpuGFNI.
 343         (i386_cpu_flags): Add cpugfni.
 344         * i386-opc.tbl: Add Intel GFNI instructions.
 345         * i386-init.h: Regenerate.
 346         * i386-tbl.h: Likewise.
 347
 348 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 349
 350         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 351         Define EXbScalar and EXwScalar for OP_EX.
 352         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 353         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 354         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 355         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 356         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 357         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 358         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 359         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 360         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 361         (OP_E_memory): Likewise.
 362         * i386-dis-evex.h: Updated.
 363         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 364         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 365         (cpu_flags): Add CpuAVX512_VBMI2.
 366         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 367         (i386_cpu_flags): Add cpuavx512_vbmi2.
 368         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 369         * i386-init.h: Regenerate.
 370         * i386-tbl.h: Likewise.
 371
 372 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 373
 374         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 375
 376 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 377
 378         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 379         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 380         K15. Add jmpix pattern.
 381
 382 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 383
 384         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 385
 386 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 387
 388         * s390-opc.c (INSTR_SI_RD): New macro.
 389         (INSTR_S_RD): Adjust example instruction.
 390         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 391         SI_RD.
 392
 393 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 394
 395         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 396         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 397         VLE multimple load/store instructions. Old e_ldm* variants are
 398         kept as aliases.
 399         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 400
 401 2017-09-27  Nick Clifton  <nickc@redhat.com>
 402
 403         PR 22179
 404         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 405         names for the fmv.x.s and fmv.s.x instructions respectively.
 406
 407 2017-09-26  do  <do@nerilex.org>
 408
 409         PR 22123
 410         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 411         be used on CPUs that have emacs support.
 412
 413 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 414
 415         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 416
 417 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 418
 419         * nds32-asm.c: Rename __BIT() to N32_BIT().
 420         * nds32-asm.h: Likewise.
 421         * nds32-dis.c: Likewise.
 422
 423 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 424
 425         * i386-dis.c (last_active_prefix): Removed.
 426         (ckprefix): Don't set last_active_prefix.
 427         (NOTRACK_Fixup): Don't check last_active_prefix.
 428
 429 2017-08-31  Nick Clifton  <nickc@redhat.com>
 430
 431         * po/fr.po: Updated French translation.
 432
 433 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 434
 435         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 436         fields.
 437
 438 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 439             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 440
 441         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 442         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 443         New entries efs2 and spe2.
 444         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 445         (SPE2_OPCD_SEGS): New macro.
 446         (spe2_opcd_indices): New.
 447         (disassemble_init_powerpc): Handle SPE2 opcodes.
 448         (lookup_spe2): New function.
 449         (print_insn_powerpc): call lookup_spe2.
 450         * ppc-opc.c (insert_evuimm1_ex0): New function.
 451         (extract_evuimm1_ex0): Likewise.
 452         (insert_evuimm_lt8): Likewise.
 453         (extract_evuimm_lt8): Likewise.
 454         (insert_off_spe2): Likewise.
 455         (extract_off_spe2): Likewise.
 456         (insert_Ddd): Likewise.
 457         (extract_Ddd): Likewise.
 458         (DD): New operand.
 459         (EVUIMM_LT8): Likewise.
 460         (EVUIMM_LT16): Adjust.
 461         (MMMM): New operand.
 462         (EVUIMM_1): Likewise.
 463         (EVUIMM_1_EX0): Likewise.
 464         (EVUIMM_2): Adjust.
 465         (NNN): New operand.
 466         (VX_OFF_SPE2): Likewise.
 467         (BBB): Likewise.
 468         (DDD): Likewise.
 469         (VX_MASK_DDD): New mask.
 470         (HH): New operand.
 471         (VX_RA_CONST): New macro.
 472         (VX_RA_CONST_MASK): Likewise.
 473         (VX_RB_CONST): Likewise.
 474         (VX_RB_CONST_MASK): Likewise.
 475         (VX_OFF_SPE2_MASK): Likewise.
 476         (VX_SPE_CRFD): Likewise.
 477         (VX_SPE_CRFD_MASK VX): Likewise.
 478         (VX_SPE2_CLR): Likewise.
 479         (VX_SPE2_CLR_MASK): Likewise.
 480         (VX_SPE2_SPLATB): Likewise.
 481         (VX_SPE2_SPLATB_MASK): Likewise.
 482         (VX_SPE2_OCTET): Likewise.
 483         (VX_SPE2_OCTET_MASK): Likewise.
 484         (VX_SPE2_DDHH): Likewise.
 485         (VX_SPE2_DDHH_MASK): Likewise.
 486         (VX_SPE2_HH): Likewise.
 487         (VX_SPE2_HH_MASK): Likewise.
 488         (VX_SPE2_EVMAR): Likewise.
 489         (VX_SPE2_EVMAR_MASK): Likewise.
 490         (PPCSPE2): Likewise.
 491         (PPCEFS2): Likewise.
 492         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 493         (powerpc_macros): Map old SPE instructions have new names
 494         with the same opcodes. Add SPE2 instructions which just are
 495         mapped to SPE2.
 496         (spe2_opcodes): Add SPE2 opcodes.
 497
 498 2017-08-23  Alan Modra  <amodra@gmail.com>
 499
 500         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 501         extract functions earlier, deleting forward declarations.
 502         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 503         RA_MASK.
 504
 505 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 506
 507         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 508
 509 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 510             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 511
 512         * ppc-opc.c (insert_evuimm2_ex0): New function.
 513         (extract_evuimm2_ex0): Likewise.
 514         (insert_evuimm4_ex0): Likewise.
 515         (extract_evuimm4_ex0): Likewise.
 516         (insert_evuimm8_ex0): Likewise.
 517         (extract_evuimm8_ex0): Likewise.
 518         (insert_evuimm_lt16): Likewise.
 519         (extract_evuimm_lt16): Likewise.
 520         (insert_rD_rS_even): Likewise.
 521         (extract_rD_rS_even): Likewise.
 522         (insert_off_lsp): Likewise.
 523         (extract_off_lsp): Likewise.
 524         (RD_EVEN): New operand.
 525         (RS_EVEN): Likewise.
 526         (RSQ): Adjust.
 527         (EVUIMM_LT16): New operand.
 528         (HTM_SI): Adjust.
 529         (EVUIMM_2_EX0): New operand.
 530         (EVUIMM_4): Adjust.
 531         (EVUIMM_4_EX0): New operand.
 532         (EVUIMM_8): Adjust.
 533         (EVUIMM_8_EX0): New operand.
 534         (WS): Adjust.
 535         (VX_OFF): New operand.
 536         (VX_LSP): New macro.
 537         (VX_LSP_MASK): Likewise.
 538         (VX_LSP_OFF_MASK): Likewise.
 539         (PPC_OPCODE_LSP): Likewise.
 540         (vle_opcodes): Add LSP opcodes.
 541         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 542
 543 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 544
 545         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 546         register operands in CRC instructions.
 547         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 548         comments.
 549
 550 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 551
 552         * disassemble.c (disassembler): Mark big and mach with
 553         ATTRIBUTE_UNUSED.
 554
 555 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 556
 557         * disassemble.c (disassembler): Remove arch/mach/endian
 558         assertions.
 559
 560 2017-07-25  Nick Clifton  <nickc@redhat.com>
 561
 562         PR 21739
 563         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 564         message.
 565         (insert_r0): Likewise.
 566         (insert_r1): Likewise.
 567         (insert_r2): Likewise.
 568         (insert_r3): Likewise.
 569         (insert_sp): Likewise.
 570         (insert_gp): Likewise.
 571         (insert_pcl): Likewise.
 572         (insert_blink): Likewise.
 573         (insert_ilink1): Likewise.
 574         (insert_ilink2): Likewise.
 575         (insert_ras): Likewise.
 576         (insert_rbs): Likewise.
 577         (insert_rcs): Likewise.
 578         (insert_simm3s): Likewise.
 579         (insert_rrange): Likewise.
 580         (insert_r13el): Likewise.
 581         (insert_fpel): Likewise.
 582         (insert_blinkel): Likewise.
 583         (insert_pclel): Likewise.
 584         (insert_nps_bitop_size_2b): Likewise.
 585         (insert_nps_imm_offset): Likewise.
 586         (insert_nps_imm_entry): Likewise.
 587         (insert_nps_size_16bit): Likewise.
 588         (insert_nps_##NAME##_pos): Likewise.
 589         (insert_nps_##NAME): Likewise.
 590         (insert_nps_bitop_ins_ext): Likewise.
 591         (insert_nps_##NAME): Likewise.
 592         (insert_nps_min_hofs): Likewise.
 593         (insert_nps_##NAME): Likewise.
 594         (insert_nps_rbdouble_64): Likewise.
 595         (insert_nps_misc_imm_offset): Likewise.
 596         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 597         option description.
 598
 599 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 600             Jiong Wang  <jiong.wang@arm.com>
 601
 602         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 603         correct the print.
 604         * aarch64-dis-2.c: Regenerated.
 605
 606 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 607
 608         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 609         table.
 610
 611 2017-07-20  Nick Clifton  <nickc@redhat.com>
 612
 613         * po/de.po: Updated German translation.
 614
 615 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 616
 617         * arc-regs.h (sec_stat): New aux register.
 618         (aux_kernel_sp): Likewise.
 619         (aux_sec_u_sp): Likewise.
 620         (aux_sec_k_sp): Likewise.
 621         (sec_vecbase_build): Likewise.
 622         (nsc_table_top): Likewise.
 623         (nsc_table_base): Likewise.
 624         (ersec_stat): Likewise.
 625         (aux_sec_except): Likewise.
 626
 627 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 628
 629         * arc-opc.c (extract_uimm12_20): New function.
 630         (UIMM12_20): New operand.
 631         (SIMM3_5_S): Adjust.
 632         * arc-tbl.h (sjli): Add new instruction.
 633
 634 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 635             John Eric Martin  <John.Martin@emmicro-us.com>
 636
 637         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 638         (UIMM3_23): Adjust accordingly.
 639         * arc-regs.h: Add/correct jli_base register.
 640         * arc-tbl.h (jli_s): Likewise.
 641
 642 2017-07-18  Nick Clifton  <nickc@redhat.com>
 643
 644         PR 21775
 645         * aarch64-opc.c: Fix spelling typos.
 646         * i386-dis.c: Likewise.
 647
 648 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 649
 650         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 651         max_addr_offset and octets variables to size_t.
 652
 653 2017-07-12  Alan Modra  <amodra@gmail.com>
 654
 655         * po/da.po: Update from translationproject.org/latest/opcodes/.
 656         * po/de.po: Likewise.
 657         * po/es.po: Likewise.
 658         * po/fi.po: Likewise.
 659         * po/fr.po: Likewise.
 660         * po/id.po: Likewise.
 661         * po/it.po: Likewise.
 662         * po/nl.po: Likewise.
 663         * po/pt_BR.po: Likewise.
 664         * po/ro.po: Likewise.
 665         * po/sv.po: Likewise.
 666         * po/tr.po: Likewise.
 667         * po/uk.po: Likewise.
 668         * po/vi.po: Likewise.
 669         * po/zh_CN.po: Likewise.
 670
 671 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 672             Alan Modra  <amodra@gmail.com>
 673
 674         * cgen.sh: Mark generated files read-only.
 675         * epiphany-asm.c: Regenerate.
 676         * epiphany-desc.c: Regenerate.
 677         * epiphany-desc.h: Regenerate.
 678         * epiphany-dis.c: Regenerate.
 679         * epiphany-ibld.c: Regenerate.
 680         * epiphany-opc.c: Regenerate.
 681         * epiphany-opc.h: Regenerate.
 682         * fr30-asm.c: Regenerate.
 683         * fr30-desc.c: Regenerate.
 684         * fr30-desc.h: Regenerate.
 685         * fr30-dis.c: Regenerate.
 686         * fr30-ibld.c: Regenerate.
 687         * fr30-opc.c: Regenerate.
 688         * fr30-opc.h: Regenerate.
 689         * frv-asm.c: Regenerate.
 690         * frv-desc.c: Regenerate.
 691         * frv-desc.h: Regenerate.
 692         * frv-dis.c: Regenerate.
 693         * frv-ibld.c: Regenerate.
 694         * frv-opc.c: Regenerate.
 695         * frv-opc.h: Regenerate.
 696         * ip2k-asm.c: Regenerate.
 697         * ip2k-desc.c: Regenerate.
 698         * ip2k-desc.h: Regenerate.
 699         * ip2k-dis.c: Regenerate.
 700         * ip2k-ibld.c: Regenerate.
 701         * ip2k-opc.c: Regenerate.
 702         * ip2k-opc.h: Regenerate.
 703         * iq2000-asm.c: Regenerate.
 704         * iq2000-desc.c: Regenerate.
 705         * iq2000-desc.h: Regenerate.
 706         * iq2000-dis.c: Regenerate.
 707         * iq2000-ibld.c: Regenerate.
 708         * iq2000-opc.c: Regenerate.
 709         * iq2000-opc.h: Regenerate.
 710         * lm32-asm.c: Regenerate.
 711         * lm32-desc.c: Regenerate.
 712         * lm32-desc.h: Regenerate.
 713         * lm32-dis.c: Regenerate.
 714         * lm32-ibld.c: Regenerate.
 715         * lm32-opc.c: Regenerate.
 716         * lm32-opc.h: Regenerate.
 717         * lm32-opinst.c: Regenerate.
 718         * m32c-asm.c: Regenerate.
 719         * m32c-desc.c: Regenerate.
 720         * m32c-desc.h: Regenerate.
 721         * m32c-dis.c: Regenerate.
 722         * m32c-ibld.c: Regenerate.
 723         * m32c-opc.c: Regenerate.
 724         * m32c-opc.h: Regenerate.
 725         * m32r-asm.c: Regenerate.
 726         * m32r-desc.c: Regenerate.
 727         * m32r-desc.h: Regenerate.
 728         * m32r-dis.c: Regenerate.
 729         * m32r-ibld.c: Regenerate.
 730         * m32r-opc.c: Regenerate.
 731         * m32r-opc.h: Regenerate.
 732         * m32r-opinst.c: Regenerate.
 733         * mep-asm.c: Regenerate.
 734         * mep-desc.c: Regenerate.
 735         * mep-desc.h: Regenerate.
 736         * mep-dis.c: Regenerate.
 737         * mep-ibld.c: Regenerate.
 738         * mep-opc.c: Regenerate.
 739         * mep-opc.h: Regenerate.
 740         * mt-asm.c: Regenerate.
 741         * mt-desc.c: Regenerate.
 742         * mt-desc.h: Regenerate.
 743         * mt-dis.c: Regenerate.
 744         * mt-ibld.c: Regenerate.
 745         * mt-opc.c: Regenerate.
 746         * mt-opc.h: Regenerate.
 747         * or1k-asm.c: Regenerate.
 748         * or1k-desc.c: Regenerate.
 749         * or1k-desc.h: Regenerate.
 750         * or1k-dis.c: Regenerate.
 751         * or1k-ibld.c: Regenerate.
 752         * or1k-opc.c: Regenerate.
 753         * or1k-opc.h: Regenerate.
 754         * or1k-opinst.c: Regenerate.
 755         * xc16x-asm.c: Regenerate.
 756         * xc16x-desc.c: Regenerate.
 757         * xc16x-desc.h: Regenerate.
 758         * xc16x-dis.c: Regenerate.
 759         * xc16x-ibld.c: Regenerate.
 760         * xc16x-opc.c: Regenerate.
 761         * xc16x-opc.h: Regenerate.
 762         * xstormy16-asm.c: Regenerate.
 763         * xstormy16-desc.c: Regenerate.
 764         * xstormy16-desc.h: Regenerate.
 765         * xstormy16-dis.c: Regenerate.
 766         * xstormy16-ibld.c: Regenerate.
 767         * xstormy16-opc.c: Regenerate.
 768         * xstormy16-opc.h: Regenerate.
 769
 770 2017-07-07  Alan Modra  <amodra@gmail.com>
 771
 772         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 773         * m32c-dis.c: Regenerate.
 774         * mep-dis.c: Regenerate.
 775
 776 2017-07-05  Borislav Petkov  <bp@suse.de>
 777
 778         * i386-dis.c: Enable ModRM.reg /6 aliases.
 779
 780 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 781
 782         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 783         with vmrs and vmsr.
 784
 785 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 786
 787         * configure: Regenerate.
 788
 789 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 790
 791         * po/opcodes.pot: Regenerate.
 792
 793 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 794
 795         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 796         entries to the MSA ASE instruction block.
 797
 798 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 799             Maciej W. Rozycki  <macro@imgtec.com>
 800
 801         * micromips-opc.c (XPA, XPAVZ): New macros.
 802         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 803         "mthgc0".
 804
 805 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 806             Maciej W. Rozycki  <macro@imgtec.com>
 807
 808         * micromips-opc.c (I36): New macro.
 809         (micromips_opcodes): Add "eretnc".
 810
 811 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 812             Andrew Bennett  <andrew.bennett@imgtec.com>
 813
 814         * mips-dis.c (mips_calculate_combination_ases): Handle the
 815         ASE_XPA_VIRT flag.
 816         (parse_mips_ase_option): New function.
 817         (parse_mips_dis_option): Factor out ASE option handling to the
 818         new function.  Call `mips_calculate_combination_ases'.
 819         * mips-opc.c (XPAVZ): New macro.
 820         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 821         "mfhgc0", "mthc0" and "mthgc0".
 822
 823 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 824
 825         * mips-dis.c (mips_calculate_combination_ases): New function.
 826         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 827         calculation to the new function.
 828         (set_default_mips_dis_options): Call the new function.
 829
 830 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 831
 832         * arc-dis.c (parse_disassembler_options): Use
 833         FOR_EACH_DISASSEMBLER_OPTION.
 834
 835 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 836
 837         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 838         disassembler option strings.
 839         (parse_cpu_option): Likewise.
 840
 841 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 842
 843         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 844         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 845         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 846         (aarch64_feature_dotprod, DOT_INSN): New.
 847         (udot, sdot): New.
 848         * aarch64-dis-2.c: Regenerated.
 849
 850 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 851
 852         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 853
 854 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 855             Matthew Fortune  <matthew.fortune@imgtec.com>
 856             Andrew Bennett  <andrew.bennett@imgtec.com>
 857
 858         * mips-formats.h (INT_BIAS): New macro.
 859         (INT_ADJ): Redefine in INT_BIAS terms.
 860         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 861         (mips_print_save_restore): New function.
 862         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 863         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 864         call.
 865         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 866         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 867         OP_SAVE_RESTORE_LIST handling, factored out from here.
 868         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 869         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 870         (mips_builtin_opcodes): Add "restore" and "save" entries.
 871         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 872         (IAMR2): New macro.
 873         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 874
 875 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 876
 877         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 878         alias; do not mark SLTI instruction as an alias.
 879
 880 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         * i386-dis.c (RM_0FAE_REG_5): Removed.
 883         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 884         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 885         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 886         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 887         PREFIX_MOD_3_0F01_REG_5_RM_0.
 888         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 889         PREFIX_MOD_3_0FAE_REG_5.
 890         (mod_table): Update MOD_0FAE_REG_5.
 891         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 892         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 893         * i386-tbl.h: Regenerated.
 894
 895 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 896
 897         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 898         * i386-opc.tbl: Likewise.
 899         * i386-tbl.h: Regenerated.
 900
 901 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 902
 903         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 904         and "jmp{&|}".
 905         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 906         prefix.
 907
 908 2017-06-19  Nick Clifton  <nickc@redhat.com>
 909
 910         PR binutils/21614
 911         * score-dis.c (score_opcodes): Add sentinel.
 912
 913 2017-06-16  Alan Modra  <amodra@gmail.com>
 914
 915         * rx-decode.c: Regenerate.
 916
 917 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 918
 919         PR binutils/21594
 920         * i386-dis.c (OP_E_register): Check valid bnd register.
 921         (OP_G): Likewise.
 922
 923 2017-06-15  Nick Clifton  <nickc@redhat.com>
 924
 925         PR binutils/21595
 926         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 927         range value.
 928
 929 2017-06-15  Nick Clifton  <nickc@redhat.com>
 930
 931         PR binutils/21588
 932         * rl78-decode.opc (OP_BUF_LEN): Define.
 933         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 934         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 935         array.
 936         * rl78-decode.c: Regenerate.
 937
 938 2017-06-15  Nick Clifton  <nickc@redhat.com>
 939
 940         PR binutils/21586
 941         * bfin-dis.c (gregs): Clip index to prevent overflow.
 942         (regs): Likewise.
 943         (regs_lo): Likewise.
 944         (regs_hi): Likewise.
 945
 946 2017-06-14  Nick Clifton  <nickc@redhat.com>
 947
 948         PR binutils/21576
 949         * score7-dis.c (score_opcodes): Add sentinel.
 950
 951 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 952
 953         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 954         * arm-dis.c: Likewise.
 955         * ia64-dis.c: Likewise.
 956         * mips-dis.c: Likewise.
 957         * spu-dis.c: Likewise.
 958         * disassemble.h (print_insn_aarch64): New declaration, moved from
 959         include/dis-asm.h.
 960         (print_insn_big_arm, print_insn_big_mips): Likewise.
 961         (print_insn_i386, print_insn_ia64): Likewise.
 962         (print_insn_little_arm, print_insn_little_mips): Likewise.
 963
 964 2017-06-14  Nick Clifton  <nickc@redhat.com>
 965
 966         PR binutils/21587
 967         * rx-decode.opc: Include libiberty.h
 968         (GET_SCALE): New macro - validates access to SCALE array.
 969         (GET_PSCALE): New macro - validates access to PSCALE array.
 970         (DIs, SIs, S2Is, rx_disp): Use new macros.
 971         * rx-decode.c: Regenerate.
 972
 973 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 974
 975         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 976
 977 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 978
 979         * arc-dis.c (enforced_isa_mask): Declare.
 980         (cpu_types): Likewise.
 981         (parse_cpu_option): New function.
 982         (parse_disassembler_options): Use it.
 983         (print_insn_arc): Use enforced_isa_mask.
 984         (print_arc_disassembler_options): Document new options.
 985
 986 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 987
 988         * alpha-dis.c: Include disassemble.h, don't include
 989         dis-asm.h.
 990         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 991         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 992         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 993         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 994         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 995         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 996         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 997         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 998         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 999         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1000         * moxie-dis.c, msp430-dis.c, mt-dis.c:
1001         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1002         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1003         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1004         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1005         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1006         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1007         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1008         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1009         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1010         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1011         * z80-dis.c, z8k-dis.c: Likewise.
1012         * disassemble.h: New file.
1013
1014 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1015
1016         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1017         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1018
1019 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1020
1021         * disassemble.c (disassembler): Add arguments a, big and mach.
1022         Use them.
1023
1024 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1025
1026         * i386-dis.c (NOTRACK_Fixup): New.
1027         (NOTRACK): Likewise.
1028         (NOTRACK_PREFIX): Likewise.
1029         (last_active_prefix): Likewise.
1030         (reg_table): Use NOTRACK on indirect call and jmp.
1031         (ckprefix): Set last_active_prefix.
1032         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1033         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1034         * i386-opc.h (NoTrackPrefixOk): New.
1035         (i386_opcode_modifier): Add notrackprefixok.
1036         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1037         Add notrack.
1038         * i386-tbl.h: Regenerated.
1039
1040 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1041
1042         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1043         (X_IMM2): Define.
1044         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1045         bfd_mach_sparc_v9m8.
1046         (print_insn_sparc): Handle new operand types.
1047         * sparc-opc.c (MASK_M8): Define.
1048         (v6): Add MASK_M8.
1049         (v6notlet): Likewise.
1050         (v7): Likewise.
1051         (v8): Likewise.
1052         (v9): Likewise.
1053         (v9a): Likewise.
1054         (v9b): Likewise.
1055         (v9c): Likewise.
1056         (v9d): Likewise.
1057         (v9e): Likewise.
1058         (v9v): Likewise.
1059         (v9m): Likewise.
1060         (v9andleon): Likewise.
1061         (m8): Define.
1062         (HWS_VM8): Define.
1063         (HWS2_VM8): Likewise.
1064         (sparc_opcode_archs): Add entry for "m8".
1065         (sparc_opcodes): Add OSA2017 and M8 instructions
1066         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1067         fpx{ll,ra,rl}64x,
1068         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1069         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1070         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1071         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1072         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1073         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1074         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1075         ASI_CORE_SELECT_COMMIT_NHT.
1076
1077 2017-05-18  Alan Modra  <amodra@gmail.com>
1078
1079         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1080         * aarch64-dis.c: Likewise.
1081         * aarch64-gen.c: Likewise.
1082         * aarch64-opc.c: Likewise.
1083
1084 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1085             Matthew Fortune  <matthew.fortune@imgtec.com>
1086
1087         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1088         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1089         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1090         (print_insn_arg) <OP_REG28>: Add handler.
1091         (validate_insn_args) <OP_REG28>: Handle.
1092         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1093         32-bit encoding and 9-bit immediates.
1094         (print_insn_mips16): Handle MIPS16 instructions that require
1095         32-bit encoding and MFC0/MTC0 operand decoding.
1096         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1097         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1098         (RD_C0, WR_C0, E2, E2MT): New macros.
1099         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1100         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1101         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1102         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1103         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1104         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1105         instructions, "swl", "swr", "sync" and its "sync_acquire",
1106         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1107         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1108         regular/extended entries for original MIPS16 ISA revision
1109         instructions whose extended forms are subdecoded in the MIPS16e2
1110         ISA revision: "li", "sll" and "srl".
1111
1112 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1113
1114         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1115         reference in CP0 move operand decoding.
1116
1117 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1118
1119         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1120         type to hexadecimal.
1121         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1122
1123 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1124
1125         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1126         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1127         "sync_rmb" and "sync_wmb" as aliases.
1128         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1129         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1130
1131 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1132
1133         * arc-dis.c (parse_option): Update quarkse_em option..
1134         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1135         QUARKSE1.
1136         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1137
1138 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1139
1140         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1141
1142 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1143
1144         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1145         register.
1146
1147 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1148
1149         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1150         and branches and not synthetic data instructions.
1151
1152 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1153
1154         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1155
1156 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1157
1158         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1159         * arc-opc.c (insert_r13el): New function.
1160         (R13_EL): Define.
1161         * arc-tbl.h: Add new enter/leave variants.
1162
1163 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1164
1165         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1166
1167 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1168
1169         * mips-dis.c (print_mips_disassembler_options): Add
1170         `no-aliases'.
1171
1172 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1173
1174         * mips16-opc.c (AL): New macro.
1175         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1176         of "ld" and "lw" as aliases.
1177
1178 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1179
1180         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1181         arguments.
1182
1183 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1184             Alan Modra  <amodra@gmail.com>
1185
1186         * ppc-opc.c (ELEV): Define.
1187         (vle_opcodes): Add se_rfgi and e_sc.
1188         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1189         for E200Z4.
1190
1191 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1192
1193         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1194
1195 2017-04-21  Nick Clifton  <nickc@redhat.com>
1196
1197         PR binutils/21380
1198         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1199         LD3R and LD4R.
1200
1201 2017-04-13  Alan Modra  <amodra@gmail.com>
1202
1203         * epiphany-desc.c: Regenerate.
1204         * fr30-desc.c: Regenerate.
1205         * frv-desc.c: Regenerate.
1206         * ip2k-desc.c: Regenerate.
1207         * iq2000-desc.c: Regenerate.
1208         * lm32-desc.c: Regenerate.
1209         * m32c-desc.c: Regenerate.
1210         * m32r-desc.c: Regenerate.
1211         * mep-desc.c: Regenerate.
1212         * mt-desc.c: Regenerate.
1213         * or1k-desc.c: Regenerate.
1214         * xc16x-desc.c: Regenerate.
1215         * xstormy16-desc.c: Regenerate.
1216
1217 2017-04-11  Alan Modra  <amodra@gmail.com>
1218
1219         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1220         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1221         PPC_OPCODE_TMR for e6500.
1222         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1223         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1224         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1225         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1226         (PPCHTM): Define as PPC_OPCODE_POWER8.
1227         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1228
1229 2017-04-10  Alan Modra  <amodra@gmail.com>
1230
1231         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1232         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1233         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1234         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1235
1236 2017-04-09  Pip Cet  <pipcet@gmail.com>
1237
1238         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1239         appropriate floating-point precision directly.
1240
1241 2017-04-07  Alan Modra  <amodra@gmail.com>
1242
1243         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1244         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1245         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1246         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1247         vector instructions with E6500 not PPCVEC2.
1248
1249 2017-04-06  Pip Cet  <pipcet@gmail.com>
1250
1251         * Makefile.am: Add wasm32-dis.c.
1252         * configure.ac: Add wasm32-dis.c to wasm32 target.
1253         * disassemble.c: Add wasm32 disassembler code.
1254         * wasm32-dis.c: New file.
1255         * Makefile.in: Regenerate.
1256         * configure: Regenerate.
1257         * po/POTFILES.in: Regenerate.
1258         * po/opcodes.pot: Regenerate.
1259
1260 2017-04-05  Pedro Alves  <palves@redhat.com>
1261
1262         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1263         * arm-dis.c (parse_arm_disassembler_options): Constify.
1264         * ppc-dis.c (powerpc_init_dialect): Constify local.
1265         * vax-dis.c (parse_disassembler_options): Constify.
1266
1267 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1268
1269         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1270         RISCV_GP_SYMBOL.
1271
1272 2017-03-30  Pip Cet  <pipcet@gmail.com>
1273
1274         * configure.ac: Add (empty) bfd_wasm32_arch target.
1275         * configure: Regenerate
1276         * po/opcodes.pot: Regenerate.
1277
1278 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1279
1280         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1281         OSA2015.
1282         * opcodes/sparc-opc.c (asi_table): New ASIs.
1283
1284 2017-03-29  Alan Modra  <amodra@gmail.com>
1285
1286         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1287         "raw" option.
1288         (lookup_powerpc): Don't special case -1 dialect.  Handle
1289         PPC_OPCODE_RAW.
1290         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1291         lookup_powerpc call, pass it on second.
1292
1293 2017-03-27  Alan Modra  <amodra@gmail.com>
1294
1295         PR 21303
1296         * ppc-dis.c (struct ppc_mopt): Comment.
1297         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1298
1299 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1300
1301         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1302         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1303         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1304         (insert_nps_misc_imm_offset): New function.
1305         (extract_nps_misc imm_offset): New function.
1306         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1307         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1308
1309 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1310
1311         * s390-mkopc.c (main): Remove vx2 check.
1312         * s390-opc.txt: Remove vx2 instruction flags.
1313
1314 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1315
1316         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1317         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1318         (insert_nps_imm_offset): New function.
1319         (extract_nps_imm_offset): New function.
1320         (insert_nps_imm_entry): New function.
1321         (extract_nps_imm_entry): New function.
1322
1323 2017-03-17  Alan Modra  <amodra@gmail.com>
1324
1325         PR 21248
1326         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1327         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1328         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1329
1330 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1331
1332         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1333         <c.andi>: Likewise.
1334         <c.addiw> Likewise.
1335
1336 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1337
1338         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1339
1340 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1341
1342         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1343         <srl> Likewise.
1344         <srai> Likewise.
1345         <sra> Likewise.
1346
1347 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1348
1349         * i386-gen.c (opcode_modifiers): Replace S with Load.
1350         * i386-opc.h (S): Removed.
1351         (Load): New.
1352         (i386_opcode_modifier): Replace s with load.
1353         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1354         and {evex}.  Replace S with Load.
1355         * i386-tbl.h: Regenerated.
1356
1357 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1358
1359         * i386-opc.tbl: Use CpuCET on rdsspq.
1360         * i386-tbl.h: Regenerated.
1361
1362 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1363
1364         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1365         <vsx>: Do not use PPC_OPCODE_VSX3;
1366
1367 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1368
1369         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1370
1371 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1372
1373         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1374         (MOD_0F1E_PREFIX_1): Likewise.
1375         (MOD_0F38F5_PREFIX_2): Likewise.
1376         (MOD_0F38F6_PREFIX_0): Likewise.
1377         (RM_0F1E_MOD_3_REG_7): Likewise.
1378         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1379         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1380         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1381         (PREFIX_0F1E): Likewise.
1382         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1383         (PREFIX_0F38F5): Likewise.
1384         (dis386_twobyte): Use PREFIX_0F1E.
1385         (reg_table): Add REG_0F1E_MOD_3.
1386         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1387         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1388         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1389         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1390         (three_byte_table): Use PREFIX_0F38F5.
1391         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1392         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1393         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1394         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1395         PREFIX_MOD_3_0F01_REG_5_RM_2.
1396         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1397         (cpu_flags): Add CpuCET.
1398         * i386-opc.h (CpuCET): New enum.
1399         (CpuUnused): Commented out.
1400         (i386_cpu_flags): Add cpucet.
1401         * i386-opc.tbl: Add Intel CET instructions.
1402         * i386-init.h: Regenerated.
1403         * i386-tbl.h: Likewise.
1404
1405 2017-03-06  Alan Modra  <amodra@gmail.com>
1406
1407         PR 21124
1408         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1409         (extract_raq, extract_ras, extract_rbx): New functions.
1410         (powerpc_operands): Use opposite corresponding insert function.
1411         (Q_MASK): Define.
1412         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1413         register restriction.
1414
1415 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1416
1417         * disassemble.c Include "safe-ctype.h".
1418         (disassemble_init_for_target): Handle s390 init.
1419         (remove_whitespace_and_extra_commas): New function.
1420         (disassembler_options_cmp): Likewise.
1421         * arm-dis.c: Include "libiberty.h".
1422         (NUM_ELEM): Delete.
1423         (regnames): Use long disassembler style names.
1424         Add force-thumb and no-force-thumb options.
1425         (NUM_ARM_REGNAMES): Rename from this...
1426         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1427         (get_arm_regname_num_options): Delete.
1428         (set_arm_regname_option): Likewise.
1429         (get_arm_regnames): Likewise.
1430         (parse_disassembler_options): Likewise.
1431         (parse_arm_disassembler_option): Rename from this...
1432         (parse_arm_disassembler_options): ...to this.  Make static.
1433         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1434         (print_insn): Use parse_arm_disassembler_options.
1435         (disassembler_options_arm): New function.
1436         (print_arm_disassembler_options): Handle updated regnames.
1437         * ppc-dis.c: Include "libiberty.h".
1438         (ppc_opts): Add "32" and "64" entries.
1439         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1440         (powerpc_init_dialect): Add break to switch statement.
1441         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1442         (disassembler_options_powerpc): New function.
1443         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1444         Remove printing of "32" and "64".
1445         * s390-dis.c: Include "libiberty.h".
1446         (init_flag): Remove unneeded variable.
1447         (struct s390_options_t): New structure type.
1448         (options): New structure.
1449         (init_disasm): Rename from this...
1450         (disassemble_init_s390): ...to this.  Add initializations for
1451         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1452         (print_insn_s390): Delete call to init_disasm.
1453         (disassembler_options_s390): New function.
1454         (print_s390_disassembler_options): Print using information from
1455         struct 'options'.
1456         * po/opcodes.pot: Regenerate.
1457
1458 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1459
1460         * i386-dis.c (PCMPESTR_Fixup): New.
1461         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1462         (prefix_table): Use PCMPESTR_Fixup.
1463         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1464         PCMPESTR_Fixup.
1465         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1466         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1467         Split 64-bit and non-64-bit variants.
1468         * opcodes/i386-tbl.h: Re-generate.
1469
1470 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1471
1472         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1473         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1474         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1475         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1476         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1477         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1478         (OP_SVE_V_HSD): New macros.
1479         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1480         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1481         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1482         (aarch64_opcode_table): Add new SVE instructions.
1483         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1484         for rotation operands.  Add new SVE operands.
1485         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1486         (ins_sve_quad_index): Likewise.
1487         (ins_imm_rotate): Split into...
1488         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1489         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1490         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1491         functions.
1492         (aarch64_ins_sve_addr_ri_s4): New function.
1493         (aarch64_ins_sve_quad_index): Likewise.
1494         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1495         * aarch64-asm-2.c: Regenerate.
1496         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1497         (ext_sve_quad_index): Likewise.
1498         (ext_imm_rotate): Split into...
1499         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1500         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1501         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1502         functions.
1503         (aarch64_ext_sve_addr_ri_s4): New function.
1504         (aarch64_ext_sve_quad_index): Likewise.
1505         (aarch64_ext_sve_index): Allow quad indices.
1506         (do_misc_decoding): Likewise.
1507         * aarch64-dis-2.c: Regenerate.
1508         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1509         aarch64_field_kinds.
1510         (OPD_F_OD_MASK): Widen by one bit.
1511         (OPD_F_NO_ZR): Bump accordingly.
1512         (get_operand_field_width): New function.
1513         * aarch64-opc.c (fields): Add new SVE fields.
1514         (operand_general_constraint_met_p): Handle new SVE operands.
1515         (aarch64_print_operand): Likewise.
1516         * aarch64-opc-2.c: Regenerate.
1517
1518 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1519
1520         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1521         (aarch64_feature_compnum): ...this.
1522         (SIMD_V8_3): Replace with...
1523         (COMPNUM): ...this.
1524         (CNUM_INSN): New macro.
1525         (aarch64_opcode_table): Use it for the complex number instructions.
1526
1527 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1528
1529         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1530
1531 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1532
1533         Add support for associating SPARC ASIs with an architecture level.
1534         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1535         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1536         decoding of SPARC ASIs.
1537
1538 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1539
1540         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1541         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1542
1543 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1544
1545         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1546         1 (instead of to itself). Correct typo.
1547
1548 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1549
1550         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1551         pseudoinstructions.
1552
1553 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1554
1555         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1556         (aarch64_sys_reg_supported_p): Handle them.
1557
1558 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1559
1560         * arc-opc.c (UIMM6_20R): Define.
1561         (SIMM12_20): Use above.
1562         (SIMM12_20R): Define.
1563         (SIMM3_5_S): Use above.
1564         (UIMM7_A32_11R_S): Define.
1565         (UIMM7_9_S): Use above.
1566         (UIMM3_13R_S): Define.
1567         (SIMM11_A32_7_S): Use above.
1568         (SIMM9_8R): Define.
1569         (UIMM10_A32_8_S): Use above.
1570         (UIMM8_8R_S): Define.
1571         (W6): Use above.
1572         (arc_relax_opcodes): Use all above defines.
1573
1574 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1575
1576         * arc-regs.h: Distinguish some of the registers different on
1577         ARC700 and HS38 cpus.
1578
1579 2017-02-14  Alan Modra  <amodra@gmail.com>
1580
1581         PR 21118
1582         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1583         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1584
1585 2017-02-11  Stafford Horne  <shorne@gmail.com>
1586             Alan Modra  <amodra@gmail.com>
1587
1588         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1589         Use insn_bytes_value and insn_int_value directly instead.  Don't
1590         free allocated memory until function exit.
1591
1592 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1593
1594         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1595
1596 2017-02-03  Nick Clifton  <nickc@redhat.com>
1597
1598         PR 21096
1599         * aarch64-opc.c (print_register_list): Ensure that the register
1600         list index will fir into the tb buffer.
1601         (print_register_offset_address): Likewise.
1602         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1603
1604 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1605
1606         PR 21056
1607         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1608         instructions when the previous fetch packet ends with a 32-bit
1609         instruction.
1610
1611 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1612
1613         * pru-opc.c: Remove vague reference to a future GDB port.
1614
1615 2017-01-20  Nick Clifton  <nickc@redhat.com>
1616
1617         * po/ga.po: Updated Irish translation.
1618
1619 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1620
1621         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1622
1623 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1624
1625         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1626         if FETCH_DATA returns 0.
1627         (m68k_scan_mask): Likewise.
1628         (print_insn_m68k): Update code to handle -1 return value.
1629
1630 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1631
1632         * m68k-dis.c (enum print_insn_arg_error): New.
1633         (NEXTBYTE): Replace -3 with
1634         PRINT_INSN_ARG_MEMORY_ERROR.
1635         (NEXTULONG): Likewise.
1636         (NEXTSINGLE): Likewise.
1637         (NEXTDOUBLE): Likewise.
1638         (NEXTDOUBLE): Likewise.
1639         (NEXTPACKED): Likewise.
1640         (FETCH_ARG): Likewise.
1641         (FETCH_DATA): Update comments.
1642         (print_insn_arg): Update comments. Replace magic numbers with
1643         enum.
1644         (match_insn_m68k): Likewise.
1645
1646 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1647
1648         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1649         * i386-dis-evex.h (evex_table): Updated.
1650         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1651         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1652         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1653         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1654         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1655         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1656         * i386-init.h: Regenerate.
1657         * i386-tbl.h: Ditto.
1658
1659 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1660
1661         * msp430-dis.c (msp430_singleoperand): Return -1 if
1662         msp430dis_opcode_signed returns false.
1663         (msp430_doubleoperand): Likewise.
1664         (msp430_branchinstr): Return -1 if
1665         msp430dis_opcode_unsigned returns false.
1666         (msp430x_calla_instr): Likewise.
1667         (print_insn_msp430): Likewise.
1668
1669 2017-01-05  Nick Clifton  <nickc@redhat.com>
1670
1671         PR 20946
1672         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1673         could not be matched.
1674         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1675         NULL.
1676
1677 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1678
1679         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1680         (aarch64_opcode_table): Use RCPC_INSN.
1681
1682 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1683
1684         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1685         extension.
1686         * riscv-opcodes/all-opcodes: Likewise.
1687
1688 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1689
1690         * riscv-dis.c (print_insn_args): Add fall through comment.
1691
1692 2017-01-03  Nick Clifton  <nickc@redhat.com>
1693
1694         * po/sr.po: New Serbian translation.
1695         * configure.ac (ALL_LINGUAS): Add sr.
1696         * configure: Regenerate.
1697
1698 2017-01-02  Alan Modra  <amodra@gmail.com>
1699
1700         * epiphany-desc.h: Regenerate.
1701         * epiphany-opc.h: Regenerate.
1702         * fr30-desc.h: Regenerate.
1703         * fr30-opc.h: Regenerate.
1704         * frv-desc.h: Regenerate.
1705         * frv-opc.h: Regenerate.
1706         * ip2k-desc.h: Regenerate.
1707         * ip2k-opc.h: Regenerate.
1708         * iq2000-desc.h: Regenerate.
1709         * iq2000-opc.h: Regenerate.
1710         * lm32-desc.h: Regenerate.
1711         * lm32-opc.h: Regenerate.
1712         * m32c-desc.h: Regenerate.
1713         * m32c-opc.h: Regenerate.
1714         * m32r-desc.h: Regenerate.
1715         * m32r-opc.h: Regenerate.
1716         * mep-desc.h: Regenerate.
1717         * mep-opc.h: Regenerate.
1718         * mt-desc.h: Regenerate.
1719         * mt-opc.h: Regenerate.
1720         * or1k-desc.h: Regenerate.
1721         * or1k-opc.h: Regenerate.
1722         * xc16x-desc.h: Regenerate.
1723         * xc16x-opc.h: Regenerate.
1724         * xstormy16-desc.h: Regenerate.
1725         * xstormy16-opc.h: Regenerate.
1726
1727 2017-01-02  Alan Modra  <amodra@gmail.com>
1728
1729         Update year range in copyright notice of all files.
1730
1731 For older changes see ChangeLog-2016
1732 \f
1733 Copyright (C) 2017 Free Software Foundation, Inc.
1734
1735 Copying and distribution of this file, with or without modification,
1736 are permitted in any medium without royalty provided the copyright
1737 notice and this notice are preserved.
1738
1739 Local Variables:
1740 mode: change-log
1741 left-margin: 8
1742 fill-column: 74
1743 version-control: never
1744 End: