1 2016-07-01 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
4 (lgdt): Remove Tbyte from non-64-bit variant.
5 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
6 xsaves64, xsavec64): Remove Disp16.
7 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
8 Remove Disp32S from non-64-bit variants. Remove Disp16 from
10 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
11 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
12 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
14 * i386-tbl.h: Re-generate.
16 2016-07-01 Jan Beulich <jbeulich@suse.com>
18 * i386-opc.tbl (xlat): Remove RepPrefixOk.
19 * i386-tbl.h: Re-generate.
21 2016-06-30 Yao Qi <yao.qi@linaro.org>
23 * arm-dis.c (print_insn): Fix typo in comment.
25 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
27 * aarch64-opc.c (operand_general_constraint_met_p): Check the
28 range of ldst_elemlist operands.
29 (print_register_list): Use PRIi64 to print the index.
30 (aarch64_print_operand): Likewise.
32 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
34 * mcore-opc.h: Remove sentinal.
35 * mcore-dis.c (print_insn_mcore): Adjust.
37 2016-06-23 Graham Markall <graham.markall@embecosm.com>
39 * arc-opc.c: Correct description of availability of NPS400
42 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
44 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
45 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
46 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
48 <setb>: Change to a VX form instruction.
49 (insert_sh6): Add support for rldixor.
50 (extract_sh6): Likewise.
52 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
54 * arc-ext.h: Wrap in extern C.
56 2016-06-21 Graham Markall <graham.markall@embecosm.com>
58 * arc-dis.c (arc_insn_length): Add comment on instruction length.
59 Use same method for determining instruction length on ARC700 and
61 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
62 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
63 with the NPS400 subclass.
64 * arc-opc.c: Likewise.
66 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
68 * sparc-opc.c (rdasr): New macro.
74 (sparc_opcodes): Use the macros above to fix and expand the
75 definition of read/write instructions from/to
76 asr/privileged/hyperprivileged instructions.
77 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
78 %hva_mask_nz. Prefer softint_set and softint_clear over
79 set_softint and clear_softint.
80 (print_insn_sparc): Support %ver in Rd.
82 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
84 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
85 architecture according to the hardware capabilities they require.
87 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
89 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
90 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
91 bfd_mach_sparc_v9{c,d,e,v,m}.
92 * sparc-opc.c (MASK_V9C): Define.
97 (v6): Add MASK_V9{C,D,E,V,M}.
102 (v9andleon): Likewise.
110 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
112 2016-06-15 Nick Clifton <nickc@redhat.com>
114 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
115 constants to match expected behaviour.
116 (nds32_parse_opcode): Likewise. Also for whitespace.
118 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
120 * arc-opc.c (extract_rhv1): Extract value from insn.
122 2016-06-14 Graham Markall <graham.markall@embecosm.com>
124 * arc-nps400-tbl.h: Add ldbit instruction.
125 * arc-opc.c: Add flag classes required for ldbit.
127 2016-06-14 Graham Markall <graham.markall@embecosm.com>
129 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
130 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
131 support the above instructions.
133 2016-06-14 Graham Markall <graham.markall@embecosm.com>
135 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
136 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
137 csma, cbba, zncv, and hofs.
138 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
139 support the above instructions.
141 2016-06-06 Graham Markall <graham.markall@embecosm.com>
143 * arc-nps400-tbl.h: Add andab and orab instructions.
145 2016-06-06 Graham Markall <graham.markall@embecosm.com>
147 * arc-nps400-tbl.h: Add addl-like instructions.
149 2016-06-06 Graham Markall <graham.markall@embecosm.com>
151 * arc-nps400-tbl.h: Add mxb and imxb instructions.
153 2016-06-06 Graham Markall <graham.markall@embecosm.com>
155 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
158 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
160 * s390-dis.c (option_use_insn_len_bits_p): New file scope
162 (init_disasm): Handle new command line option "insnlength".
163 (print_s390_disassembler_options): Mention new option in help
165 (print_insn_s390): Use the encoded insn length when dumping
166 unknown instructions.
168 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
170 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
171 to the address and set as symbol address for LDS/ STS immediate operands.
173 2016-06-07 Alan Modra <amodra@gmail.com>
175 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
176 cpu for "vle" to e500.
177 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
178 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
179 (PPCNONE): Delete, substitute throughout.
180 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
181 except for major opcode 4 and 31.
182 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
184 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
186 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
187 ARM_EXT_RAS in relevant entries.
189 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
192 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
195 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
198 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
200 Add comments for '&'.
201 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
203 (intel_operand_size): Handle indir_v_mode.
204 (OP_E_register): Likewise.
205 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
206 64-bit indirect call/jmp for AMD64.
207 * i386-tbl.h: Regenerated
209 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
211 * arc-dis.c (struct arc_operand_iterator): New structure.
212 (find_format_from_table): All the old content from find_format,
213 with some minor adjustments, and parameter renaming.
214 (find_format_long_instructions): New function.
215 (find_format): Rewritten.
216 (arc_insn_length): Add LSB parameter.
217 (extract_operand_value): New function.
218 (operand_iterator_next): New function.
219 (print_insn_arc): Use new functions to find opcode, and iterator
221 * arc-opc.c (insert_nps_3bit_dst_short): New function.
222 (extract_nps_3bit_dst_short): New function.
223 (insert_nps_3bit_src2_short): New function.
224 (extract_nps_3bit_src2_short): New function.
225 (insert_nps_bitop1_size): New function.
226 (extract_nps_bitop1_size): New function.
227 (insert_nps_bitop2_size): New function.
228 (extract_nps_bitop2_size): New function.
229 (insert_nps_bitop_mod4_msb): New function.
230 (extract_nps_bitop_mod4_msb): New function.
231 (insert_nps_bitop_mod4_lsb): New function.
232 (extract_nps_bitop_mod4_lsb): New function.
233 (insert_nps_bitop_dst_pos3_pos4): New function.
234 (extract_nps_bitop_dst_pos3_pos4): New function.
235 (insert_nps_bitop_ins_ext): New function.
236 (extract_nps_bitop_ins_ext): New function.
237 (arc_operands): Add new operands.
238 (arc_long_opcodes): New global array.
239 (arc_num_long_opcodes): New global.
240 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
242 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
244 * nds32-asm.h: Add extern "C".
245 * sh-opc.h: Likewise.
247 2016-06-01 Graham Markall <graham.markall@embecosm.com>
249 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
250 0,b,limm to the rflt instruction.
252 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
254 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
257 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
260 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
261 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
262 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
263 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
264 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
265 * i386-init.h: Regenerated.
267 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
270 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
271 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
272 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
273 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
274 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
275 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
276 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
277 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
278 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
279 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
280 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
281 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
282 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
283 CpuRegMask for AVX512.
284 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
286 (set_bitfield_from_cpu_flag_init): New function.
287 (set_bitfield): Remove const on f. Call
288 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
289 * i386-opc.h (CpuRegMMX): New.
290 (CpuRegXMM): Likewise.
291 (CpuRegYMM): Likewise.
292 (CpuRegZMM): Likewise.
293 (CpuRegMask): Likewise.
294 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
296 * i386-init.h: Regenerated.
297 * i386-tbl.h: Likewise.
299 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
302 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
303 (opcode_modifiers): Add AMD64 and Intel64.
304 (main): Properly verify CpuMax.
305 * i386-opc.h (CpuAMD64): Removed.
306 (CpuIntel64): Likewise.
307 (CpuMax): Set to CpuNo64.
308 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
311 (i386_opcode_modifier): Add amd64 and intel64.
312 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
314 * i386-init.h: Regenerated.
315 * i386-tbl.h: Likewise.
317 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
320 * i386-gen.c (main): Fail if CpuMax is incorrect.
321 * i386-opc.h (CpuMax): Set to CpuIntel64.
322 * i386-tbl.h: Regenerated.
324 2016-05-27 Nick Clifton <nickc@redhat.com>
327 * msp430-dis.c (msp430dis_read_two_bytes): New function.
328 (msp430dis_opcode_unsigned): New function.
329 (msp430dis_opcode_signed): New function.
330 (msp430_singleoperand): Use the new opcode reading functions.
331 Only disassenmble bytes if they were successfully read.
332 (msp430_doubleoperand): Likewise.
333 (msp430_branchinstr): Likewise.
334 (msp430x_callx_instr): Likewise.
335 (print_insn_msp430): Check that it is safe to read bytes before
336 attempting disassembly. Use the new opcode reading functions.
338 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
340 * ppc-opc.c (CY): New define. Document it.
341 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
343 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
345 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
346 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
347 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
348 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
350 * i386-init.h: Regenerated.
352 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
355 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
356 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
357 * i386-init.h: Regenerated.
359 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
361 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
362 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
363 * i386-init.h: Regenerated.
365 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
367 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
369 (print_insn_arc): Set insn_type information.
370 * arc-opc.c (C_CC): Add F_CLASS_COND.
371 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
372 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
373 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
374 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
375 (brne, brne_s, jeq_s, jne_s): Likewise.
377 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
379 * arc-tbl.h (neg): New instruction variant.
381 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
383 * arc-dis.c (find_format, find_format, get_auxreg)
384 (print_insn_arc): Changed.
385 * arc-ext.h (INSERT_XOP): Likewise.
387 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
389 * tic54x-dis.c (sprint_mmr): Adjust.
390 * tic54x-opc.c: Likewise.
392 2016-05-19 Alan Modra <amodra@gmail.com>
394 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
396 2016-05-19 Alan Modra <amodra@gmail.com>
398 * ppc-opc.c: Formatting.
399 (NSISIGNOPT): Define.
400 (powerpc_opcodes <subis>): Use NSISIGNOPT.
402 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
404 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
405 replacing references to `micromips_ase' throughout.
406 (_print_insn_mips): Don't use file-level microMIPS annotation to
407 determine the disassembly mode with the symbol table.
409 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
411 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
413 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
415 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
417 * mips-opc.c (D34): New macro.
418 (mips_builtin_opcodes): Define bposge32c for DSPr3.
420 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
422 * i386-dis.c (prefix_table): Add RDPID instruction.
423 * i386-gen.c (cpu_flag_init): Add RDPID flag.
424 (cpu_flags): Add RDPID bitfield.
425 * i386-opc.h (enum): Add RDPID element.
426 (i386_cpu_flags): Add RDPID field.
427 * i386-opc.tbl: Add RDPID instruction.
428 * i386-init.h: Regenerate.
429 * i386-tbl.h: Regenerate.
431 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
433 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
434 branch type of a symbol.
435 (print_insn): Likewise.
437 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
439 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
440 Mainline Security Extensions instructions.
441 (thumb_opcodes): Add entries for narrow ARMv8-M Security
442 Extensions instructions.
443 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
445 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
448 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
450 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
452 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
454 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
455 (arcExtMap_genOpcode): Likewise.
456 * arc-opc.c (arg_32bit_rc): Define new variable.
457 (arg_32bit_u6): Likewise.
458 (arg_32bit_limm): Likewise.
460 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
462 * aarch64-gen.c (VERIFIER): Define.
463 * aarch64-opc.c (VERIFIER): Define.
464 (verify_ldpsw): Use static linkage.
465 * aarch64-opc.h (verify_ldpsw): Remove.
466 * aarch64-tbl.h: Use VERIFIER for verifiers.
468 2016-04-28 Nick Clifton <nickc@redhat.com>
471 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
472 * aarch64-opc.c (verify_ldpsw): New function.
473 * aarch64-opc.h (verify_ldpsw): New prototype.
474 * aarch64-tbl.h: Add initialiser for verifier field.
475 (LDPSW): Set verifier to verify_ldpsw.
477 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
481 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
482 smaller than address size.
484 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
486 * alpha-dis.c: Regenerate.
487 * crx-dis.c: Likewise.
488 * disassemble.c: Likewise.
489 * epiphany-opc.c: Likewise.
490 * fr30-opc.c: Likewise.
491 * frv-opc.c: Likewise.
492 * ip2k-opc.c: Likewise.
493 * iq2000-opc.c: Likewise.
494 * lm32-opc.c: Likewise.
495 * lm32-opinst.c: Likewise.
496 * m32c-opc.c: Likewise.
497 * m32r-opc.c: Likewise.
498 * m32r-opinst.c: Likewise.
499 * mep-opc.c: Likewise.
500 * mt-opc.c: Likewise.
501 * or1k-opc.c: Likewise.
502 * or1k-opinst.c: Likewise.
503 * tic80-opc.c: Likewise.
504 * xc16x-opc.c: Likewise.
505 * xstormy16-opc.c: Likewise.
507 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
509 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
510 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
511 calcsd, and calcxd instructions.
512 * arc-opc.c (insert_nps_bitop_size): Delete.
513 (extract_nps_bitop_size): Delete.
514 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
515 (extract_nps_qcmp_m3): Define.
516 (extract_nps_qcmp_m2): Define.
517 (extract_nps_qcmp_m1): Define.
518 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
519 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
520 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
521 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
522 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
525 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
527 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
529 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
531 * Makefile.in: Regenerated with automake 1.11.6.
532 * aclocal.m4: Likewise.
534 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
536 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
538 * arc-opc.c (insert_nps_cmem_uimm16): New function.
539 (extract_nps_cmem_uimm16): New function.
540 (arc_operands): Add NPS_XLDST_UIMM16 operand.
542 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
544 * arc-dis.c (arc_insn_length): New function.
545 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
546 (find_format): Change insnLen parameter to unsigned.
548 2016-04-13 Nick Clifton <nickc@redhat.com>
551 * v850-opc.c (v850_opcodes): Correct masks for long versions of
552 the LD.B and LD.BU instructions.
554 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
556 * arc-dis.c (find_format): Check for extension flags.
557 (print_flags): New function.
558 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
560 * arc-ext.c (arcExtMap_coreRegName): Use
561 LAST_EXTENSION_CORE_REGISTER.
562 (arcExtMap_coreReadWrite): Likewise.
563 (dump_ARC_extmap): Update printing.
564 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
565 (arc_aux_regs): Add cpu field.
566 * arc-regs.h: Add cpu field, lower case name aux registers.
568 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
570 * arc-tbl.h: Add rtsc, sleep with no arguments.
572 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
574 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
576 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
577 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
578 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
579 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
580 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
581 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
582 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
583 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
584 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
585 (arc_opcode arc_opcodes): Null terminate the array.
586 (arc_num_opcodes): Remove.
587 * arc-ext.h (INSERT_XOP): Define.
588 (extInstruction_t): Likewise.
589 (arcExtMap_instName): Delete.
590 (arcExtMap_insn): New function.
591 (arcExtMap_genOpcode): Likewise.
592 * arc-ext.c (ExtInstruction): Remove.
593 (create_map): Zero initialize instruction fields.
594 (arcExtMap_instName): Remove.
595 (arcExtMap_insn): New function.
596 (dump_ARC_extmap): More info while debuging.
597 (arcExtMap_genOpcode): New function.
598 * arc-dis.c (find_format): New function.
599 (print_insn_arc): Use find_format.
600 (arc_get_disassembler): Enable dump_ARC_extmap only when
603 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
605 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
606 instruction bits out.
608 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
610 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
611 * arc-opc.c (arc_flag_operands): Add new flags.
612 (arc_flag_classes): Add new classes.
614 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
616 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
618 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
620 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
621 encode1, rflt, crc16, and crc32 instructions.
622 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
623 (arc_flag_classes): Add C_NPS_R.
624 (insert_nps_bitop_size_2b): New function.
625 (extract_nps_bitop_size_2b): Likewise.
626 (insert_nps_bitop_uimm8): Likewise.
627 (extract_nps_bitop_uimm8): Likewise.
628 (arc_operands): Add new operand entries.
630 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
632 * arc-regs.h: Add a new subclass field. Add double assist
633 accumulator register values.
634 * arc-tbl.h: Use DPA subclass to mark the double assist
635 instructions. Use DPX/SPX subclas to mark the FPX instructions.
636 * arc-opc.c (RSP): Define instead of SP.
637 (arc_aux_regs): Add the subclass field.
639 2016-04-05 Jiong Wang <jiong.wang@arm.com>
641 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
643 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
645 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
648 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
650 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
651 issues. No functional changes.
653 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
655 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
656 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
657 (RTT): Remove duplicate.
658 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
659 (PCT_CONFIG*): Remove.
660 (D1L, D1H, D2H, D2L): Define.
662 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
664 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
666 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
668 * arc-tbl.h (invld07): Remove.
669 * arc-ext-tbl.h: New file.
670 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
671 * arc-opc.c (arc_opcodes): Add ext-tbl include.
673 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
675 Fix -Wstack-usage warnings.
676 * aarch64-dis.c (print_operands): Substitute size.
677 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
679 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
681 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
682 to get a proper diagnostic when an invalid ASR register is used.
684 2016-03-22 Nick Clifton <nickc@redhat.com>
686 * configure: Regenerate.
688 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
690 * arc-nps400-tbl.h: New file.
691 * arc-opc.c: Add top level comment.
692 (insert_nps_3bit_dst): New function.
693 (extract_nps_3bit_dst): New function.
694 (insert_nps_3bit_src2): New function.
695 (extract_nps_3bit_src2): New function.
696 (insert_nps_bitop_size): New function.
697 (extract_nps_bitop_size): New function.
698 (arc_flag_operands): Add nps400 entries.
699 (arc_flag_classes): Add nps400 entries.
700 (arc_operands): Add nps400 entries.
701 (arc_opcodes): Add nps400 include.
703 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
705 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
706 the new class enum values.
708 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
710 * arc-dis.c (print_insn_arc): Handle nps400.
712 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
714 * arc-opc.c (BASE): Delete.
716 2016-03-18 Nick Clifton <nickc@redhat.com>
719 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
720 of MOV insn that aliases an ORR insn.
722 2016-03-16 Jiong Wang <jiong.wang@arm.com>
724 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
726 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
728 * mcore-opc.h: Add const qualifiers.
729 * microblaze-opc.h (struct op_code_struct): Likewise.
730 * sh-opc.h: Likewise.
731 * tic4x-dis.c (tic4x_print_indirect): Likewise.
732 (tic4x_print_op): Likewise.
734 2016-03-02 Alan Modra <amodra@gmail.com>
736 * or1k-desc.h: Regenerate.
737 * fr30-ibld.c: Regenerate.
738 * rl78-decode.c: Regenerate.
740 2016-03-01 Nick Clifton <nickc@redhat.com>
743 * rl78-dis.c (print_insn_rl78_common): Fix typo.
745 2016-02-24 Renlin Li <renlin.li@arm.com>
747 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
748 (print_insn_coprocessor): Support fp16 instructions.
750 2016-02-24 Renlin Li <renlin.li@arm.com>
752 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
755 2016-02-24 Renlin Li <renlin.li@arm.com>
757 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
758 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
760 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
762 * i386-dis.c (print_insn): Parenthesize expression to prevent
766 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
767 Janek van Oirschot <jvanoirs@synopsys.com>
769 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
772 2016-02-04 Nick Clifton <nickc@redhat.com>
775 * msp430-dis.c (print_insn_msp430): Add a special case for
776 decoding an RRC instruction with the ZC bit set in the extension
779 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
781 * cgen-ibld.in (insert_normal): Rework calculation of shift.
782 * epiphany-ibld.c: Regenerate.
783 * fr30-ibld.c: Regenerate.
784 * frv-ibld.c: Regenerate.
785 * ip2k-ibld.c: Regenerate.
786 * iq2000-ibld.c: Regenerate.
787 * lm32-ibld.c: Regenerate.
788 * m32c-ibld.c: Regenerate.
789 * m32r-ibld.c: Regenerate.
790 * mep-ibld.c: Regenerate.
791 * mt-ibld.c: Regenerate.
792 * or1k-ibld.c: Regenerate.
793 * xc16x-ibld.c: Regenerate.
794 * xstormy16-ibld.c: Regenerate.
796 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
798 * epiphany-dis.c: Regenerated from latest cpu files.
800 2016-02-01 Michael McConville <mmcco@mykolab.com>
802 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
805 2016-01-25 Renlin Li <renlin.li@arm.com>
807 * arm-dis.c (mapping_symbol_for_insn): New function.
808 (find_ifthen_state): Call mapping_symbol_for_insn().
810 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
812 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
813 of MSR UAO immediate operand.
815 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
817 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
820 2016-01-17 Alan Modra <amodra@gmail.com>
822 * configure: Regenerate.
824 2016-01-14 Nick Clifton <nickc@redhat.com>
826 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
827 instructions that can support stack pointer operations.
828 * rl78-decode.c: Regenerate.
829 * rl78-dis.c: Fix display of stack pointer in MOVW based
832 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
834 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
835 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
836 erxtatus_el1 and erxaddr_el1.
838 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
840 * arm-dis.c (arm_opcodes): Add "esb".
841 (thumb_opcodes): Likewise.
843 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
845 * ppc-opc.c <xscmpnedp>: Delete.
846 <xvcmpnedp>: Likewise.
847 <xvcmpnedp.>: Likewise.
848 <xvcmpnesp>: Likewise.
849 <xvcmpnesp.>: Likewise.
851 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
854 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
857 2016-01-01 Alan Modra <amodra@gmail.com>
859 Update year range in copyright notice of all files.
861 For older changes see ChangeLog-2015
863 Copyright (C) 2016 Free Software Foundation, Inc.
865 Copying and distribution of this file, with or without modification,
866 are permitted in any medium without royalty provided the copyright
867 notice and this notice are preserved.
873 version-control: never