1 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
3 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
6 2017-07-20 Nick Clifton <nickc@redhat.com>
8 * po/de.po: Updated German translation.
10 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
12 * arc-regs.h (sec_stat): New aux register.
13 (aux_kernel_sp): Likewise.
14 (aux_sec_u_sp): Likewise.
15 (aux_sec_k_sp): Likewise.
16 (sec_vecbase_build): Likewise.
17 (nsc_table_top): Likewise.
18 (nsc_table_base): Likewise.
19 (ersec_stat): Likewise.
20 (aux_sec_except): Likewise.
22 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
24 * arc-opc.c (extract_uimm12_20): New function.
25 (UIMM12_20): New operand.
27 * arc-tbl.h (sjli): Add new instruction.
29 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
30 John Eric Martin <John.Martin@emmicro-us.com>
32 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
33 (UIMM3_23): Adjust accordingly.
34 * arc-regs.h: Add/correct jli_base register.
35 * arc-tbl.h (jli_s): Likewise.
37 2017-07-18 Nick Clifton <nickc@redhat.com>
40 * aarch64-opc.c: Fix spelling typos.
41 * i386-dis.c: Likewise.
43 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
45 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
46 max_addr_offset and octets variables to size_t.
48 2017-07-12 Alan Modra <amodra@gmail.com>
50 * po/da.po: Update from translationproject.org/latest/opcodes/.
58 * po/pt_BR.po: Likewise.
64 * po/zh_CN.po: Likewise.
66 2017-07-11 Yao Qi <yao.qi@linaro.org>
67 Alan Modra <amodra@gmail.com>
69 * cgen.sh: Mark generated files read-only.
70 * epiphany-asm.c: Regenerate.
71 * epiphany-desc.c: Regenerate.
72 * epiphany-desc.h: Regenerate.
73 * epiphany-dis.c: Regenerate.
74 * epiphany-ibld.c: Regenerate.
75 * epiphany-opc.c: Regenerate.
76 * epiphany-opc.h: Regenerate.
77 * fr30-asm.c: Regenerate.
78 * fr30-desc.c: Regenerate.
79 * fr30-desc.h: Regenerate.
80 * fr30-dis.c: Regenerate.
81 * fr30-ibld.c: Regenerate.
82 * fr30-opc.c: Regenerate.
83 * fr30-opc.h: Regenerate.
84 * frv-asm.c: Regenerate.
85 * frv-desc.c: Regenerate.
86 * frv-desc.h: Regenerate.
87 * frv-dis.c: Regenerate.
88 * frv-ibld.c: Regenerate.
89 * frv-opc.c: Regenerate.
90 * frv-opc.h: Regenerate.
91 * ip2k-asm.c: Regenerate.
92 * ip2k-desc.c: Regenerate.
93 * ip2k-desc.h: Regenerate.
94 * ip2k-dis.c: Regenerate.
95 * ip2k-ibld.c: Regenerate.
96 * ip2k-opc.c: Regenerate.
97 * ip2k-opc.h: Regenerate.
98 * iq2000-asm.c: Regenerate.
99 * iq2000-desc.c: Regenerate.
100 * iq2000-desc.h: Regenerate.
101 * iq2000-dis.c: Regenerate.
102 * iq2000-ibld.c: Regenerate.
103 * iq2000-opc.c: Regenerate.
104 * iq2000-opc.h: Regenerate.
105 * lm32-asm.c: Regenerate.
106 * lm32-desc.c: Regenerate.
107 * lm32-desc.h: Regenerate.
108 * lm32-dis.c: Regenerate.
109 * lm32-ibld.c: Regenerate.
110 * lm32-opc.c: Regenerate.
111 * lm32-opc.h: Regenerate.
112 * lm32-opinst.c: Regenerate.
113 * m32c-asm.c: Regenerate.
114 * m32c-desc.c: Regenerate.
115 * m32c-desc.h: Regenerate.
116 * m32c-dis.c: Regenerate.
117 * m32c-ibld.c: Regenerate.
118 * m32c-opc.c: Regenerate.
119 * m32c-opc.h: Regenerate.
120 * m32r-asm.c: Regenerate.
121 * m32r-desc.c: Regenerate.
122 * m32r-desc.h: Regenerate.
123 * m32r-dis.c: Regenerate.
124 * m32r-ibld.c: Regenerate.
125 * m32r-opc.c: Regenerate.
126 * m32r-opc.h: Regenerate.
127 * m32r-opinst.c: Regenerate.
128 * mep-asm.c: Regenerate.
129 * mep-desc.c: Regenerate.
130 * mep-desc.h: Regenerate.
131 * mep-dis.c: Regenerate.
132 * mep-ibld.c: Regenerate.
133 * mep-opc.c: Regenerate.
134 * mep-opc.h: Regenerate.
135 * mt-asm.c: Regenerate.
136 * mt-desc.c: Regenerate.
137 * mt-desc.h: Regenerate.
138 * mt-dis.c: Regenerate.
139 * mt-ibld.c: Regenerate.
140 * mt-opc.c: Regenerate.
141 * mt-opc.h: Regenerate.
142 * or1k-asm.c: Regenerate.
143 * or1k-desc.c: Regenerate.
144 * or1k-desc.h: Regenerate.
145 * or1k-dis.c: Regenerate.
146 * or1k-ibld.c: Regenerate.
147 * or1k-opc.c: Regenerate.
148 * or1k-opc.h: Regenerate.
149 * or1k-opinst.c: Regenerate.
150 * xc16x-asm.c: Regenerate.
151 * xc16x-desc.c: Regenerate.
152 * xc16x-desc.h: Regenerate.
153 * xc16x-dis.c: Regenerate.
154 * xc16x-ibld.c: Regenerate.
155 * xc16x-opc.c: Regenerate.
156 * xc16x-opc.h: Regenerate.
157 * xstormy16-asm.c: Regenerate.
158 * xstormy16-desc.c: Regenerate.
159 * xstormy16-desc.h: Regenerate.
160 * xstormy16-dis.c: Regenerate.
161 * xstormy16-ibld.c: Regenerate.
162 * xstormy16-opc.c: Regenerate.
163 * xstormy16-opc.h: Regenerate.
165 2017-07-07 Alan Modra <amodra@gmail.com>
167 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
168 * m32c-dis.c: Regenerate.
169 * mep-dis.c: Regenerate.
171 2017-07-05 Borislav Petkov <bp@suse.de>
173 * i386-dis.c: Enable ModRM.reg /6 aliases.
175 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
177 * opcodes/arm-dis.c: Support MVFR2 in disassembly
180 2017-07-04 Tristan Gingold <gingold@adacore.com>
182 * configure: Regenerate.
184 2017-07-03 Tristan Gingold <gingold@adacore.com>
186 * po/opcodes.pot: Regenerate.
188 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
190 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
191 entries to the MSA ASE instruction block.
193 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
194 Maciej W. Rozycki <macro@imgtec.com>
196 * micromips-opc.c (XPA, XPAVZ): New macros.
197 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
200 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
201 Maciej W. Rozycki <macro@imgtec.com>
203 * micromips-opc.c (I36): New macro.
204 (micromips_opcodes): Add "eretnc".
206 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
207 Andrew Bennett <andrew.bennett@imgtec.com>
209 * mips-dis.c (mips_calculate_combination_ases): Handle the
211 (parse_mips_ase_option): New function.
212 (parse_mips_dis_option): Factor out ASE option handling to the
213 new function. Call `mips_calculate_combination_ases'.
214 * mips-opc.c (XPAVZ): New macro.
215 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
216 "mfhgc0", "mthc0" and "mthgc0".
218 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
220 * mips-dis.c (mips_calculate_combination_ases): New function.
221 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
222 calculation to the new function.
223 (set_default_mips_dis_options): Call the new function.
225 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
227 * arc-dis.c (parse_disassembler_options): Use
228 FOR_EACH_DISASSEMBLER_OPTION.
230 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
232 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
233 disassembler option strings.
234 (parse_cpu_option): Likewise.
236 2017-06-28 Tamar Christina <tamar.christina@arm.com>
238 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
239 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
240 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
241 (aarch64_feature_dotprod, DOT_INSN): New.
243 * aarch64-dis-2.c: Regenerated.
245 2017-06-28 Jiong Wang <jiong.wang@arm.com>
247 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
249 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
250 Matthew Fortune <matthew.fortune@imgtec.com>
251 Andrew Bennett <andrew.bennett@imgtec.com>
253 * mips-formats.h (INT_BIAS): New macro.
254 (INT_ADJ): Redefine in INT_BIAS terms.
255 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
256 (mips_print_save_restore): New function.
257 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
258 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
260 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
261 (print_mips16_insn_arg): Call `mips_print_save_restore' for
262 OP_SAVE_RESTORE_LIST handling, factored out from here.
263 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
264 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
265 (mips_builtin_opcodes): Add "restore" and "save" entries.
266 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
268 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
270 2017-06-23 Andrew Waterman <andrew@sifive.com>
272 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
273 alias; do not mark SLTI instruction as an alias.
275 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
277 * i386-dis.c (RM_0FAE_REG_5): Removed.
278 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
279 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
280 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
281 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
282 PREFIX_MOD_3_0F01_REG_5_RM_0.
283 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
284 PREFIX_MOD_3_0FAE_REG_5.
285 (mod_table): Update MOD_0FAE_REG_5.
286 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
287 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
288 * i386-tbl.h: Regenerated.
290 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
292 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
293 * i386-opc.tbl: Likewise.
294 * i386-tbl.h: Regenerated.
296 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
298 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
300 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
303 2017-06-19 Nick Clifton <nickc@redhat.com>
306 * score-dis.c (score_opcodes): Add sentinel.
308 2017-06-16 Alan Modra <amodra@gmail.com>
310 * rx-decode.c: Regenerate.
312 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
315 * i386-dis.c (OP_E_register): Check valid bnd register.
318 2017-06-15 Nick Clifton <nickc@redhat.com>
321 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
324 2017-06-15 Nick Clifton <nickc@redhat.com>
327 * rl78-decode.opc (OP_BUF_LEN): Define.
328 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
329 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
331 * rl78-decode.c: Regenerate.
333 2017-06-15 Nick Clifton <nickc@redhat.com>
336 * bfin-dis.c (gregs): Clip index to prevent overflow.
341 2017-06-14 Nick Clifton <nickc@redhat.com>
344 * score7-dis.c (score_opcodes): Add sentinel.
346 2017-06-14 Yao Qi <yao.qi@linaro.org>
348 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
349 * arm-dis.c: Likewise.
350 * ia64-dis.c: Likewise.
351 * mips-dis.c: Likewise.
352 * spu-dis.c: Likewise.
353 * disassemble.h (print_insn_aarch64): New declaration, moved from
355 (print_insn_big_arm, print_insn_big_mips): Likewise.
356 (print_insn_i386, print_insn_ia64): Likewise.
357 (print_insn_little_arm, print_insn_little_mips): Likewise.
359 2017-06-14 Nick Clifton <nickc@redhat.com>
362 * rx-decode.opc: Include libiberty.h
363 (GET_SCALE): New macro - validates access to SCALE array.
364 (GET_PSCALE): New macro - validates access to PSCALE array.
365 (DIs, SIs, S2Is, rx_disp): Use new macros.
366 * rx-decode.c: Regenerate.
368 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
370 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
372 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
374 * arc-dis.c (enforced_isa_mask): Declare.
375 (cpu_types): Likewise.
376 (parse_cpu_option): New function.
377 (parse_disassembler_options): Use it.
378 (print_insn_arc): Use enforced_isa_mask.
379 (print_arc_disassembler_options): Document new options.
381 2017-05-24 Yao Qi <yao.qi@linaro.org>
383 * alpha-dis.c: Include disassemble.h, don't include
385 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
386 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
387 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
388 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
389 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
390 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
391 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
392 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
393 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
394 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
395 * moxie-dis.c, msp430-dis.c, mt-dis.c:
396 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
397 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
398 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
399 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
400 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
401 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
402 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
403 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
404 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
405 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
406 * z80-dis.c, z8k-dis.c: Likewise.
407 * disassemble.h: New file.
409 2017-05-24 Yao Qi <yao.qi@linaro.org>
411 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
412 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
414 2017-05-24 Yao Qi <yao.qi@linaro.org>
416 * disassemble.c (disassembler): Add arguments a, big and mach.
419 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
421 * i386-dis.c (NOTRACK_Fixup): New.
423 (NOTRACK_PREFIX): Likewise.
424 (last_active_prefix): Likewise.
425 (reg_table): Use NOTRACK on indirect call and jmp.
426 (ckprefix): Set last_active_prefix.
427 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
428 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
429 * i386-opc.h (NoTrackPrefixOk): New.
430 (i386_opcode_modifier): Add notrackprefixok.
431 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
433 * i386-tbl.h: Regenerated.
435 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
437 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
439 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
441 (print_insn_sparc): Handle new operand types.
442 * sparc-opc.c (MASK_M8): Define.
444 (v6notlet): Likewise.
455 (v9andleon): Likewise.
458 (HWS2_VM8): Likewise.
459 (sparc_opcode_archs): Add entry for "m8".
460 (sparc_opcodes): Add OSA2017 and M8 instructions
461 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
463 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
464 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
465 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
466 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
467 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
468 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
469 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
470 ASI_CORE_SELECT_COMMIT_NHT.
472 2017-05-18 Alan Modra <amodra@gmail.com>
474 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
475 * aarch64-dis.c: Likewise.
476 * aarch64-gen.c: Likewise.
477 * aarch64-opc.c: Likewise.
479 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
480 Matthew Fortune <matthew.fortune@imgtec.com>
482 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
483 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
484 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
485 (print_insn_arg) <OP_REG28>: Add handler.
486 (validate_insn_args) <OP_REG28>: Handle.
487 (print_mips16_insn_arg): Handle MIPS16 instructions that require
488 32-bit encoding and 9-bit immediates.
489 (print_insn_mips16): Handle MIPS16 instructions that require
490 32-bit encoding and MFC0/MTC0 operand decoding.
491 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
492 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
493 (RD_C0, WR_C0, E2, E2MT): New macros.
494 (mips16_opcodes): Add entries for MIPS16e2 instructions:
495 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
496 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
497 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
498 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
499 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
500 instructions, "swl", "swr", "sync" and its "sync_acquire",
501 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
502 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
503 regular/extended entries for original MIPS16 ISA revision
504 instructions whose extended forms are subdecoded in the MIPS16e2
505 ISA revision: "li", "sll" and "srl".
507 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
509 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
510 reference in CP0 move operand decoding.
512 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
514 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
516 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
518 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
520 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
521 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
522 "sync_rmb" and "sync_wmb" as aliases.
523 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
524 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
526 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
528 * arc-dis.c (parse_option): Update quarkse_em option..
529 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
531 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
533 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
535 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
537 2017-05-01 Michael Clark <michaeljclark@mac.com>
539 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
542 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
544 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
545 and branches and not synthetic data instructions.
547 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
549 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
551 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
553 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
554 * arc-opc.c (insert_r13el): New function.
556 * arc-tbl.h: Add new enter/leave variants.
558 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
560 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
562 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
564 * mips-dis.c (print_mips_disassembler_options): Add
567 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
569 * mips16-opc.c (AL): New macro.
570 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
571 of "ld" and "lw" as aliases.
573 2017-04-24 Tamar Christina <tamar.christina@arm.com>
575 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
578 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
579 Alan Modra <amodra@gmail.com>
581 * ppc-opc.c (ELEV): Define.
582 (vle_opcodes): Add se_rfgi and e_sc.
583 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
586 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
588 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
590 2017-04-21 Nick Clifton <nickc@redhat.com>
593 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
596 2017-04-13 Alan Modra <amodra@gmail.com>
598 * epiphany-desc.c: Regenerate.
599 * fr30-desc.c: Regenerate.
600 * frv-desc.c: Regenerate.
601 * ip2k-desc.c: Regenerate.
602 * iq2000-desc.c: Regenerate.
603 * lm32-desc.c: Regenerate.
604 * m32c-desc.c: Regenerate.
605 * m32r-desc.c: Regenerate.
606 * mep-desc.c: Regenerate.
607 * mt-desc.c: Regenerate.
608 * or1k-desc.c: Regenerate.
609 * xc16x-desc.c: Regenerate.
610 * xstormy16-desc.c: Regenerate.
612 2017-04-11 Alan Modra <amodra@gmail.com>
614 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
615 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
616 PPC_OPCODE_TMR for e6500.
617 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
618 (PPCVEC3): Define as PPC_OPCODE_POWER9.
619 (PPCVSX2): Define as PPC_OPCODE_POWER8.
620 (PPCVSX3): Define as PPC_OPCODE_POWER9.
621 (PPCHTM): Define as PPC_OPCODE_POWER8.
622 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
624 2017-04-10 Alan Modra <amodra@gmail.com>
626 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
627 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
628 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
629 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
631 2017-04-09 Pip Cet <pipcet@gmail.com>
633 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
634 appropriate floating-point precision directly.
636 2017-04-07 Alan Modra <amodra@gmail.com>
638 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
639 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
640 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
641 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
642 vector instructions with E6500 not PPCVEC2.
644 2017-04-06 Pip Cet <pipcet@gmail.com>
646 * Makefile.am: Add wasm32-dis.c.
647 * configure.ac: Add wasm32-dis.c to wasm32 target.
648 * disassemble.c: Add wasm32 disassembler code.
649 * wasm32-dis.c: New file.
650 * Makefile.in: Regenerate.
651 * configure: Regenerate.
652 * po/POTFILES.in: Regenerate.
653 * po/opcodes.pot: Regenerate.
655 2017-04-05 Pedro Alves <palves@redhat.com>
657 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
658 * arm-dis.c (parse_arm_disassembler_options): Constify.
659 * ppc-dis.c (powerpc_init_dialect): Constify local.
660 * vax-dis.c (parse_disassembler_options): Constify.
662 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
664 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
667 2017-03-30 Pip Cet <pipcet@gmail.com>
669 * configure.ac: Add (empty) bfd_wasm32_arch target.
670 * configure: Regenerate
671 * po/opcodes.pot: Regenerate.
673 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
675 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
677 * opcodes/sparc-opc.c (asi_table): New ASIs.
679 2017-03-29 Alan Modra <amodra@gmail.com>
681 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
683 (lookup_powerpc): Don't special case -1 dialect. Handle
685 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
686 lookup_powerpc call, pass it on second.
688 2017-03-27 Alan Modra <amodra@gmail.com>
691 * ppc-dis.c (struct ppc_mopt): Comment.
692 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
694 2017-03-27 Rinat Zelig <rinat@mellanox.com>
696 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
697 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
698 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
699 (insert_nps_misc_imm_offset): New function.
700 (extract_nps_misc imm_offset): New function.
701 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
702 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
704 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
706 * s390-mkopc.c (main): Remove vx2 check.
707 * s390-opc.txt: Remove vx2 instruction flags.
709 2017-03-21 Rinat Zelig <rinat@mellanox.com>
711 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
712 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
713 (insert_nps_imm_offset): New function.
714 (extract_nps_imm_offset): New function.
715 (insert_nps_imm_entry): New function.
716 (extract_nps_imm_entry): New function.
718 2017-03-17 Alan Modra <amodra@gmail.com>
721 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
722 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
723 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
725 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
727 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
731 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
733 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
735 2017-03-13 Andrew Waterman <andrew@sifive.com>
737 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
742 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
744 * i386-gen.c (opcode_modifiers): Replace S with Load.
745 * i386-opc.h (S): Removed.
747 (i386_opcode_modifier): Replace s with load.
748 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
749 and {evex}. Replace S with Load.
750 * i386-tbl.h: Regenerated.
752 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
754 * i386-opc.tbl: Use CpuCET on rdsspq.
755 * i386-tbl.h: Regenerated.
757 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
759 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
760 <vsx>: Do not use PPC_OPCODE_VSX3;
762 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
764 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
766 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
768 * i386-dis.c (REG_0F1E_MOD_3): New enum.
769 (MOD_0F1E_PREFIX_1): Likewise.
770 (MOD_0F38F5_PREFIX_2): Likewise.
771 (MOD_0F38F6_PREFIX_0): Likewise.
772 (RM_0F1E_MOD_3_REG_7): Likewise.
773 (PREFIX_MOD_0_0F01_REG_5): Likewise.
774 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
775 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
776 (PREFIX_0F1E): Likewise.
777 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
778 (PREFIX_0F38F5): Likewise.
779 (dis386_twobyte): Use PREFIX_0F1E.
780 (reg_table): Add REG_0F1E_MOD_3.
781 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
782 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
783 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
784 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
785 (three_byte_table): Use PREFIX_0F38F5.
786 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
787 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
788 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
789 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
790 PREFIX_MOD_3_0F01_REG_5_RM_2.
791 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
792 (cpu_flags): Add CpuCET.
793 * i386-opc.h (CpuCET): New enum.
794 (CpuUnused): Commented out.
795 (i386_cpu_flags): Add cpucet.
796 * i386-opc.tbl: Add Intel CET instructions.
797 * i386-init.h: Regenerated.
798 * i386-tbl.h: Likewise.
800 2017-03-06 Alan Modra <amodra@gmail.com>
803 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
804 (extract_raq, extract_ras, extract_rbx): New functions.
805 (powerpc_operands): Use opposite corresponding insert function.
807 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
808 register restriction.
810 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
812 * disassemble.c Include "safe-ctype.h".
813 (disassemble_init_for_target): Handle s390 init.
814 (remove_whitespace_and_extra_commas): New function.
815 (disassembler_options_cmp): Likewise.
816 * arm-dis.c: Include "libiberty.h".
818 (regnames): Use long disassembler style names.
819 Add force-thumb and no-force-thumb options.
820 (NUM_ARM_REGNAMES): Rename from this...
821 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
822 (get_arm_regname_num_options): Delete.
823 (set_arm_regname_option): Likewise.
824 (get_arm_regnames): Likewise.
825 (parse_disassembler_options): Likewise.
826 (parse_arm_disassembler_option): Rename from this...
827 (parse_arm_disassembler_options): ...to this. Make static.
828 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
829 (print_insn): Use parse_arm_disassembler_options.
830 (disassembler_options_arm): New function.
831 (print_arm_disassembler_options): Handle updated regnames.
832 * ppc-dis.c: Include "libiberty.h".
833 (ppc_opts): Add "32" and "64" entries.
834 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
835 (powerpc_init_dialect): Add break to switch statement.
836 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
837 (disassembler_options_powerpc): New function.
838 (print_ppc_disassembler_options): Use ARRAY_SIZE.
839 Remove printing of "32" and "64".
840 * s390-dis.c: Include "libiberty.h".
841 (init_flag): Remove unneeded variable.
842 (struct s390_options_t): New structure type.
843 (options): New structure.
844 (init_disasm): Rename from this...
845 (disassemble_init_s390): ...to this. Add initializations for
846 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
847 (print_insn_s390): Delete call to init_disasm.
848 (disassembler_options_s390): New function.
849 (print_s390_disassembler_options): Print using information from
851 * po/opcodes.pot: Regenerate.
853 2017-02-28 Jan Beulich <jbeulich@suse.com>
855 * i386-dis.c (PCMPESTR_Fixup): New.
856 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
857 (prefix_table): Use PCMPESTR_Fixup.
858 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
860 (vex_w_table): Delete VPCMPESTR{I,M} entries.
861 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
862 Split 64-bit and non-64-bit variants.
863 * opcodes/i386-tbl.h: Re-generate.
865 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
867 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
868 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
869 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
870 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
871 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
872 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
873 (OP_SVE_V_HSD): New macros.
874 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
875 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
876 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
877 (aarch64_opcode_table): Add new SVE instructions.
878 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
879 for rotation operands. Add new SVE operands.
880 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
881 (ins_sve_quad_index): Likewise.
882 (ins_imm_rotate): Split into...
883 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
884 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
885 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
887 (aarch64_ins_sve_addr_ri_s4): New function.
888 (aarch64_ins_sve_quad_index): Likewise.
889 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
890 * aarch64-asm-2.c: Regenerate.
891 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
892 (ext_sve_quad_index): Likewise.
893 (ext_imm_rotate): Split into...
894 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
895 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
896 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
898 (aarch64_ext_sve_addr_ri_s4): New function.
899 (aarch64_ext_sve_quad_index): Likewise.
900 (aarch64_ext_sve_index): Allow quad indices.
901 (do_misc_decoding): Likewise.
902 * aarch64-dis-2.c: Regenerate.
903 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
905 (OPD_F_OD_MASK): Widen by one bit.
906 (OPD_F_NO_ZR): Bump accordingly.
907 (get_operand_field_width): New function.
908 * aarch64-opc.c (fields): Add new SVE fields.
909 (operand_general_constraint_met_p): Handle new SVE operands.
910 (aarch64_print_operand): Likewise.
911 * aarch64-opc-2.c: Regenerate.
913 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
915 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
916 (aarch64_feature_compnum): ...this.
917 (SIMD_V8_3): Replace with...
919 (CNUM_INSN): New macro.
920 (aarch64_opcode_table): Use it for the complex number instructions.
922 2017-02-24 Jan Beulich <jbeulich@suse.com>
924 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
926 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
928 Add support for associating SPARC ASIs with an architecture level.
929 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
930 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
931 decoding of SPARC ASIs.
933 2017-02-23 Jan Beulich <jbeulich@suse.com>
935 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
936 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
938 2017-02-21 Jan Beulich <jbeulich@suse.com>
940 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
941 1 (instead of to itself). Correct typo.
943 2017-02-14 Andrew Waterman <andrew@sifive.com>
945 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
948 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
950 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
951 (aarch64_sys_reg_supported_p): Handle them.
953 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
955 * arc-opc.c (UIMM6_20R): Define.
956 (SIMM12_20): Use above.
957 (SIMM12_20R): Define.
958 (SIMM3_5_S): Use above.
959 (UIMM7_A32_11R_S): Define.
960 (UIMM7_9_S): Use above.
961 (UIMM3_13R_S): Define.
962 (SIMM11_A32_7_S): Use above.
964 (UIMM10_A32_8_S): Use above.
965 (UIMM8_8R_S): Define.
967 (arc_relax_opcodes): Use all above defines.
969 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
971 * arc-regs.h: Distinguish some of the registers different on
972 ARC700 and HS38 cpus.
974 2017-02-14 Alan Modra <amodra@gmail.com>
977 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
978 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
980 2017-02-11 Stafford Horne <shorne@gmail.com>
981 Alan Modra <amodra@gmail.com>
983 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
984 Use insn_bytes_value and insn_int_value directly instead. Don't
985 free allocated memory until function exit.
987 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
989 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
991 2017-02-03 Nick Clifton <nickc@redhat.com>
994 * aarch64-opc.c (print_register_list): Ensure that the register
995 list index will fir into the tb buffer.
996 (print_register_offset_address): Likewise.
997 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
999 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1002 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1003 instructions when the previous fetch packet ends with a 32-bit
1006 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1008 * pru-opc.c: Remove vague reference to a future GDB port.
1010 2017-01-20 Nick Clifton <nickc@redhat.com>
1012 * po/ga.po: Updated Irish translation.
1014 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1016 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1018 2017-01-13 Yao Qi <yao.qi@linaro.org>
1020 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1021 if FETCH_DATA returns 0.
1022 (m68k_scan_mask): Likewise.
1023 (print_insn_m68k): Update code to handle -1 return value.
1025 2017-01-13 Yao Qi <yao.qi@linaro.org>
1027 * m68k-dis.c (enum print_insn_arg_error): New.
1028 (NEXTBYTE): Replace -3 with
1029 PRINT_INSN_ARG_MEMORY_ERROR.
1030 (NEXTULONG): Likewise.
1031 (NEXTSINGLE): Likewise.
1032 (NEXTDOUBLE): Likewise.
1033 (NEXTDOUBLE): Likewise.
1034 (NEXTPACKED): Likewise.
1035 (FETCH_ARG): Likewise.
1036 (FETCH_DATA): Update comments.
1037 (print_insn_arg): Update comments. Replace magic numbers with
1039 (match_insn_m68k): Likewise.
1041 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1043 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1044 * i386-dis-evex.h (evex_table): Updated.
1045 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1046 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1047 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1048 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1049 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1050 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1051 * i386-init.h: Regenerate.
1052 * i386-tbl.h: Ditto.
1054 2017-01-12 Yao Qi <yao.qi@linaro.org>
1056 * msp430-dis.c (msp430_singleoperand): Return -1 if
1057 msp430dis_opcode_signed returns false.
1058 (msp430_doubleoperand): Likewise.
1059 (msp430_branchinstr): Return -1 if
1060 msp430dis_opcode_unsigned returns false.
1061 (msp430x_calla_instr): Likewise.
1062 (print_insn_msp430): Likewise.
1064 2017-01-05 Nick Clifton <nickc@redhat.com>
1067 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1068 could not be matched.
1069 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1072 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1074 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1075 (aarch64_opcode_table): Use RCPC_INSN.
1077 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1079 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1081 * riscv-opcodes/all-opcodes: Likewise.
1083 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1085 * riscv-dis.c (print_insn_args): Add fall through comment.
1087 2017-01-03 Nick Clifton <nickc@redhat.com>
1089 * po/sr.po: New Serbian translation.
1090 * configure.ac (ALL_LINGUAS): Add sr.
1091 * configure: Regenerate.
1093 2017-01-02 Alan Modra <amodra@gmail.com>
1095 * epiphany-desc.h: Regenerate.
1096 * epiphany-opc.h: Regenerate.
1097 * fr30-desc.h: Regenerate.
1098 * fr30-opc.h: Regenerate.
1099 * frv-desc.h: Regenerate.
1100 * frv-opc.h: Regenerate.
1101 * ip2k-desc.h: Regenerate.
1102 * ip2k-opc.h: Regenerate.
1103 * iq2000-desc.h: Regenerate.
1104 * iq2000-opc.h: Regenerate.
1105 * lm32-desc.h: Regenerate.
1106 * lm32-opc.h: Regenerate.
1107 * m32c-desc.h: Regenerate.
1108 * m32c-opc.h: Regenerate.
1109 * m32r-desc.h: Regenerate.
1110 * m32r-opc.h: Regenerate.
1111 * mep-desc.h: Regenerate.
1112 * mep-opc.h: Regenerate.
1113 * mt-desc.h: Regenerate.
1114 * mt-opc.h: Regenerate.
1115 * or1k-desc.h: Regenerate.
1116 * or1k-opc.h: Regenerate.
1117 * xc16x-desc.h: Regenerate.
1118 * xc16x-opc.h: Regenerate.
1119 * xstormy16-desc.h: Regenerate.
1120 * xstormy16-opc.h: Regenerate.
1122 2017-01-02 Alan Modra <amodra@gmail.com>
1124 Update year range in copyright notice of all files.
1126 For older changes see ChangeLog-2016
1128 Copyright (C) 2017 Free Software Foundation, Inc.
1130 Copying and distribution of this file, with or without modification,
1131 are permitted in any medium without royalty provided the copyright
1132 notice and this notice are preserved.
1138 version-control: never