opcodes/ChangeLog

   1 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
   2
   3         * mips-dis.c (mips_arch_choices): Add loongson3a.
   4         * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
   5         (mips_builtin_opcodes): Modify some instructions' membership from
   6         IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
   7
   8 2010-11-10  Nick Clifton  <nickc@redhat.com>
   9
  10         * po/fi.po: Updated Finnish translation.
  11
  12 2010-11-05  Tristan Gingold  <gingold@adacore.com>
  13
  14         * po/opcodes.pot: Regenerate
  15
  16 2010-10-28  Maciej W. Rozycki  <macro@codesourcery.com>
  17
  18         * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
  19
  20 2010-10-28  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  21
  22         * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
  23
  24 2010-10-25  Chao-ying Fu  <fu@mips.com>
  25
  26         * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
  27
  28 2010-10-25  Nathan Sidwell  <nathan@codesourcery.com>
  29
  30         * tic6x-dis.c: Add attribution.
  31
  32 2010-10-22  Alan Modra  <amodra@gmail.com>
  33
  34         * Makefile.am (CLEANFILES): Add stamp-lm32.  Sort.
  35         * Makefile.in: Regenerate.
  36
  37 2010-10-18  Maciej W. Rozycki  <macro@linux-mips.org>
  38
  39         * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
  40         macros before their corresponding MIPS III hardware instructions.
  41
  42 2010-10-16  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
  45
  46         * i386-init.h: Regenerated.
  47
  48 2010-10-15  Mike Frysinger  <vapier@gentoo.org>
  49
  50         * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
  51
  52 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  53
  54         * i386-opc.tbl: Remove CheckRegSize from movq.
  55         * i386-tbl.h: Regenerated.
  56
  57 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  58
  59         * i386-opc.tbl: Remove CheckRegSize from instructions with
  60         0, 1 or fixed operands.
  61         * i386-tbl.h: Regenerated.
  62
  63 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         * i386-gen.c (opcode_modifiers): Add CheckRegSize.
  66
  67         * i386-opc.h (CheckRegSize): New.
  68         (i386_opcode_modifier): Add checkregsize.
  69
  70         * i386-opc.tbl: Add CheckRegSize to instructions which
  71         require register size check.
  72         * i386-tbl.h: Regenerated.
  73
  74 2010-10-12  Andreas Schwab  <schwab@linux-m68k.org>
  75
  76         * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
  77
  78 2010-10-11  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  79
  80         * s390-opc.c: Make the instruction masks for the load/store on
  81         condition instructions to cover the condition code mask as well.
  82         * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
  83
  84 2010-10-11  Jan Kratochvil  <jan.kratochvil@redhat.com>
  85             Jiang Jilin  <freephp@gmail.com>
  86
  87         * Makefile.am (libopcodes_a_SOURCES): New as empty.
  88         * Makefile.in: Regenerate.
  89
  90 2010-10-09  Matt Rice  <ratmice@gmail.com>
  91
  92         * fr30-desc.h: Regenerate.
  93         * frv-desc.h: Regenerate.
  94         * ip2k-desc.h: Regenerate.
  95         * iq2000-desc.h: Regenerate.
  96         * lm32-desc.h: Regenerate.
  97         * m32c-desc.h: Regenerate.
  98         * m32r-desc.h: Regenerate.
  99         * mep-desc.h: Regenerate.
 100         * mep-opc.c: Regenerate.
 101         * mt-desc.h: Regenerate.
 102         * openrisc-desc.h: Regenerate.
 103         * xc16x-desc.h: Regenerate.
 104         * xstormy16-desc.h: Regenerate.
 105
 106 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
 107
 108         Fix build with -DDEBUG=7
 109         * frv-opc.c: Regenerate.
 110         * or32-dis.c (DEBUG): Don't redefine.
 111         (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
 112         Adapt DEBUG code to some type changes throughout.
 113         * or32-opc.c (or32_extract): Likewise.
 114
 115 2010-10-07  Bernd Schmidt  <bernds@codesourcery.com>
 116
 117         * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
 118         in SPKERNEL instructions.
 119
 120 2010-10-02  H.J. Lu  <hongjiu.lu@intel.com>
 121
 122         PR binutils/12076
 123         * i386-dis.c (RMAL): Remove duplicate.
 124
 125 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
 126
 127         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
 128         to parse all 6 parameters.
 129
 130 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
 131
 132         * s390-mkopc.c (main): Change description array size to 80.
 133         Add maximum length of 79 to description parsing.
 134
 135 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 136
 137         * configure: Regenerate.
 138
 139 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 140
 141         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
 142         (main): Recognize the new CPU string.
 143         * s390-opc.c: Add new instruction formats and masks.
 144         * s390-opc.txt: Add new z196 instructions.
 145
 146 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 147
 148         * s390-dis.c (print_insn_s390): Pick instruction with most
 149         specific mask.
 150         * s390-opc.c: Add unused bits to the insn mask.
 151         * s390-opc.txt: Reorder some instructions to prefer more recent
 152         versions.
 153
 154 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
 155
 156         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
 157         correction to unaligned PCs while printing comment.
 158
 159 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 160
 161         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
 162         (thumb32_opcodes): Likewise.
 163         (banked_regname): New function.
 164         (print_insn_arm): Add Virtualization Extensions support.
 165         (print_insn_thumb32): Likewise.
 166
 167 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 168
 169         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
 170         ARM state.
 171
 172 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 173
 174         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
 175         (thumb32_opcodes): Likewise.
 176
 177 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 178
 179         * arm-dis.c (arm_opcodes): Add support for pldw.
 180         (thumb32_opcodes): Likewise.
 181
 182 2010-09-22  Robin Getz  <robin.getz@analog.com>
 183
 184         * bfin-dis.c (fmtconst): Cast address to 32bits.
 185
 186 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 187
 188         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
 189
 190 2010-09-22  Robin Getz  <robin.getz@analog.com>
 191
 192         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
 193         Reject P6/P7 to TESTSET.
 194         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
 195         SP onto the stack.
 196         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
 197         P/D fields match all the time.
 198         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
 199         are 0 for accumulator compares.
 200         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
 201         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
 202         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
 203         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 204         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 205         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
 206         insns.
 207         (decode_dagMODim_0): Verify br field for IREG ops.
 208         (decode_LDST_0): Reject preg load into same preg.
 209         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
 210         (print_insn_bfin): Likewise.
 211
 212 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 213
 214         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
 215
 216 2010-09-22  Robin Getz  <robin.getz@analog.com>
 217
 218         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
 219
 220 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 221
 222         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
 223
 224 2010-09-22  Robin Getz  <robin.getz@analog.com>
 225
 226         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 227         register values greater than 8.
 228         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 229         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 230         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 231         (decode_CC2dreg_0): Check valid CC register number.
 232
 233 2010-09-22  Robin Getz  <robin.getz@analog.com>
 234
 235         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 236
 237 2010-09-22  Robin Getz  <robin.getz@analog.com>
 238
 239         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 240         (reg_names): Likewise.
 241         (decode_statbits): Likewise; while reformatting to make manageable.
 242
 243 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 244
 245         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 246         (decode_pseudoOChar_0): New function.
 247         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 248
 249 2010-09-22  Robin Getz  <robin.getz@analog.com>
 250
 251         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 252         LSHIFT instead of SHIFT.
 253
 254 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 255
 256         * bfin-dis.c (constant_formats): Constify the whole structure.
 257         (fmtconst): Add const to return value.
 258         (reg_names): Mark const.
 259         (decode_multfunc): Mark s0/s1 as const.
 260         (decode_macfunc): Mark a/sop as const.
 261
 262 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 263
 264         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 265
 266 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 267
 268         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 269         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 270
 271 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 272
 273         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 274         dlx_insn_type array.
 275
 276 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         PR binutils/11960
 279         * i386-dis.c (sIv): New.
 280         (dis386): Replace Iq with sIv on "pushT".
 281         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 282         (x86_64_table): Replace {T|}/{P|} with P.
 283         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 284         (OP_sI): Update v_mode.  Remove w_mode.
 285
 286 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 287
 288         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 289         on E500 and E500MC.
 290
 291 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 292
 293         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 294         prefetchw.
 295
 296 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 297
 298         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 299         to processor flags for PENTIUMPRO processors and later.
 300         * i386-opc.h (enum): Add CpuNop.
 301         (i386_cpu_flags): Add cpunop bit.
 302         * i386-opc.tbl: Change nop cpu_flags.
 303         * i386-init.h: Regenerated.
 304         * i386-tbl.h: Likewise.
 305
 306 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 307
 308         * i386-opc.h (enum): Fix typos in comments.
 309
 310 2010-08-06  Alan Modra  <amodra@gmail.com>
 311
 312         * disassemble.c: Formatting.
 313         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 314
 315 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 316
 317         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 318         * i386-tbl.h: Regenerated.
 319
 320 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 321
 322         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 323
 324         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 325         * i386-tbl.h: Regenerated.
 326
 327 2010-07-29  DJ Delorie  <dj@redhat.com>
 328
 329         * rx-decode.opc (SRR): New.
 330         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 331         r0,r0) and NOP3 (max r0,r0) special cases.
 332         * rx-decode.c: Regenerate.
 333
 334 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 335
 336         * i386-dis.c: Add 0F to VEX opcode enums.
 337
 338 2010-07-27  DJ Delorie  <dj@redhat.com>
 339
 340         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 341         (rx_decode_opcode): Likewise.
 342         * rx-decode.c: Regenerate.
 343
 344 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 345             Ina Pandit  <ina.pandit@kpitcummins.com>
 346
 347         * v850-dis.c (v850_sreg_names): Updated structure for system
 348         registers.
 349         (float_cc_names): new structure for condition codes.
 350         (print_value): Update the function that prints value.
 351         (get_operand_value): New function to get the operand value.
 352         (disassemble): Updated to handle the disassembly of instructions.
 353         (print_insn_v850): Updated function to print instruction for different
 354         families.
 355         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 356         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 357         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 358         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 359         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 360         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 361         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 362         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 363         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 364         (v850_operands): Update with the relocation name. Also update
 365         the instructions with specific set of processors.
 366
 367 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 368
 369         * arm-dis.c (print_insn_arm): Add cases for printing more
 370         symbolic operands.
 371         (print_insn_thumb32): Likewise.
 372
 373 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 374
 375         * mips-dis.c (print_insn_mips): Correct branch instruction type
 376         determination.
 377
 378 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 379
 380         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 381         type and delay slot determination.
 382         (print_insn_mips16): Extend branch instruction type and delay
 383         slot determination to cover all instructions.
 384         * mips16-opc.c (BR): Remove macro.
 385         (UBR, CBR): New macros.
 386         (mips16_opcodes): Update branch annotation for "b", "beqz",
 387         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 388         and "jrc".
 389
 390 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 391
 392         AVX Programming Reference (June, 2010)
 393         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 394         * i386-opc.tbl: Likewise.
 395         * i386-tbl.h: Regenerated.
 396
 397 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 398
 399         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 400
 401 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 402
 403         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 404         ppc_cpu_t before inverting.
 405         (ppc_parse_cpu): Likewise.
 406         (print_insn_powerpc): Likewise.
 407
 408 2010-07-03  Alan Modra  <amodra@gmail.com>
 409
 410         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 411         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 412         (PPC64, MFDEC2): Update.
 413         (NON32, NO371): Define.
 414         (powerpc_opcode): Update to not use old opcode flags, and avoid
 415         -m601 duplicates.
 416
 417 2010-07-03  DJ Delorie  <dj@delorie.com>
 418
 419         * m32c-ibld.c: Regenerate.
 420
 421 2010-07-03  Alan Modra  <amodra@gmail.com>
 422
 423         * ppc-opc.c (PWR2COM): Define.
 424         (PPCPWR2): Add PPC_OPCODE_COMMON.
 425         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 426         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 427         "rac" from -mcom.
 428
 429 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 430
 431         AVX Programming Reference (June, 2010)
 432         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 433         (PREFIX_0FAE_REG_1): Likewise.
 434         (PREFIX_0FAE_REG_2): Likewise.
 435         (PREFIX_0FAE_REG_3): Likewise.
 436         (PREFIX_VEX_3813): Likewise.
 437         (PREFIX_VEX_3A1D): Likewise.
 438         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 439         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 440         PREFIX_VEX_3A1D.
 441         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 442         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 443         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 444
 445         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 446         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 447         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 448
 449         * i386-opc.h (CpuXsaveopt): New.
 450         (CpuFSGSBase): Likewise.
 451         (CpuRdRnd): Likewise.
 452         (CpuF16C): Likewise.
 453         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 454         cpuf16c.
 455
 456         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 457         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 458         * i386-init.h: Regenerated.
 459         * i386-tbl.h: Likewise.
 460
 461 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 462
 463         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 464         and mtocrf on EFS.
 465
 466 2010-06-29  Alan Modra  <amodra@gmail.com>
 467
 468         * maxq-dis.c: Delete file.
 469         * Makefile.am: Remove references to maxq.
 470         * configure.in: Likewise.
 471         * disassemble.c: Likewise.
 472         * Makefile.in: Regenerate.
 473         * configure: Regenerate.
 474         * po/POTFILES.in: Regenerate.
 475
 476 2010-06-29  Alan Modra  <amodra@gmail.com>
 477
 478         * mep-dis.c: Regenerate.
 479
 480 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 481
 482         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 483
 484 2010-06-27  Alan Modra  <amodra@gmail.com>
 485
 486         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 487         (decodeInstr): Likewise.
 488         * dlx-dis.c (print_insn_dlx): Likewise.
 489         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 490         * maxq-dis.c (check_move, print_insn): Likewise.
 491         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 492         * msp430-dis.c (msp430_branchinstr): Likewise.
 493         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 494         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 495         * sparc-dis.c (print_insn_sparc): Likewise.
 496         * fr30-asm.c: Regenerate.
 497         * frv-asm.c: Regenerate.
 498         * ip2k-asm.c: Regenerate.
 499         * iq2000-asm.c: Regenerate.
 500         * lm32-asm.c: Regenerate.
 501         * m32c-asm.c: Regenerate.
 502         * m32r-asm.c: Regenerate.
 503         * mep-asm.c: Regenerate.
 504         * mt-asm.c: Regenerate.
 505         * openrisc-asm.c: Regenerate.
 506         * xc16x-asm.c: Regenerate.
 507         * xstormy16-asm.c: Regenerate.
 508
 509 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 510
 511         PR gas/11673
 512         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 513
 514 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 515
 516         PR binutils/11676
 517         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 518
 519 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 520
 521         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 522         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 523         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 524         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 525         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 526         Treat lwsync as msync on e500.
 527
 528 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 529
 530         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 531
 532 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 533
 534         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 535         constants is the same on 32-bit and 64-bit hosts.
 536
 537 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 538
 539         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 540         .short directives so that they can be reassembled.
 541
 542 2010-05-26  Catherine Moore <clm@codesourcery.com>
 543             David Ung  <davidu@mips.com>
 544
 545         * mips-opc.c: Change membership to I1 for instructions ssnop and
 546         ehb.
 547
 548 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         * i386-dis.c (sib): New.
 551         (get_sib): Likewise.
 552         (print_insn): Call get_sib.
 553         OP_E_memory): Use sib.
 554
 555 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 556
 557         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 558         * mips-opc.c (I16): Remove.
 559         (mips_builtin_op): Reclassify jalx.
 560
 561 2010-05-19  Alan Modra  <amodra@gmail.com>
 562
 563         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 564         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 565
 566 2010-05-13  Alan Modra  <amodra@gmail.com>
 567
 568         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 569
 570 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 571
 572         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 573         format.
 574         (print_insn_thumb16): Add support for new %W format.
 575
 576 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 577
 578         * Makefile.in: Regenerate with automake 1.11.1.
 579         * aclocal.m4: Ditto.
 580
 581 2010-05-05  Nick Clifton  <nickc@redhat.com>
 582
 583         * po/es.po: Updated Spanish translation.
 584
 585 2010-04-22  Nick Clifton  <nickc@redhat.com>
 586
 587         * po/opcodes.pot: Updated by the Translation project.
 588         * po/vi.po: Updated Vietnamese translation.
 589
 590 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 591
 592         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 593         bits in opcode.
 594
 595 2010-04-09  Nick Clifton  <nickc@redhat.com>
 596
 597         * i386-dis.c (print_insn): Remove unused variable op.
 598         (OP_sI): Remove unused variable mask.
 599
 600 2010-04-07  Alan Modra  <amodra@gmail.com>
 601
 602         * configure: Regenerate.
 603
 604 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 605
 606         * ppc-opc.c (RBOPT): New define.
 607         ("dccci"): Enable for PPCA2.  Make operands optional.
 608         ("iccci"): Likewise.  Do not deprecate for PPC476.
 609
 610 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 611
 612         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 613
 614 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 615
 616         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 617         * Makefile.in: Regenerate.
 618         * configure.in (bfd_tic6x_arch): New.
 619         * configure: Regenerate.
 620         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 621         (disassembler): Handle TI C6X.
 622         * tic6x-dis.c: New.
 623
 624 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 625
 626         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 627
 628 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 629
 630         * dis-buf.c (buffer_read_memory): Give error for reading just
 631         before the start of memory.
 632
 633 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 634             Quentin Neill <quentin.neill@amd.com>
 635
 636         * i386-dis.c (OP_LWP_I): Removed.
 637         (reg_table): Do not use OP_LWP_I, use Iq.
 638         (OP_LWPCB_E): Remove use of names16.
 639         (OP_LWP_E): Same.
 640         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 641         should not set the Vex.length bit.
 642         * i386-tbl.h: Regenerated.
 643
 644 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 645
 646         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 647
 648 2010-02-24  Nick Clifton  <nickc@redhat.com>
 649
 650         PR binutils/6773
 651         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 652         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 653         (thumb32_opcodes): Likewise.
 654
 655 2010-02-15  Nick Clifton  <nickc@redhat.com>
 656
 657         * po/vi.po: Updated Vietnamese translation.
 658
 659 2010-02-12  Doug Evans  <dje@sebabeach.org>
 660
 661         * lm32-opinst.c: Regenerate.
 662
 663 2010-02-11  Doug Evans  <dje@sebabeach.org>
 664
 665         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 666         (print_address): Delete CGEN_PRINT_ADDRESS.
 667         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 668         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 669         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 670         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 671
 672         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 673         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 674         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 675         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 676         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 677         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 678         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 679         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 680         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 681         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 682         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 683         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 684
 685 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 686
 687         * i386-dis.c: Update copyright.
 688         * i386-gen.c: Likewise.
 689         * i386-opc.h: Likewise.
 690         * i386-opc.tbl: Likewise.
 691
 692 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 693             Sebastian Pop  <sebastian.pop@amd.com>
 694
 695         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 696         function to handle 5th imm8 operand.
 697         (PREFIX_VEX_3A48): Added.
 698         (PREFIX_VEX_3A49): Added.
 699         (VEX_W_3A48_P_2): Added.
 700         (VEX_W_3A49_P_2): Added.
 701         (prefix table): Added entries for PREFIX_VEX_3A48
 702         and PREFIX_VEX_3A49.
 703         (vex table): Added entries for VEX_W_3A48_P_2 and
 704         and VEX_W_3A49_P_2.
 705         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 706         for Vec_Imm4 operands.
 707         * i386-opc.h (enum): Added Vec_Imm4.
 708         (i386_operand_type): Added vec_imm4.
 709         * i386-opc.tbl: Add entries for vpermilp[ds].
 710         * i386-init.h: Regenerated.
 711         * i386-tbl.h: Regenerated.
 712
 713 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 714
 715         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 716         and "pwr7".  Move "a2" into alphabetical order.
 717
 718 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 719
 720         * ppc-dis.c (ppc_opts): Add titan entry.
 721         * ppc-opc.c (TITAN, MULHW): Define.
 722         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 723
 724 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 725
 726         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 727         to CPU_BDVER1_FLAGS
 728         * i386-init.h: Regenerated.
 729
 730 2010-02-03  Anthony Green  <green@moxielogic.com>
 731
 732         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 733         0x0f, and make 0x00 an illegal instruction.
 734
 735 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 736
 737         * opcodes/arm-dis.c (struct arm_private_data): New.
 738         (print_insn_coprocessor, print_insn_arm): Update to use struct
 739         arm_private_data.
 740         (is_mapping_symbol, get_map_sym_type): New functions.
 741         (get_sym_code_type): Check the symbol's section.  Do not check
 742         mapping symbols.
 743         (print_insn): Default to disassembling ARM mode code.  Check
 744         for mapping symbols separately from other symbols.  Use
 745         struct arm_private_data.
 746
 747 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         * i386-dis.c (EXVexWdqScalar): New.
 750         (vex_scalar_w_dq_mode): Likewise.
 751         (prefix_table): Update entries for PREFIX_VEX_3899,
 752         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 753         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 754         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 755         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 756         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 757         (OP_EX): Likewise.
 758
 759 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 760
 761         * i386-dis.c (XMScalar): New.
 762         (EXdScalar): Likewise.
 763         (EXqScalar): Likewise.
 764         (EXqScalarS): Likewise.
 765         (VexScalar): Likewise.
 766         (EXdVexScalarS): Likewise.
 767         (EXqVexScalarS): Likewise.
 768         (XMVexScalar): Likewise.
 769         (scalar_mode): Likewise.
 770         (d_scalar_mode): Likewise.
 771         (d_scalar_swap_mode): Likewise.
 772         (q_scalar_mode): Likewise.
 773         (q_scalar_swap_mode): Likewise.
 774         (vex_scalar_mode): Likewise.
 775         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 776         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 777         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 778         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 779         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 780         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 781         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 782         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 783         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 784         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 785         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 786         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 787         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 788         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 789         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 790         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 791         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 792         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 793         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 794         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 795         q_scalar_mode, q_scalar_swap_mode.
 796         (OP_XMM): Handle scalar_mode.
 797         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 798         and q_scalar_swap_mode.
 799         (OP_VEX): Handle vex_scalar_mode.
 800
 801 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 802
 803         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 804
 805 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 806
 807         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 808
 809 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 810
 811         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 812
 813 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 814
 815         * i386-dis.c (Bad_Opcode): New.
 816         (bad_opcode): Likewise.
 817         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 818         (dis386_twobyte): Likewise.
 819         (reg_table): Likewise.
 820         (prefix_table): Likewise.
 821         (x86_64_table): Likewise.
 822         (vex_len_table): Likewise.
 823         (vex_w_table): Likewise.
 824         (mod_table): Likewise.
 825         (rm_table): Likewise.
 826         (float_reg): Likewise.
 827         (reg_table): Remove trailing "(bad)" entries.
 828         (prefix_table): Likewise.
 829         (x86_64_table): Likewise.
 830         (vex_len_table): Likewise.
 831         (vex_w_table): Likewise.
 832         (mod_table): Likewise.
 833         (rm_table): Likewise.
 834         (get_valid_dis386): Handle bytemode 0.
 835
 836 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 837
 838         * i386-opc.h (VEXScalar): New.
 839
 840         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 841         instructions.
 842         * i386-tbl.h: Regenerated.
 843
 844 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 845
 846         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 847
 848         * i386-opc.tbl: Add xsave64 and xrstor64.
 849         * i386-tbl.h: Regenerated.
 850
 851 2010-01-20  Nick Clifton  <nickc@redhat.com>
 852
 853         PR 11170
 854         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 855         based post-indexed addressing.
 856
 857 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 858
 859         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 860         * i386-tbl.h: Regenerated.
 861
 862 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 863
 864         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 865         comments.
 866
 867 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 868
 869         * i386-dis.c (names_mm): New.
 870         (intel_names_mm): Likewise.
 871         (att_names_mm): Likewise.
 872         (names_xmm): Likewise.
 873         (intel_names_xmm): Likewise.
 874         (att_names_xmm): Likewise.
 875         (names_ymm): Likewise.
 876         (intel_names_ymm): Likewise.
 877         (att_names_ymm): Likewise.
 878         (print_insn): Set names_mm, names_xmm and names_ymm.
 879         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 880         (OP_XMM): Likewise.
 881         (OP_EM): Likewise.
 882         (OP_EMC): Likewise.
 883         (OP_MXC): Likewise.
 884         (OP_EX): Likewise.
 885         (XMM_Fixup): Likewise.
 886         (OP_VEX): Likewise.
 887         (OP_EX_VexReg): Likewise.
 888         (OP_Vex_2src): Likewise.
 889         (OP_Vex_2src_1): Likewise.
 890         (OP_Vex_2src_2): Likewise.
 891         (OP_REG_VexI4): Likewise.
 892
 893 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 894
 895         * i386-dis.c (print_insn): Update comments.
 896
 897 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 898
 899         * i386-dis.c (rex_original): Removed.
 900         (ckprefix): Remove rex_original.
 901         (print_insn): Update comments.
 902
 903 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 904
 905         * Makefile.in: Regenerate.
 906         * configure: Regenerate.
 907
 908 2010-01-07  Doug Evans  <dje@sebabeach.org>
 909
 910         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 911         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 912         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 913         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 914         * xstormy16-ibld.c: Regenerate.
 915
 916 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 917
 918         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 919         * i386-init.h: Regenerated.
 920
 921 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 922
 923         * arm-dis.c (print_insn): Fixed search for next symbol and data
 924         dumping condition, and the initial mapping symbol state.
 925
 926 2010-01-05  Doug Evans  <dje@sebabeach.org>
 927
 928         * cgen-ibld.in: #include "cgen/basic-modes.h".
 929         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 930         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 931         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 932         * xstormy16-ibld.c: Regenerate.
 933
 934 2010-01-04  Nick Clifton  <nickc@redhat.com>
 935
 936         PR 11123
 937         * arm-dis.c (print_insn_coprocessor): Initialise value.
 938
 939 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 940
 941         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 942
 943 2010-01-02  Doug Evans  <dje@sebabeach.org>
 944
 945         * cgen-asm.in: Update copyright year.
 946         * cgen-dis.in: Update copyright year.
 947         * cgen-ibld.in: Update copyright year.
 948         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 949         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 950         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 951         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 952         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 953         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 954         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 955         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 956         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 957         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 958         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 959         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 960         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 961         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 962         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 963         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 964         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 965         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 966         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 967         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 968         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 969
 970 For older changes see ChangeLog-2009
 971 \f
 972 Local Variables:
 973 mode: change-log
 974 left-margin: 8
 975 fill-column: 74
 976 version-control: never
 977 End: