1 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
3 Fix extraction of signed constants in nios2 disassembler (again).
5 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
6 extractions of signed fields.
8 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
10 * s390-opc.txt: Relocate vector load/store instructions with
11 additional alignment parameter and change architecture level
12 constraint from z14 to z13.
14 2020-05-21 Alan Modra <amodra@gmail.com>
16 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
17 * sparc-dis.c: Likewise.
18 * tic4x-dis.c: Likewise.
19 * xtensa-dis.c: Likewise.
20 * bpf-desc.c: Regenerate.
21 * epiphany-desc.c: Regenerate.
22 * fr30-desc.c: Regenerate.
23 * frv-desc.c: Regenerate.
24 * ip2k-desc.c: Regenerate.
25 * iq2000-desc.c: Regenerate.
26 * lm32-desc.c: Regenerate.
27 * m32c-desc.c: Regenerate.
28 * m32r-desc.c: Regenerate.
29 * mep-asm.c: Regenerate.
30 * mep-desc.c: Regenerate.
31 * mt-desc.c: Regenerate.
32 * or1k-desc.c: Regenerate.
33 * xc16x-desc.c: Regenerate.
34 * xstormy16-desc.c: Regenerate.
36 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
38 * riscv-opc.c (riscv_ext_version_table): The table used to store
39 all information about the supported spec and the corresponding ISA
40 versions. Currently, only Zicsr is supported to verify the
41 correctness of Z sub extension settings. Others will be supported
42 in the future patches.
43 (struct isa_spec_t, isa_specs): List for all supported ISA spec
44 classes and the corresponding strings.
45 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
46 spec class by giving a ISA spec string.
47 * riscv-opc.c (struct priv_spec_t): New structure.
48 (struct priv_spec_t priv_specs): List for all supported privilege spec
49 classes and the corresponding strings.
50 (riscv_get_priv_spec_class): New function. Get the corresponding
51 privilege spec class by giving a spec string.
52 (riscv_get_priv_spec_name): New function. Get the corresponding
53 privilege spec string by giving a CSR version class.
54 * riscv-dis.c: Updated since DECLARE_CSR is changed.
55 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
56 according to the chosen version. Build a hash table riscv_csr_hash to
57 store the valid CSR for the chosen pirv verison. Dump the direct
58 CSR address rather than it's name if it is invalid.
59 (parse_riscv_dis_option_without_args): New function. Parse the options
61 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
62 parse the options without arguments first, and then handle the options
63 with arguments. Add the new option -Mpriv-spec, which has argument.
64 * riscv-dis.c (print_riscv_disassembler_options): Add description
65 about the new OBJDUMP option.
67 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
69 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
70 WC values on POWER10 sync, dcbf and wait instructions.
71 (insert_pl, extract_pl): New functions.
72 (L2OPT, LS, WC): Use insert_ls and extract_ls.
73 (LS3): New , 3-bit L for sync.
74 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
75 (SC2, PL): New, 2-bit SC and PL for sync and wait.
76 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
77 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
78 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
79 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
80 <wait>: Enable PL operand on POWER10.
81 <dcbf>: Enable L3OPT operand on POWER10.
82 <sync>: Enable SC2 operand on POWER10.
84 2020-05-19 Stafford Horne <shorne@gmail.com>
87 * or1k-asm.c: Regenerate.
88 * or1k-desc.c: Regenerate.
89 * or1k-desc.h: Regenerate.
90 * or1k-dis.c: Regenerate.
91 * or1k-ibld.c: Regenerate.
92 * or1k-opc.c: Regenerate.
93 * or1k-opc.h: Regenerate.
94 * or1k-opinst.c: Regenerate.
96 2020-05-11 Alan Modra <amodra@gmail.com>
98 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
101 2020-05-11 Alan Modra <amodra@gmail.com>
103 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
104 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
106 2020-05-11 Alan Modra <amodra@gmail.com>
108 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
110 2020-05-11 Alan Modra <amodra@gmail.com>
112 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
113 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
115 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
117 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
120 2020-05-11 Alan Modra <amodra@gmail.com>
122 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
123 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
124 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
125 (prefix_opcodes): Add xxeval.
127 2020-05-11 Alan Modra <amodra@gmail.com>
129 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
130 xxgenpcvwm, xxgenpcvdm.
132 2020-05-11 Alan Modra <amodra@gmail.com>
134 * ppc-opc.c (MP, VXVAM_MASK): Define.
135 (VXVAPS_MASK): Use VXVA_MASK.
136 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
137 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
138 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
139 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
141 2020-05-11 Alan Modra <amodra@gmail.com>
142 Peter Bergner <bergner@linux.ibm.com>
144 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
146 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
147 YMSK2, XA6a, XA6ap, XB6a entries.
148 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
149 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
151 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
152 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
153 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
154 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
155 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
156 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
157 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
158 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
159 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
160 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
161 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
162 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
163 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
164 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
166 2020-05-11 Alan Modra <amodra@gmail.com>
168 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
169 (insert_xts, extract_xts): New functions.
170 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
171 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
172 (VXRC_MASK, VXSH_MASK): Define.
173 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
174 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
175 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
176 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
177 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
178 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
179 xxblendvh, xxblendvw, xxblendvd, xxpermx.
181 2020-05-11 Alan Modra <amodra@gmail.com>
183 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
184 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
185 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
186 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
187 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
189 2020-05-11 Alan Modra <amodra@gmail.com>
191 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
192 (XTP, DQXP, DQXP_MASK): Define.
193 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
194 (prefix_opcodes): Add plxvp and pstxvp.
196 2020-05-11 Alan Modra <amodra@gmail.com>
198 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
199 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
200 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
202 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
204 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
206 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
208 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
210 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
212 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
214 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
216 2020-05-11 Alan Modra <amodra@gmail.com>
218 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
220 2020-05-11 Alan Modra <amodra@gmail.com>
222 * ppc-dis.c (ppc_opts): Add "power10" entry.
223 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
224 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
226 2020-05-11 Nick Clifton <nickc@redhat.com>
228 * po/fr.po: Updated French translation.
230 2020-04-30 Alex Coplan <alex.coplan@arm.com>
232 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
233 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
234 (operand_general_constraint_met_p): validate
235 AARCH64_OPND_UNDEFINED.
236 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
238 * aarch64-asm-2.c: Regenerated.
239 * aarch64-dis-2.c: Regenerated.
240 * aarch64-opc-2.c: Regenerated.
242 2020-04-29 Nick Clifton <nickc@redhat.com>
245 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
248 2020-04-29 Nick Clifton <nickc@redhat.com>
250 * po/sv.po: Updated Swedish translation.
252 2020-04-29 Nick Clifton <nickc@redhat.com>
255 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
256 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
257 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
260 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
263 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
264 cmpi only on m68020up and cpu32.
266 2020-04-20 Sudakshina Das <sudi.das@arm.com>
268 * aarch64-asm.c (aarch64_ins_none): New.
269 * aarch64-asm.h (ins_none): New declaration.
270 * aarch64-dis.c (aarch64_ext_none): New.
271 * aarch64-dis.h (ext_none): New declaration.
272 * aarch64-opc.c (aarch64_print_operand): Update case for
273 AARCH64_OPND_BARRIER_PSB.
274 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
275 (AARCH64_OPERANDS): Update inserter/extracter for
276 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
277 * aarch64-asm-2.c: Regenerated.
278 * aarch64-dis-2.c: Regenerated.
279 * aarch64-opc-2.c: Regenerated.
281 2020-04-20 Sudakshina Das <sudi.das@arm.com>
283 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
284 (aarch64_feature_ras, RAS): Likewise.
285 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
286 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
287 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
288 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
289 * aarch64-asm-2.c: Regenerated.
290 * aarch64-dis-2.c: Regenerated.
291 * aarch64-opc-2.c: Regenerated.
293 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
295 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
296 (print_insn_neon): Support disassembly of conditional
299 2020-02-16 David Faust <david.faust@oracle.com>
301 * bpf-desc.c: Regenerate.
302 * bpf-desc.h: Likewise.
303 * bpf-opc.c: Regenerate.
304 * bpf-opc.h: Likewise.
306 2020-04-07 Lili Cui <lili.cui@intel.com>
308 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
309 (prefix_table): New instructions (see prefixes above).
311 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
312 CPU_ANY_TSXLDTRK_FLAGS.
313 (cpu_flags): Add CpuTSXLDTRK.
314 * i386-opc.h (enum): Add CpuTSXLDTRK.
315 (i386_cpu_flags): Add cputsxldtrk.
316 * i386-opc.tbl: Add XSUSPLDTRK insns.
317 * i386-init.h: Regenerate.
318 * i386-tbl.h: Likewise.
320 2020-04-02 Lili Cui <lili.cui@intel.com>
322 * i386-dis.c (prefix_table): New instructions serialize.
323 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
324 CPU_ANY_SERIALIZE_FLAGS.
325 (cpu_flags): Add CpuSERIALIZE.
326 * i386-opc.h (enum): Add CpuSERIALIZE.
327 (i386_cpu_flags): Add cpuserialize.
328 * i386-opc.tbl: Add SERIALIZE insns.
329 * i386-init.h: Regenerate.
330 * i386-tbl.h: Likewise.
332 2020-03-26 Alan Modra <amodra@gmail.com>
334 * disassemble.h (opcodes_assert): Declare.
335 (OPCODES_ASSERT): Define.
336 * disassemble.c: Don't include assert.h. Include opintl.h.
337 (opcodes_assert): New function.
338 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
339 (bfd_h8_disassemble): Reduce size of data array. Correctly
340 calculate maxlen. Omit insn decoding when insn length exceeds
341 maxlen. Exit from nibble loop when looking for E, before
342 accessing next data byte. Move processing of E outside loop.
343 Replace tests of maxlen in loop with assertions.
345 2020-03-26 Alan Modra <amodra@gmail.com>
347 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
349 2020-03-25 Alan Modra <amodra@gmail.com>
351 * z80-dis.c (suffix): Init mybuf.
353 2020-03-22 Alan Modra <amodra@gmail.com>
355 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
356 successflly read from section.
358 2020-03-22 Alan Modra <amodra@gmail.com>
360 * arc-dis.c (find_format): Use ISO C string concatenation rather
361 than line continuation within a string. Don't access needs_limm
362 before testing opcode != NULL.
364 2020-03-22 Alan Modra <amodra@gmail.com>
366 * ns32k-dis.c (print_insn_arg): Update comment.
367 (print_insn_ns32k): Reduce size of index_offset array, and
368 initialize, passing -1 to print_insn_arg for args that are not
369 an index. Don't exit arg loop early. Abort on bad arg number.
371 2020-03-22 Alan Modra <amodra@gmail.com>
373 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
374 * s12z-opc.c: Formatting.
375 (operands_f): Return an int.
376 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
377 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
378 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
379 (exg_sex_discrim): Likewise.
380 (create_immediate_operand, create_bitfield_operand),
381 (create_register_operand_with_size, create_register_all_operand),
382 (create_register_all16_operand, create_simple_memory_operand),
383 (create_memory_operand, create_memory_auto_operand): Don't
384 segfault on malloc failure.
385 (z_ext24_decode): Return an int status, negative on fail, zero
387 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
388 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
389 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
390 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
391 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
392 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
393 (loop_primitive_decode, shift_decode, psh_pul_decode),
394 (bit_field_decode): Similarly.
395 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
396 to return value, update callers.
397 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
398 Don't segfault on NULL operand.
399 (decode_operation): Return OP_INVALID on first fail.
400 (decode_s12z): Check all reads, returning -1 on fail.
402 2020-03-20 Alan Modra <amodra@gmail.com>
404 * metag-dis.c (print_insn_metag): Don't ignore status from
407 2020-03-20 Alan Modra <amodra@gmail.com>
409 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
410 Initialize parts of buffer not written when handling a possible
411 2-byte insn at end of section. Don't attempt decoding of such
412 an insn by the 4-byte machinery.
414 2020-03-20 Alan Modra <amodra@gmail.com>
416 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
417 partially filled buffer. Prevent lookup of 4-byte insns when
418 only VLE 2-byte insns are possible due to section size. Print
419 ".word" rather than ".long" for 2-byte leftovers.
421 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
424 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
426 2020-03-13 Jan Beulich <jbeulich@suse.com>
428 * i386-dis.c (X86_64_0D): Rename to ...
429 (X86_64_0E): ... this.
431 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
433 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
434 * Makefile.in: Regenerated.
436 2020-03-09 Jan Beulich <jbeulich@suse.com>
438 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
440 * i386-tbl.h: Re-generate.
442 2020-03-09 Jan Beulich <jbeulich@suse.com>
444 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
445 vprot*, vpsha*, and vpshl*.
446 * i386-tbl.h: Re-generate.
448 2020-03-09 Jan Beulich <jbeulich@suse.com>
450 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
451 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
452 * i386-tbl.h: Re-generate.
454 2020-03-09 Jan Beulich <jbeulich@suse.com>
456 * i386-gen.c (set_bitfield): Ignore zero-length field names.
457 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
458 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
459 * i386-tbl.h: Re-generate.
461 2020-03-09 Jan Beulich <jbeulich@suse.com>
463 * i386-gen.c (struct template_arg, struct template_instance,
464 struct template_param, struct template, templates,
465 parse_template, expand_templates): New.
466 (process_i386_opcodes): Various local variables moved to
467 expand_templates. Call parse_template and expand_templates.
468 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
469 * i386-tbl.h: Re-generate.
471 2020-03-06 Jan Beulich <jbeulich@suse.com>
473 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
474 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
475 register and memory source templates. Replace VexW= by VexW*
477 * i386-tbl.h: Re-generate.
479 2020-03-06 Jan Beulich <jbeulich@suse.com>
481 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
482 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
483 * i386-tbl.h: Re-generate.
485 2020-03-06 Jan Beulich <jbeulich@suse.com>
487 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
488 * i386-tbl.h: Re-generate.
490 2020-03-06 Jan Beulich <jbeulich@suse.com>
492 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
493 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
494 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
495 VexW0 on SSE2AVX variants.
496 (vmovq): Drop NoRex64 from XMM/XMM variants.
497 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
498 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
499 applicable use VexW0.
500 * i386-tbl.h: Re-generate.
502 2020-03-06 Jan Beulich <jbeulich@suse.com>
504 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
505 * i386-opc.h (Rex64): Delete.
506 (struct i386_opcode_modifier): Remove rex64 field.
507 * i386-opc.tbl (crc32): Drop Rex64.
508 Replace Rex64 with Size64 everywhere else.
509 * i386-tbl.h: Re-generate.
511 2020-03-06 Jan Beulich <jbeulich@suse.com>
513 * i386-dis.c (OP_E_memory): Exclude recording of used address
514 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
515 addressed memory operands for MPX insns.
517 2020-03-06 Jan Beulich <jbeulich@suse.com>
519 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
520 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
521 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
522 (ptwrite): Split into non-64-bit and 64-bit forms.
523 * i386-tbl.h: Re-generate.
525 2020-03-06 Jan Beulich <jbeulich@suse.com>
527 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
529 * i386-tbl.h: Re-generate.
531 2020-03-04 Jan Beulich <jbeulich@suse.com>
533 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
534 (prefix_table): Move vmmcall here. Add vmgexit.
535 (rm_table): Replace vmmcall entry by prefix_table[] escape.
536 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
537 (cpu_flags): Add CpuSEV_ES entry.
538 * i386-opc.h (CpuSEV_ES): New.
539 (union i386_cpu_flags): Add cpusev_es field.
540 * i386-opc.tbl (vmgexit): New.
541 * i386-init.h, i386-tbl.h: Re-generate.
543 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
545 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
547 * i386-opc.h (IGNORESIZE): New.
548 (DEFAULTSIZE): Likewise.
549 (IgnoreSize): Removed.
550 (DefaultSize): Likewise.
552 (i386_opcode_modifier): Replace ignoresize/defaultsize with
554 * i386-opc.tbl (IgnoreSize): New.
555 (DefaultSize): Likewise.
556 * i386-tbl.h: Regenerated.
558 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
561 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
564 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
567 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
568 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
569 * i386-tbl.h: Regenerated.
571 2020-02-26 Alan Modra <amodra@gmail.com>
573 * aarch64-asm.c: Indent labels correctly.
574 * aarch64-dis.c: Likewise.
575 * aarch64-gen.c: Likewise.
576 * aarch64-opc.c: Likewise.
577 * alpha-dis.c: Likewise.
578 * i386-dis.c: Likewise.
579 * nds32-asm.c: Likewise.
580 * nfp-dis.c: Likewise.
581 * visium-dis.c: Likewise.
583 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
585 * arc-regs.h (int_vector_base): Make it available for all ARC
588 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
590 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
593 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
595 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
596 c.mv/c.li if rs1 is zero.
598 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
600 * i386-gen.c (cpu_flag_init): Replace CpuABM with
601 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
603 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
604 * i386-opc.h (CpuABM): Removed.
606 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
607 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
608 popcnt. Remove CpuABM from lzcnt.
609 * i386-init.h: Regenerated.
610 * i386-tbl.h: Likewise.
612 2020-02-17 Jan Beulich <jbeulich@suse.com>
614 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
615 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
616 VexW1 instead of open-coding them.
617 * i386-tbl.h: Re-generate.
619 2020-02-17 Jan Beulich <jbeulich@suse.com>
621 * i386-opc.tbl (AddrPrefixOpReg): Define.
622 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
623 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
624 templates. Drop NoRex64.
625 * i386-tbl.h: Re-generate.
627 2020-02-17 Jan Beulich <jbeulich@suse.com>
630 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
631 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
632 into Intel syntax instance (with Unpsecified) and AT&T one
634 (vcvtneps2bf16): Likewise, along with folding the two so far
636 * i386-tbl.h: Re-generate.
638 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
640 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
643 2020-02-17 Alan Modra <amodra@gmail.com>
645 * i386-gen.c (cpu_flag_init): Correct last change.
647 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
649 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
652 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
654 * i386-opc.tbl (movsx): Remove Intel syntax comments.
657 2020-02-14 Jan Beulich <jbeulich@suse.com>
660 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
661 destination for Cpu64-only variant.
662 (movzx): Fold patterns.
663 * i386-tbl.h: Re-generate.
665 2020-02-13 Jan Beulich <jbeulich@suse.com>
667 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
668 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
669 CPU_ANY_SSE4_FLAGS entry.
670 * i386-init.h: Re-generate.
672 2020-02-12 Jan Beulich <jbeulich@suse.com>
674 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
675 with Unspecified, making the present one AT&T syntax only.
676 * i386-tbl.h: Re-generate.
678 2020-02-12 Jan Beulich <jbeulich@suse.com>
680 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
681 * i386-tbl.h: Re-generate.
683 2020-02-12 Jan Beulich <jbeulich@suse.com>
686 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
687 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
688 Amd64 and Intel64 templates.
689 (call, jmp): Likewise for far indirect variants. Dro
691 * i386-tbl.h: Re-generate.
693 2020-02-11 Jan Beulich <jbeulich@suse.com>
695 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
696 * i386-opc.h (ShortForm): Delete.
697 (struct i386_opcode_modifier): Remove shortform field.
698 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
699 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
700 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
701 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
703 * i386-tbl.h: Re-generate.
705 2020-02-11 Jan Beulich <jbeulich@suse.com>
707 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
708 fucompi): Drop ShortForm from operand-less templates.
709 * i386-tbl.h: Re-generate.
711 2020-02-11 Alan Modra <amodra@gmail.com>
713 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
714 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
715 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
716 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
717 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
719 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
721 * arm-dis.c (print_insn_cde): Define 'V' parse character.
722 (cde_opcodes): Add VCX* instructions.
724 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
725 Matthew Malcomson <matthew.malcomson@arm.com>
727 * arm-dis.c (struct cdeopcode32): New.
728 (CDE_OPCODE): New macro.
729 (cde_opcodes): New disassembly table.
730 (regnames): New option to table.
731 (cde_coprocs): New global variable.
732 (print_insn_cde): New
733 (print_insn_thumb32): Use print_insn_cde.
734 (parse_arm_disassembler_options): Parse coprocN args.
736 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
739 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
741 * i386-opc.h (AMD64): Removed.
745 (INTEL64ONLY): Likewise.
746 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
747 * i386-opc.tbl (Amd64): New.
749 (Intel64Only): Likewise.
750 Replace AMD64 with Amd64. Update sysenter/sysenter with
751 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
752 * i386-tbl.h: Regenerated.
754 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
757 * z80-dis.c: Add support for GBZ80 opcodes.
759 2020-02-04 Alan Modra <amodra@gmail.com>
761 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
763 2020-02-03 Alan Modra <amodra@gmail.com>
765 * m32c-ibld.c: Regenerate.
767 2020-02-01 Alan Modra <amodra@gmail.com>
769 * frv-ibld.c: Regenerate.
771 2020-01-31 Jan Beulich <jbeulich@suse.com>
773 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
774 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
775 (OP_E_memory): Replace xmm_mdq_mode case label by
776 vex_scalar_w_dq_mode one.
777 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
779 2020-01-31 Jan Beulich <jbeulich@suse.com>
781 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
782 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
783 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
784 (intel_operand_size): Drop vex_w_dq_mode case label.
786 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
788 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
789 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
791 2020-01-30 Alan Modra <amodra@gmail.com>
793 * m32c-ibld.c: Regenerate.
795 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
797 * bpf-opc.c: Regenerate.
799 2020-01-30 Jan Beulich <jbeulich@suse.com>
801 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
802 (dis386): Use them to replace C2/C3 table entries.
803 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
804 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
805 ones. Use Size64 instead of DefaultSize on Intel64 ones.
806 * i386-tbl.h: Re-generate.
808 2020-01-30 Jan Beulich <jbeulich@suse.com>
810 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
812 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
814 * i386-tbl.h: Re-generate.
816 2020-01-30 Alan Modra <amodra@gmail.com>
818 * tic4x-dis.c (tic4x_dp): Make unsigned.
820 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
821 Jan Beulich <jbeulich@suse.com>
824 * i386-dis.c (MOVSXD_Fixup): New function.
825 (movsxd_mode): New enum.
826 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
827 (intel_operand_size): Handle movsxd_mode.
828 (OP_E_register): Likewise.
830 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
831 register on movsxd. Add movsxd with 16-bit destination register
832 for AMD64 and Intel64 ISAs.
833 * i386-tbl.h: Regenerated.
835 2020-01-27 Tamar Christina <tamar.christina@arm.com>
838 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
839 * aarch64-asm-2.c: Regenerate
840 * aarch64-dis-2.c: Likewise.
841 * aarch64-opc-2.c: Likewise.
843 2020-01-21 Jan Beulich <jbeulich@suse.com>
845 * i386-opc.tbl (sysret): Drop DefaultSize.
846 * i386-tbl.h: Re-generate.
848 2020-01-21 Jan Beulich <jbeulich@suse.com>
850 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
852 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
853 * i386-tbl.h: Re-generate.
855 2020-01-20 Nick Clifton <nickc@redhat.com>
857 * po/de.po: Updated German translation.
858 * po/pt_BR.po: Updated Brazilian Portuguese translation.
859 * po/uk.po: Updated Ukranian translation.
861 2020-01-20 Alan Modra <amodra@gmail.com>
863 * hppa-dis.c (fput_const): Remove useless cast.
865 2020-01-20 Alan Modra <amodra@gmail.com>
867 * arm-dis.c (print_insn_arm): Wrap 'T' value.
869 2020-01-18 Nick Clifton <nickc@redhat.com>
871 * configure: Regenerate.
872 * po/opcodes.pot: Regenerate.
874 2020-01-18 Nick Clifton <nickc@redhat.com>
876 Binutils 2.34 branch created.
878 2020-01-17 Christian Biesinger <cbiesinger@google.com>
880 * opintl.h: Fix spelling error (seperate).
882 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
884 * i386-opc.tbl: Add {vex} pseudo prefix.
885 * i386-tbl.h: Regenerated.
887 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
890 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
891 (neon_opcodes): Likewise.
892 (select_arm_features): Make sure we enable MVE bits when selecting
893 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
896 2020-01-16 Jan Beulich <jbeulich@suse.com>
898 * i386-opc.tbl: Drop stale comment from XOP section.
900 2020-01-16 Jan Beulich <jbeulich@suse.com>
902 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
903 (extractps): Add VexWIG to SSE2AVX forms.
904 * i386-tbl.h: Re-generate.
906 2020-01-16 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
909 Size64 from and use VexW1 on SSE2AVX forms.
910 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
911 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
912 * i386-tbl.h: Re-generate.
914 2020-01-15 Alan Modra <amodra@gmail.com>
916 * tic4x-dis.c (tic4x_version): Make unsigned long.
917 (optab, optab_special, registernames): New file scope vars.
918 (tic4x_print_register): Set up registernames rather than
919 malloc'd registertable.
920 (tic4x_disassemble): Delete optable and optable_special. Use
921 optab and optab_special instead. Throw away old optab,
922 optab_special and registernames when info->mach changes.
924 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
927 * z80-dis.c (suffix): Use .db instruction to generate double
930 2020-01-14 Alan Modra <amodra@gmail.com>
932 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
933 values to unsigned before shifting.
935 2020-01-13 Thomas Troeger <tstroege@gmx.de>
937 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
939 (print_insn_thumb16, print_insn_thumb32): Likewise.
940 (print_insn): Initialize the insn info.
941 * i386-dis.c (print_insn): Initialize the insn info fields, and
944 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
946 * arc-opc.c (C_NE): Make it required.
948 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
950 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
951 reserved register name.
953 2020-01-13 Alan Modra <amodra@gmail.com>
955 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
956 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
958 2020-01-13 Alan Modra <amodra@gmail.com>
960 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
961 result of wasm_read_leb128 in a uint64_t and check that bits
962 are not lost when copying to other locals. Use uint32_t for
963 most locals. Use PRId64 when printing int64_t.
965 2020-01-13 Alan Modra <amodra@gmail.com>
967 * score-dis.c: Formatting.
968 * score7-dis.c: Formatting.
970 2020-01-13 Alan Modra <amodra@gmail.com>
972 * score-dis.c (print_insn_score48): Use unsigned variables for
973 unsigned values. Don't left shift negative values.
974 (print_insn_score32): Likewise.
975 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
977 2020-01-13 Alan Modra <amodra@gmail.com>
979 * tic4x-dis.c (tic4x_print_register): Remove dead code.
981 2020-01-13 Alan Modra <amodra@gmail.com>
983 * fr30-ibld.c: Regenerate.
985 2020-01-13 Alan Modra <amodra@gmail.com>
987 * xgate-dis.c (print_insn): Don't left shift signed value.
988 (ripBits): Formatting, use 1u.
990 2020-01-10 Alan Modra <amodra@gmail.com>
992 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
993 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
995 2020-01-10 Alan Modra <amodra@gmail.com>
997 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
998 and XRREG value earlier to avoid a shift with negative exponent.
999 * m10200-dis.c (disassemble): Similarly.
1001 2020-01-09 Nick Clifton <nickc@redhat.com>
1004 * z80-dis.c (ld_ii_ii): Use correct cast.
1006 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1009 * z80-dis.c (ld_ii_ii): Use character constant when checking
1012 2020-01-09 Jan Beulich <jbeulich@suse.com>
1014 * i386-dis.c (SEP_Fixup): New.
1016 (dis386_twobyte): Use it for sysenter/sysexit.
1017 (enum x86_64_isa): Change amd64 enumerator to value 1.
1018 (OP_J): Compare isa64 against intel64 instead of amd64.
1019 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1021 * i386-tbl.h: Re-generate.
1023 2020-01-08 Alan Modra <amodra@gmail.com>
1025 * z8k-dis.c: Include libiberty.h
1026 (instr_data_s): Make max_fetched unsigned.
1027 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1028 Don't exceed byte_info bounds.
1029 (output_instr): Make num_bytes unsigned.
1030 (unpack_instr): Likewise for nibl_count and loop.
1031 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1033 * z8k-opc.h: Regenerate.
1035 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1037 * arc-tbl.h (llock): Use 'LLOCK' as class.
1039 (scond): Use 'SCOND' as class.
1041 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1044 2020-01-06 Alan Modra <amodra@gmail.com>
1046 * m32c-ibld.c: Regenerate.
1048 2020-01-06 Alan Modra <amodra@gmail.com>
1051 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1052 Peek at next byte to prevent recursion on repeated prefix bytes.
1053 Ensure uninitialised "mybuf" is not accessed.
1054 (print_insn_z80): Don't zero n_fetch and n_used here,..
1055 (print_insn_z80_buf): ..do it here instead.
1057 2020-01-04 Alan Modra <amodra@gmail.com>
1059 * m32r-ibld.c: Regenerate.
1061 2020-01-04 Alan Modra <amodra@gmail.com>
1063 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1065 2020-01-04 Alan Modra <amodra@gmail.com>
1067 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1069 2020-01-04 Alan Modra <amodra@gmail.com>
1071 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1073 2020-01-03 Jan Beulich <jbeulich@suse.com>
1075 * aarch64-tbl.h (aarch64_opcode_table): Use
1076 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1078 2020-01-03 Jan Beulich <jbeulich@suse.com>
1080 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1081 forms of SUDOT and USDOT.
1083 2020-01-03 Jan Beulich <jbeulich@suse.com>
1085 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1087 * opcodes/aarch64-dis-2.c: Re-generate.
1089 2020-01-03 Jan Beulich <jbeulich@suse.com>
1091 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1093 * opcodes/aarch64-dis-2.c: Re-generate.
1095 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1097 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1099 2020-01-01 Alan Modra <amodra@gmail.com>
1101 Update year range in copyright notice of all files.
1103 For older changes see ChangeLog-2019
1105 Copyright (C) 2020 Free Software Foundation, Inc.
1107 Copying and distribution of this file, with or without modification,
1108 are permitted in any medium without royalty provided the copyright
1109 notice and this notice are preserved.
1115 version-control: never