opcodes/ChangeLog

   1 2020-07-14  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (OP_VexR, VexScalarR): New.
   4         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
   5         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
   6         need_vex_reg): Delete.
   7         (prefix_table): Replace VexScalar by VexScalarR and
   8         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
   9         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
  10         (vex_len_table): Replace EXqVexScalarS by EXqS.
  11         (get_valid_dis386): Don't set need_vex_reg.
  12         (print_insn): Don't initialize need_vex_reg.
  13         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
  14         q_scalar_swap_mode cases.
  15         (OP_EX): Don't check for d_scalar_swap_mode and
  16         q_scalar_swap_mode.
  17         (OP_VEX): Done check need_vex_reg.
  18         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
  19         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
  20         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
  21
  22 2020-07-14  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
  25         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
  26         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
  27         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
  28         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
  29         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
  30         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
  31         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
  32         (vex_table): Replace Vex128 by Vex.
  33         (vex_len_table): Likewise. Adjust referenced enum names.
  34         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
  35         referenced enum names.
  36         (OP_VEX): Drop vex128_mode and vex256_mode cases.
  37         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
  38
  39 2020-07-14  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-dis.c (dis386): "LW" description now applies to "DQ".
  42         (putop): Handle "DQ". Don't handle "LW" anymore.
  43         (prefix_table, mod_table): Replace %LW by %DQ.
  44         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
  45
  46 2020-07-14  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
  49         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
  50         d_scalar_swap_mode case handling. Move shift adjsutment into
  51         the case its applicable to.
  52
  53 2020-07-14  Jan Beulich  <jbeulich@suse.com>
  54
  55         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
  56         (EXbScalar, EXwScalar): Fold to ...
  57         (EXbwUnit): ... this.
  58         (b_scalar_mode, w_scalar_mode): Fold to ...
  59         (bw_unit_mode): ... this.
  60         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
  61         w_scalar_mode handling by bw_unit_mode one.
  62         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
  63         ...
  64         * i386-dis-evex-prefix.h: ... here.
  65
  66 2020-07-14  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-dis.c (PCMPESTR_Fixup): Delete.
  69         (dis386): Adjust "LQ" description.
  70         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
  71         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
  72         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
  73         vpcmpestrm, and vpcmpestri.
  74         (putop): Honor "cond" when handling LQ.
  75         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
  76         vcvtsi2ss and vcvtusi2ss.
  77         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
  78         vcvtsi2sd and vcvtusi2sd.
  79
  80 2020-07-14  Jan Beulich  <jbeulich@suse.com>
  81
  82         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
  83         (simd_cmp_op): Add const.
  84         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
  85         (CMP_Fixup): Handle VEX case.
  86         (prefix_table): Replace VCMP by CMP.
  87         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
  88
  89 2020-07-14  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-dis.c (MOVBE_Fixup): Delete.
  92         (Mv): Define.
  93         (prefix_table): Use Mv for movbe entries.
  94
  95 2020-07-14  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-dis.c (CRC32_Fixup): Delete.
  98         (prefix_table): Use Eb/Ev for crc32 entries.
  99
 100 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
 103         Conditionalize invocations of "USED_REX (0)".
 104
 105 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
 108         CH, DH, BH, AX, DX): Delete.
 109         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
 110         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
 111         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
 112
 113 2020-07-10  Lili Cui  <lili.cui@intel.com>
 114
 115         * i386-dis.c (TMM): New.
 116         (EXtmm): Likewise.
 117         (VexTmm): Likewise.
 118         (MVexSIBMEM): Likewise.
 119         (tmm_mode): Likewise.
 120         (vex_sibmem_mode): Likewise.
 121         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
 122         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
 123         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
 124         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
 125         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
 126         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
 127         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
 128         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
 129         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
 130         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
 131         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
 132         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
 133         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
 134         (PREFIX_VEX_0F3849_X86_64): Likewise.
 135         (PREFIX_VEX_0F384B_X86_64): Likewise.
 136         (PREFIX_VEX_0F385C_X86_64): Likewise.
 137         (PREFIX_VEX_0F385E_X86_64): Likewise.
 138         (X86_64_VEX_0F3849): Likewise.
 139         (X86_64_VEX_0F384B): Likewise.
 140         (X86_64_VEX_0F385C): Likewise.
 141         (X86_64_VEX_0F385E): Likewise.
 142         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
 143         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
 144         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
 145         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
 146         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
 147         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
 148         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
 149         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
 150         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
 151         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
 152         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
 153         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
 154         (VEX_W_0F3849_X86_64_P_0): Likewise.
 155         (VEX_W_0F3849_X86_64_P_2): Likewise.
 156         (VEX_W_0F3849_X86_64_P_3): Likewise.
 157         (VEX_W_0F384B_X86_64_P_1): Likewise.
 158         (VEX_W_0F384B_X86_64_P_2): Likewise.
 159         (VEX_W_0F384B_X86_64_P_3): Likewise.
 160         (VEX_W_0F385C_X86_64_P_1): Likewise.
 161         (VEX_W_0F385E_X86_64_P_0): Likewise.
 162         (VEX_W_0F385E_X86_64_P_1): Likewise.
 163         (VEX_W_0F385E_X86_64_P_2): Likewise.
 164         (VEX_W_0F385E_X86_64_P_3): Likewise.
 165         (names_tmm): Likewise.
 166         (att_names_tmm): Likewise.
 167         (intel_operand_size): Handle void_mode.
 168         (OP_XMM): Handle tmm_mode.
 169         (OP_EX): Likewise.
 170         (OP_VEX): Likewise.
 171         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
 172         CpuAMX_BF16 and CpuAMX_TILE.
 173         (operand_type_shorthands): Add RegTMM.
 174         (operand_type_init): Likewise.
 175         (operand_types): Add Tmmword.
 176         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
 177         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
 178         * i386-opc.h (CpuAMX_INT8): New.
 179         (CpuAMX_BF16): Likewise.
 180         (CpuAMX_TILE): Likewise.
 181         (SIBMEM): Likewise.
 182         (Tmmword): Likewise.
 183         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
 184         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
 185         (i386_operand_type): Add tmmword.
 186         * i386-opc.tbl: Add AMX instructions.
 187         * i386-reg.tbl: Add AMX registers.
 188         * i386-init.h: Regenerated.
 189         * i386-tbl.h: Likewise.
 190
 191 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
 194         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
 195         Rename to ...
 196         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 197         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
 198         respectively.
 199         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
 200         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
 201         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
 202         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
 203         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
 204         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
 205         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
 206         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
 207         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
 208         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
 209         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
 210         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
 211         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
 212         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
 213         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
 214         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
 215         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
 216         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
 217         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
 218         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
 219         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
 220         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
 221         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
 222         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
 223         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
 224         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
 225         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
 226         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
 227         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
 228         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
 229         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
 230         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
 231         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
 232         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
 233         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
 234         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
 235         (reg_table): Re-order XOP entries. Adjust their operands.
 236         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
 237         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
 238         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
 239         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
 240         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
 241         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
 242         entries by references ...
 243         (vex_len_table): ... to resepctive new entries here. For several
 244         new and existing entries reference ...
 245         (vex_w_table): ... new entries here.
 246         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
 247
 248 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 249
 250         * i386-dis.c (XMVexScalarI4): Define.
 251         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
 252         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
 253         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
 254         (vex_len_table): Move scalar FMA4 entries ...
 255         (prefix_table): ... here.
 256         (OP_REG_VexI4): Handle scalar_mode.
 257         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
 258         * i386-tbl.h: Re-generate.
 259
 260 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
 263         Vex_2src_2): Delete.
 264         (OP_VexW, VexW): New.
 265         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
 266         for shifts and rotates by register.
 267
 268 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 269
 270         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
 271         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
 272         OP_EX_VexReg): Delete.
 273         (OP_VexI4, VexI4): New.
 274         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
 275         (prefix_table): ... here.
 276         (print_insn): Drop setting of vex_w_done.
 277
 278 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 279
 280         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
 281         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
 282         (xop_table): Replace operands of 4-operand insns.
 283         (OP_REG_VexI4): Move VEX.W based operand swaping here.
 284
 285 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
 286
 287         * arc-opc.c (insert_rbd): New function.
 288         (RBD): Define.
 289         (RBDdup): Likewise.
 290         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
 291         instructions.
 292
 293 2020-07-07  Jan Beulich  <jbeulich@suse.com>
 294
 295         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
 296         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
 297         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
 298         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
 299         Delete.
 300         (putop): Handle "BW".
 301         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
 302         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
 303         and 0F3A3F ...
 304         * i386-dis-evex-prefix.h: ... here.
 305
 306 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
 309         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
 310         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
 311         VEX_W_0FXOP_09_83): New enumerators.
 312         (xop_table): Reference the above.
 313         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
 314         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
 315         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
 316         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
 317
 318 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-dis.c (EVEX_W_0F3838_P_1,
 321         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
 322         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
 323         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
 324         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
 325         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
 326         (putop): Centralize management of last[]. Delete SAVE_LAST.
 327         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
 328         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
 329         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
 330         * i386-dis-evex-prefix.h: here.
 331
 332 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
 335         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
 336         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
 337         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
 338         enumerators.
 339         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
 340         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
 341         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
 342         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
 343         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
 344         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
 345         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
 346         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
 347         these, respectively.
 348         * i386-dis-evex-len.h: Adjust comments.
 349         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
 350         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
 351         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
 352         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
 353         MOD_EVEX_0F385B_P_2_W_1 table entries.
 354         * i386-dis-evex-w.h: Reference mod_table[] for
 355         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
 356         EVEX_W_0F385B_P_2.
 357
 358 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
 361         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
 362         EXymm.
 363         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
 364         Likewise. Mark 256-bit entries invalid.
 365
 366 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
 369         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
 370         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
 371         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
 372         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
 373         PREFIX_EVEX_0F382B): Delete.
 374         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
 375         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
 376         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
 377         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
 378         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
 379         to ...
 380         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
 381         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
 382         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
 383         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
 384         respectively.
 385         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
 386         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
 387         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
 388         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
 389         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
 390         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
 391         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
 392         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
 393         PREFIX_EVEX_0F382B): Remove table entries.
 394         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
 395         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
 396         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
 397
 398 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 399
 400         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
 401         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
 402         enumerators.
 403         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
 404         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
 405         EVEX_LEN_0F3A01_P_2_W_1 table entries.
 406         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
 407         entries.
 408
 409 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
 412         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
 413         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
 414         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
 415         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
 416         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
 417         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
 418         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
 419         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
 420         entries.
 421
 422 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 423
 424         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
 425         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
 426         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
 427         respectively.
 428         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
 429         entries.
 430         * i386-dis-evex.h (evex_table): Reference VEX table entry for
 431         opcode 0F3A1D.
 432         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
 433         entry.
 434         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
 435
 436 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 439         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 440         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 441         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 442         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 443         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 444         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 445         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 446         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 447         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 448         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 449         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 450         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 451         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 452         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 453         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 454         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 455         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 456         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 457         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 458         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 459         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 460         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 461         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 462         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 463         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 464         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
 465         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
 466         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
 467         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
 468         (prefix_table): Add EXxEVexR to FMA table entries.
 469         (OP_Rounding): Move abort() invocation.
 470         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
 471         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
 472         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
 473         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
 474         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
 475         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
 476         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
 477         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
 478         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
 479         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
 480         0F3ACE, 0F3ACF.
 481         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 482         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 483         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 484         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 485         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 486         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 487         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 488         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 489         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 490         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 491         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 492         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 493         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 494         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 495         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 496         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 497         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 498         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 499         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 500         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 501         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 502         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 503         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 504         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 505         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 506         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 507         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
 508         Delete table entries.
 509         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
 510         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
 511         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
 512         Likewise.
 513
 514 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 515
 516         * i386-dis.c (EXqScalarS): Delete.
 517         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
 518         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
 519
 520 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 521
 522         * i386-dis.c (safe-ctype.h): Include.
 523         (EXdScalar, EXqScalar): Delete.
 524         (d_scalar_mode, q_scalar_mode): Delete.
 525         (prefix_table, vex_len_table): Use EXxmm_md in place of
 526         EXdScalar and EXxmm_mq in place of EXqScalar.
 527         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
 528         d_scalar_mode and q_scalar_mode.
 529         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
 530         (vmovsd): Use EXxmm_mq.
 531
 532 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
 533
 534         PR 26204
 535         * arc-dis.c: Fix spelling mistake.
 536         * po/opcodes.pot: Regenerate.
 537
 538 2020-07-06  Nick Clifton  <nickc@redhat.com>
 539
 540         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 541         * po/uk.po: Updated Ukranian translation.
 542
 543 2020-07-04  Nick Clifton  <nickc@redhat.com>
 544
 545         * configure: Regenerate.
 546         * po/opcodes.pot: Regenerate.
 547
 548 2020-07-04  Nick Clifton  <nickc@redhat.com>
 549
 550         Binutils 2.35 branch created.
 551
 552 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 555         * i386-opc.h (VexSwapSources): New.
 556         (i386_opcode_modifier): Add vexswapsources.
 557         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 558         with two source operands swapped.
 559         * i386-tbl.h: Regenerated.
 560
 561 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 562
 563         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 564         unprivileged CSR can also be initialized.
 565
 566 2020-06-29  Alan Modra  <amodra@gmail.com>
 567
 568         * arm-dis.c: Use C style comments.
 569         * cr16-opc.c: Likewise.
 570         * ft32-dis.c: Likewise.
 571         * moxie-opc.c: Likewise.
 572         * tic54x-dis.c: Likewise.
 573         * s12z-opc.c: Remove useless comment.
 574         * xgate-dis.c: Likewise.
 575
 576 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 577
 578         * i386-opc.tbl: Add a blank line.
 579
 580 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 581
 582         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 583         (VecSIB128): Renamed to ...
 584         (VECSIB128): This.
 585         (VecSIB256): Renamed to ...
 586         (VECSIB256): This.
 587         (VecSIB512): Renamed to ...
 588         (VECSIB512): This.
 589         (VecSIB): Renamed to ...
 590         (SIB): This.
 591         (i386_opcode_modifier): Replace vecsib with sib.
 592         * i386-opc.tbl (VecSIB128): New.
 593         (VecSIB256): Likewise.
 594         (VecSIB512): Likewise.
 595         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 596         and VecSIB512, respectively.
 597
 598 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-dis.c: Adjust description of I macro.
 601         (x86_64_table): Drop use of I.
 602         (float_mem): Replace use of I.
 603         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 604
 605 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 606
 607         * i386-dis.c: (print_insn): Avoid straight assignment to
 608         priv.orig_sizeflag when processing -M sub-options.
 609
 610 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 611
 612         * i386-dis.c: Adjust description of J macro.
 613         (dis386, x86_64_table, mod_table): Replace J.
 614         (putop): Remove handling of J.
 615
 616 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 619
 620 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-dis.c: Adjust description of "LQ" macro.
 623         (dis386_twobyte): Use LQ for sysret.
 624         (putop): Adjust handling of LQ.
 625
 626 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 627
 628         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 629         * riscv-dis.c: Include elfxx-riscv.h.
 630
 631 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 632
 633         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 634
 635 2020-06-17  Lili Cui  <lili.cui@intel.com>
 636
 637         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 638
 639 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 640
 641         PR gas/26115
 642         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 643         * i386-opc.tbl: Likewise.
 644         * i386-tbl.h: Regenerated.
 645
 646 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 647
 648         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 649
 650 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 651
 652         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 653         (SR_CORE): Likewise.
 654         (SR_FEAT): Likewise.
 655         (SR_RNG): Likewise.
 656         (SR_V8_1): Likewise.
 657         (SR_V8_2): Likewise.
 658         (SR_V8_3): Likewise.
 659         (SR_V8_4): Likewise.
 660         (SR_PAN): Likewise.
 661         (SR_RAS): Likewise.
 662         (SR_SSBS): Likewise.
 663         (SR_SVE): Likewise.
 664         (SR_ID_PFR2): Likewise.
 665         (SR_PROFILE): Likewise.
 666         (SR_MEMTAG): Likewise.
 667         (SR_SCXTNUM): Likewise.
 668         (aarch64_sys_regs): Refactor to store feature information in the table.
 669         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 670         that now describe their own features.
 671         (aarch64_pstatefield_supported_p): Likewise.
 672
 673 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 674
 675         * i386-dis.c (prefix_table): Fix a typo in comments.
 676
 677 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 678
 679         * i386-dis.c (rex_ignored): Delete.
 680         (ckprefix): Drop rex_ignored initialization.
 681         (get_valid_dis386): Drop setting of rex_ignored.
 682         (print_insn): Drop checking of rex_ignored. Don't record data
 683         size prefix as used with VEX-and-alike encodings.
 684
 685 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 688         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 689         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 690         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 691         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 692         VEX_0F12, and VEX_0F16.
 693         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 694         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 695         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 696         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 697         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 698         MOD_VEX_0F16_PREFIX_2 entries.
 699
 700 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 703         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 704         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 705         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 706         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 707         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 708         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 709         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 710         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 711         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 712         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 713         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 714         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 715         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 716         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 717         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 718         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 719         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 720         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 721         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 722         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 723         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 724         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 725         EVEX_W_0FC6_P_2): Delete.
 726         (print_insn): Add EVEX.W vs embedded prefix consistency check
 727         to prefix validation.
 728         * i386-dis-evex.h (evex_table): Don't further descend for
 729         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 730         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 731         and 0F2B.
 732         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 733         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 734         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 735         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 736         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 737         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 738         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 739         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 740         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 741         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 742         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 743         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 744         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 745         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 746         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 747         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 748         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 749         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 750         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 751         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 752         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 753         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 754         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 755         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 756         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 757         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 758         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 759
 760 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 763         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 764         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 765         vmovmskpX.
 766         (print_insn): Drop pointless check against bad_opcode. Split
 767         prefix validation into legacy and VEX-and-alike parts.
 768         (putop): Re-work 'X' macro handling.
 769
 770 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-dis.c (MOD_0F51): Rename to ...
 773         (MOD_0F50): ... this.
 774
 775 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 776
 777         * arm-dis.c (arm_opcodes): Add dfb.
 778         (thumb32_opcodes): Add dfb.
 779
 780 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 781
 782         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 783
 784 2020-06-06  Alan Modra  <amodra@gmail.com>
 785
 786         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 787
 788 2020-06-05  Alan Modra  <amodra@gmail.com>
 789
 790         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 791         size is large enough.
 792
 793 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 794
 795         * disassemble.c (disassemble_init_for_target): Set endian_code for
 796         bpf targets.
 797         * bpf-desc.c: Regenerate.
 798         * bpf-opc.c: Likewise.
 799         * bpf-dis.c: Likewise.
 800
 801 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 802
 803         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 804         (cgen_put_insn_value): Likewise.
 805         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 806         * cgen-dis.in (print_insn): Likewise.
 807         * cgen-ibld.in (insert_1): Likewise.
 808         (insert_1): Likewise.
 809         (insert_insn_normal): Likewise.
 810         (extract_1): Likewise.
 811         * bpf-dis.c: Regenerate.
 812         * bpf-ibld.c: Likewise.
 813         * bpf-ibld.c: Likewise.
 814         * cgen-dis.in: Likewise.
 815         * cgen-ibld.in: Likewise.
 816         * cgen-opc.c: Likewise.
 817         * epiphany-dis.c: Likewise.
 818         * epiphany-ibld.c: Likewise.
 819         * fr30-dis.c: Likewise.
 820         * fr30-ibld.c: Likewise.
 821         * frv-dis.c: Likewise.
 822         * frv-ibld.c: Likewise.
 823         * ip2k-dis.c: Likewise.
 824         * ip2k-ibld.c: Likewise.
 825         * iq2000-dis.c: Likewise.
 826         * iq2000-ibld.c: Likewise.
 827         * lm32-dis.c: Likewise.
 828         * lm32-ibld.c: Likewise.
 829         * m32c-dis.c: Likewise.
 830         * m32c-ibld.c: Likewise.
 831         * m32r-dis.c: Likewise.
 832         * m32r-ibld.c: Likewise.
 833         * mep-dis.c: Likewise.
 834         * mep-ibld.c: Likewise.
 835         * mt-dis.c: Likewise.
 836         * mt-ibld.c: Likewise.
 837         * or1k-dis.c: Likewise.
 838         * or1k-ibld.c: Likewise.
 839         * xc16x-dis.c: Likewise.
 840         * xc16x-ibld.c: Likewise.
 841         * xstormy16-dis.c: Likewise.
 842         * xstormy16-ibld.c: Likewise.
 843
 844 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 845
 846         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 847         (print_insn_): Handle instruction endian.
 848         * bpf-dis.c: Regenerate.
 849         * bpf-desc.c: Regenerate.
 850         * epiphany-dis.c: Likewise.
 851         * epiphany-desc.c: Likewise.
 852         * fr30-dis.c: Likewise.
 853         * fr30-desc.c: Likewise.
 854         * frv-dis.c: Likewise.
 855         * frv-desc.c: Likewise.
 856         * ip2k-dis.c: Likewise.
 857         * ip2k-desc.c: Likewise.
 858         * iq2000-dis.c: Likewise.
 859         * iq2000-desc.c: Likewise.
 860         * lm32-dis.c: Likewise.
 861         * lm32-desc.c: Likewise.
 862         * m32c-dis.c: Likewise.
 863         * m32c-desc.c: Likewise.
 864         * m32r-dis.c: Likewise.
 865         * m32r-desc.c: Likewise.
 866         * mep-dis.c: Likewise.
 867         * mep-desc.c: Likewise.
 868         * mt-dis.c: Likewise.
 869         * mt-desc.c: Likewise.
 870         * or1k-dis.c: Likewise.
 871         * or1k-desc.c: Likewise.
 872         * xc16x-dis.c: Likewise.
 873         * xc16x-desc.c: Likewise.
 874         * xstormy16-dis.c: Likewise.
 875         * xstormy16-desc.c: Likewise.
 876
 877 2020-06-03  Nick Clifton  <nickc@redhat.com>
 878
 879         * po/sr.po: Updated Serbian translation.
 880
 881 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 882
 883         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 884         (riscv_get_priv_spec_class): Likewise.
 885
 886 2020-06-01  Alan Modra  <amodra@gmail.com>
 887
 888         * bpf-desc.c: Regenerate.
 889
 890 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 891             David Faust <david.faust@oracle.com>
 892
 893         * bpf-desc.c: Regenerate.
 894         * bpf-opc.h: Likewise.
 895         * bpf-opc.c: Likewise.
 896         * bpf-dis.c: Likewise.
 897
 898 2020-05-28  Alan Modra  <amodra@gmail.com>
 899
 900         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 901         values.
 902
 903 2020-05-28  Alan Modra  <amodra@gmail.com>
 904
 905         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 906         immediates.
 907         (print_insn_ns32k): Revert last change.
 908
 909 2020-05-28  Nick Clifton  <nickc@redhat.com>
 910
 911         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 912         static.
 913
 914 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 915
 916         Fix extraction of signed constants in nios2 disassembler (again).
 917
 918         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 919         extractions of signed fields.
 920
 921 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 922
 923         * s390-opc.txt: Relocate vector load/store instructions with
 924         additional alignment parameter and change architecture level
 925         constraint from z14 to z13.
 926
 927 2020-05-21  Alan Modra  <amodra@gmail.com>
 928
 929         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 930         * sparc-dis.c: Likewise.
 931         * tic4x-dis.c: Likewise.
 932         * xtensa-dis.c: Likewise.
 933         * bpf-desc.c: Regenerate.
 934         * epiphany-desc.c: Regenerate.
 935         * fr30-desc.c: Regenerate.
 936         * frv-desc.c: Regenerate.
 937         * ip2k-desc.c: Regenerate.
 938         * iq2000-desc.c: Regenerate.
 939         * lm32-desc.c: Regenerate.
 940         * m32c-desc.c: Regenerate.
 941         * m32r-desc.c: Regenerate.
 942         * mep-asm.c: Regenerate.
 943         * mep-desc.c: Regenerate.
 944         * mt-desc.c: Regenerate.
 945         * or1k-desc.c: Regenerate.
 946         * xc16x-desc.c: Regenerate.
 947         * xstormy16-desc.c: Regenerate.
 948
 949 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 950
 951         * riscv-opc.c (riscv_ext_version_table): The table used to store
 952         all information about the supported spec and the corresponding ISA
 953         versions.  Currently, only Zicsr is supported to verify the
 954         correctness of Z sub extension settings.  Others will be supported
 955         in the future patches.
 956         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 957         classes and the corresponding strings.
 958         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 959         spec class by giving a ISA spec string.
 960         * riscv-opc.c (struct priv_spec_t): New structure.
 961         (struct priv_spec_t priv_specs): List for all supported privilege spec
 962         classes and the corresponding strings.
 963         (riscv_get_priv_spec_class): New function.  Get the corresponding
 964         privilege spec class by giving a spec string.
 965         (riscv_get_priv_spec_name): New function.  Get the corresponding
 966         privilege spec string by giving a CSR version class.
 967         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 968         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 969         according to the chosen version.  Build a hash table riscv_csr_hash to
 970         store the valid CSR for the chosen pirv verison.  Dump the direct
 971         CSR address rather than it's name if it is invalid.
 972         (parse_riscv_dis_option_without_args): New function.  Parse the options
 973         without arguments.
 974         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 975         parse the options without arguments first, and then handle the options
 976         with arguments.  Add the new option -Mpriv-spec, which has argument.
 977         * riscv-dis.c (print_riscv_disassembler_options): Add description
 978         about the new OBJDUMP option.
 979
 980 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 981
 982         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 983         WC values on POWER10 sync, dcbf  and wait instructions.
 984         (insert_pl, extract_pl): New functions.
 985         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 986         (LS3): New , 3-bit L for sync.
 987         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 988         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 989         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 990         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 991         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 992         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 993         <wait>: Enable PL operand on POWER10.
 994         <dcbf>: Enable L3OPT operand on POWER10.
 995         <sync>: Enable SC2 operand on POWER10.
 996
 997 2020-05-19  Stafford Horne  <shorne@gmail.com>
 998
 999         PR 25184
1000         * or1k-asm.c: Regenerate.
1001         * or1k-desc.c: Regenerate.
1002         * or1k-desc.h: Regenerate.
1003         * or1k-dis.c: Regenerate.
1004         * or1k-ibld.c: Regenerate.
1005         * or1k-opc.c: Regenerate.
1006         * or1k-opc.h: Regenerate.
1007         * or1k-opinst.c: Regenerate.
1008
1009 2020-05-11  Alan Modra  <amodra@gmail.com>
1010
1011         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1012         xsmaxcqp, xsmincqp.
1013
1014 2020-05-11  Alan Modra  <amodra@gmail.com>
1015
1016         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1017         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1018
1019 2020-05-11  Alan Modra  <amodra@gmail.com>
1020
1021         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1022
1023 2020-05-11  Alan Modra  <amodra@gmail.com>
1024
1025         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1026         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1027
1028 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1029
1030         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1031         mnemonics.
1032
1033 2020-05-11  Alan Modra  <amodra@gmail.com>
1034
1035         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1036         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1037         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1038         (prefix_opcodes): Add xxeval.
1039
1040 2020-05-11  Alan Modra  <amodra@gmail.com>
1041
1042         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1043         xxgenpcvwm, xxgenpcvdm.
1044
1045 2020-05-11  Alan Modra  <amodra@gmail.com>
1046
1047         * ppc-opc.c (MP, VXVAM_MASK): Define.
1048         (VXVAPS_MASK): Use VXVA_MASK.
1049         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1050         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1051         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1052         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1053
1054 2020-05-11  Alan Modra  <amodra@gmail.com>
1055             Peter Bergner  <bergner@linux.ibm.com>
1056
1057         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1058         New functions.
1059         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1060         YMSK2, XA6a, XA6ap, XB6a entries.
1061         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1062         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1063         (PPCVSX4): Define.
1064         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1065         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1066         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1067         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1068         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1069         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1070         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1071         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1072         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1073         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1074         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1075         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1076         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1077         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1078
1079 2020-05-11  Alan Modra  <amodra@gmail.com>
1080
1081         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1082         (insert_xts, extract_xts): New functions.
1083         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1084         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1085         (VXRC_MASK, VXSH_MASK): Define.
1086         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1087         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1088         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1089         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1090         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1091         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1092         xxblendvh, xxblendvw, xxblendvd, xxpermx.
1093
1094 2020-05-11  Alan Modra  <amodra@gmail.com>
1095
1096         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1097         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1098         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1099         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1100         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1101
1102 2020-05-11  Alan Modra  <amodra@gmail.com>
1103
1104         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1105         (XTP, DQXP, DQXP_MASK): Define.
1106         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1107         (prefix_opcodes): Add plxvp and pstxvp.
1108
1109 2020-05-11  Alan Modra  <amodra@gmail.com>
1110
1111         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1112         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1113         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1114
1115 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1116
1117         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1118
1119 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1120
1121         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1122         (L1OPT): Define.
1123         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1124
1125 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1126
1127         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1128
1129 2020-05-11  Alan Modra  <amodra@gmail.com>
1130
1131         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1132
1133 2020-05-11  Alan Modra  <amodra@gmail.com>
1134
1135         * ppc-dis.c (ppc_opts): Add "power10" entry.
1136         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1137         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
1138
1139 2020-05-11  Nick Clifton  <nickc@redhat.com>
1140
1141         * po/fr.po: Updated French translation.
1142
1143 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
1144
1145         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1146         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1147         (operand_general_constraint_met_p): validate
1148         AARCH64_OPND_UNDEFINED.
1149         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1150         for FLD_imm16_2.
1151         * aarch64-asm-2.c: Regenerated.
1152         * aarch64-dis-2.c: Regenerated.
1153         * aarch64-opc-2.c: Regenerated.
1154
1155 2020-04-29  Nick Clifton  <nickc@redhat.com>
1156
1157         PR 22699
1158         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1159         and SETRC insns.
1160
1161 2020-04-29  Nick Clifton  <nickc@redhat.com>
1162
1163         * po/sv.po: Updated Swedish translation.
1164
1165 2020-04-29  Nick Clifton  <nickc@redhat.com>
1166
1167         PR 22699
1168         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
1169         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1170         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1171         IMM0_8U case.
1172
1173 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
1174
1175         PR 25848
1176         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1177         cmpi only on m68020up and cpu32.
1178
1179 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
1180
1181         * aarch64-asm.c (aarch64_ins_none): New.
1182         * aarch64-asm.h (ins_none): New declaration.
1183         * aarch64-dis.c (aarch64_ext_none): New.
1184         * aarch64-dis.h (ext_none): New declaration.
1185         * aarch64-opc.c (aarch64_print_operand): Update case for
1186         AARCH64_OPND_BARRIER_PSB.
1187         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1188         (AARCH64_OPERANDS): Update inserter/extracter for
1189         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1190         * aarch64-asm-2.c: Regenerated.
1191         * aarch64-dis-2.c: Regenerated.
1192         * aarch64-opc-2.c: Regenerated.
1193
1194 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
1195
1196         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1197         (aarch64_feature_ras, RAS): Likewise.
1198         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1199         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1200         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1201         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1202         * aarch64-asm-2.c: Regenerated.
1203         * aarch64-dis-2.c: Regenerated.
1204         * aarch64-opc-2.c: Regenerated.
1205
1206 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
1207
1208         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1209         (print_insn_neon): Support disassembly of conditional
1210         instructions.
1211
1212 2020-02-16  David Faust  <david.faust@oracle.com>
1213
1214         * bpf-desc.c: Regenerate.
1215         * bpf-desc.h: Likewise.
1216         * bpf-opc.c: Regenerate.
1217         * bpf-opc.h: Likewise.
1218
1219 2020-04-07  Lili Cui  <lili.cui@intel.com>
1220
1221         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1222         (prefix_table): New instructions (see prefixes above).
1223         (rm_table): Likewise
1224         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1225         CPU_ANY_TSXLDTRK_FLAGS.
1226         (cpu_flags): Add CpuTSXLDTRK.
1227         * i386-opc.h (enum): Add CpuTSXLDTRK.
1228         (i386_cpu_flags): Add cputsxldtrk.
1229         * i386-opc.tbl: Add XSUSPLDTRK insns.
1230         * i386-init.h: Regenerate.
1231         * i386-tbl.h: Likewise.
1232
1233 2020-04-02  Lili Cui  <lili.cui@intel.com>
1234
1235         * i386-dis.c (prefix_table): New instructions serialize.
1236         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1237         CPU_ANY_SERIALIZE_FLAGS.
1238         (cpu_flags): Add CpuSERIALIZE.
1239         * i386-opc.h (enum): Add CpuSERIALIZE.
1240         (i386_cpu_flags): Add cpuserialize.
1241         * i386-opc.tbl: Add SERIALIZE insns.
1242         * i386-init.h: Regenerate.
1243         * i386-tbl.h: Likewise.
1244
1245 2020-03-26  Alan Modra  <amodra@gmail.com>
1246
1247         * disassemble.h (opcodes_assert): Declare.
1248         (OPCODES_ASSERT): Define.
1249         * disassemble.c: Don't include assert.h.  Include opintl.h.
1250         (opcodes_assert): New function.
1251         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1252         (bfd_h8_disassemble): Reduce size of data array.  Correctly
1253         calculate maxlen.  Omit insn decoding when insn length exceeds
1254         maxlen.  Exit from nibble loop when looking for E, before
1255         accessing next data byte.  Move processing of E outside loop.
1256         Replace tests of maxlen in loop with assertions.
1257
1258 2020-03-26  Alan Modra  <amodra@gmail.com>
1259
1260         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
1261
1262 2020-03-25  Alan Modra  <amodra@gmail.com>
1263
1264         * z80-dis.c (suffix): Init mybuf.
1265
1266 2020-03-22  Alan Modra  <amodra@gmail.com>
1267
1268         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1269         successflly read from section.
1270
1271 2020-03-22  Alan Modra  <amodra@gmail.com>
1272
1273         * arc-dis.c (find_format): Use ISO C string concatenation rather
1274         than line continuation within a string.  Don't access needs_limm
1275         before testing opcode != NULL.
1276
1277 2020-03-22  Alan Modra  <amodra@gmail.com>
1278
1279         * ns32k-dis.c (print_insn_arg): Update comment.
1280         (print_insn_ns32k): Reduce size of index_offset array, and
1281         initialize, passing -1 to print_insn_arg for args that are not
1282         an index.  Don't exit arg loop early.  Abort on bad arg number.
1283
1284 2020-03-22  Alan Modra  <amodra@gmail.com>
1285
1286         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1287         * s12z-opc.c: Formatting.
1288         (operands_f): Return an int.
1289         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1290         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1291         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1292         (exg_sex_discrim): Likewise.
1293         (create_immediate_operand, create_bitfield_operand),
1294         (create_register_operand_with_size, create_register_all_operand),
1295         (create_register_all16_operand, create_simple_memory_operand),
1296         (create_memory_operand, create_memory_auto_operand): Don't
1297         segfault on malloc failure.
1298         (z_ext24_decode): Return an int status, negative on fail, zero
1299         on success.
1300         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1301         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1302         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1303         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1304         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1305         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1306         (loop_primitive_decode, shift_decode, psh_pul_decode),
1307         (bit_field_decode): Similarly.
1308         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
1309         to return value, update callers.
1310         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1311         Don't segfault on NULL operand.
1312         (decode_operation): Return OP_INVALID on first fail.
1313         (decode_s12z): Check all reads, returning -1 on fail.
1314
1315 2020-03-20  Alan Modra  <amodra@gmail.com>
1316
1317         * metag-dis.c (print_insn_metag): Don't ignore status from
1318         read_memory_func.
1319
1320 2020-03-20  Alan Modra  <amodra@gmail.com>
1321
1322         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1323         Initialize parts of buffer not written when handling a possible
1324         2-byte insn at end of section.  Don't attempt decoding of such
1325         an insn by the 4-byte machinery.
1326
1327 2020-03-20  Alan Modra  <amodra@gmail.com>
1328
1329         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1330         partially filled buffer.  Prevent lookup of 4-byte insns when
1331         only VLE 2-byte insns are possible due to section size.  Print
1332         ".word" rather than ".long" for 2-byte leftovers.
1333
1334 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
1335
1336         PR 25641
1337         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1338
1339 2020-03-13  Jan Beulich  <jbeulich@suse.com>
1340
1341         * i386-dis.c (X86_64_0D): Rename to ...
1342         (X86_64_0E): ... this.
1343
1344 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1345
1346         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1347         * Makefile.in: Regenerated.
1348
1349 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1350
1351         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1352         3-operand pseudos.
1353         * i386-tbl.h: Re-generate.
1354
1355 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1356
1357         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1358         vprot*, vpsha*, and vpshl*.
1359         * i386-tbl.h: Re-generate.
1360
1361 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1362
1363         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1364         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1365         * i386-tbl.h: Re-generate.
1366
1367 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1368
1369         * i386-gen.c (set_bitfield): Ignore zero-length field names.
1370         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1371         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1372         * i386-tbl.h: Re-generate.
1373
1374 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1375
1376         * i386-gen.c (struct template_arg, struct template_instance,
1377         struct template_param, struct template, templates,
1378         parse_template, expand_templates): New.
1379         (process_i386_opcodes): Various local variables moved to
1380         expand_templates. Call parse_template and expand_templates.
1381         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1382         * i386-tbl.h: Re-generate.
1383
1384 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1385
1386         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1387         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1388         register and memory source templates. Replace VexW= by VexW*
1389         where applicable.
1390         * i386-tbl.h: Re-generate.
1391
1392 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1393
1394         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1395         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1396         * i386-tbl.h: Re-generate.
1397
1398 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1399
1400         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1401         * i386-tbl.h: Re-generate.
1402
1403 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1404
1405         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1406         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1407         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1408         VexW0 on SSE2AVX variants.
1409         (vmovq): Drop NoRex64 from XMM/XMM variants.
1410         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1411         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1412         applicable use VexW0.
1413         * i386-tbl.h: Re-generate.
1414
1415 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1416
1417         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1418         * i386-opc.h (Rex64): Delete.
1419         (struct i386_opcode_modifier): Remove rex64 field.
1420         * i386-opc.tbl (crc32): Drop Rex64.
1421         Replace Rex64 with Size64 everywhere else.
1422         * i386-tbl.h: Re-generate.
1423
1424 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1425
1426         * i386-dis.c (OP_E_memory): Exclude recording of used address
1427         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1428         addressed memory operands for MPX insns.
1429
1430 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1431
1432         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1433         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1434         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1435         (ptwrite): Split into non-64-bit and 64-bit forms.
1436         * i386-tbl.h: Re-generate.
1437
1438 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1439
1440         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1441         template.
1442         * i386-tbl.h: Re-generate.
1443
1444 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1445
1446         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1447         (prefix_table): Move vmmcall here. Add vmgexit.
1448         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1449         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1450         (cpu_flags): Add CpuSEV_ES entry.
1451         * i386-opc.h (CpuSEV_ES): New.
1452         (union i386_cpu_flags): Add cpusev_es field.
1453         * i386-opc.tbl (vmgexit): New.
1454         * i386-init.h, i386-tbl.h: Re-generate.
1455
1456 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1457
1458         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1459         with MnemonicSize.
1460         * i386-opc.h (IGNORESIZE): New.
1461         (DEFAULTSIZE): Likewise.
1462         (IgnoreSize): Removed.
1463         (DefaultSize): Likewise.
1464         (MnemonicSize): New.
1465         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1466         mnemonicsize.
1467         * i386-opc.tbl (IgnoreSize): New.
1468         (DefaultSize): Likewise.
1469         * i386-tbl.h: Regenerated.
1470
1471 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1472
1473         PR 25627
1474         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1475         instructions.
1476
1477 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1478
1479         PR gas/25622
1480         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1481         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1482         * i386-tbl.h: Regenerated.
1483
1484 2020-02-26  Alan Modra  <amodra@gmail.com>
1485
1486         * aarch64-asm.c: Indent labels correctly.
1487         * aarch64-dis.c: Likewise.
1488         * aarch64-gen.c: Likewise.
1489         * aarch64-opc.c: Likewise.
1490         * alpha-dis.c: Likewise.
1491         * i386-dis.c: Likewise.
1492         * nds32-asm.c: Likewise.
1493         * nfp-dis.c: Likewise.
1494         * visium-dis.c: Likewise.
1495
1496 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1497
1498         * arc-regs.h (int_vector_base): Make it available for all ARC
1499         CPUs.
1500
1501 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1502
1503         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1504         changed.
1505
1506 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1507
1508         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1509         c.mv/c.li if rs1 is zero.
1510
1511 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1512
1513         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1514         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1515         CPU_POPCNT_FLAGS.
1516         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1517         * i386-opc.h (CpuABM): Removed.
1518         (CpuPOPCNT): New.
1519         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1520         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1521         popcnt.  Remove CpuABM from lzcnt.
1522         * i386-init.h: Regenerated.
1523         * i386-tbl.h: Likewise.
1524
1525 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1526
1527         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1528         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1529         VexW1 instead of open-coding them.
1530         * i386-tbl.h: Re-generate.
1531
1532 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1533
1534         * i386-opc.tbl (AddrPrefixOpReg): Define.
1535         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1536         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1537         templates. Drop NoRex64.
1538         * i386-tbl.h: Re-generate.
1539
1540 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1541
1542         PR gas/6518
1543         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1544         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1545         into Intel syntax instance (with Unpsecified) and AT&T one
1546         (without).
1547         (vcvtneps2bf16): Likewise, along with folding the two so far
1548         separate ones.
1549         * i386-tbl.h: Re-generate.
1550
1551 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1552
1553         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1554         CPU_ANY_SSE4A_FLAGS.
1555
1556 2020-02-17  Alan Modra  <amodra@gmail.com>
1557
1558         * i386-gen.c (cpu_flag_init): Correct last change.
1559
1560 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1561
1562         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1563         CPU_ANY_SSE4_FLAGS.
1564
1565 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1566
1567         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1568         (movzx): Likewise.
1569
1570 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1571
1572         PR gas/25438
1573         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1574         destination for Cpu64-only variant.
1575         (movzx): Fold patterns.
1576         * i386-tbl.h: Re-generate.
1577
1578 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1579
1580         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1581         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1582         CPU_ANY_SSE4_FLAGS entry.
1583         * i386-init.h: Re-generate.
1584
1585 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1586
1587         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1588         with Unspecified, making the present one AT&T syntax only.
1589         * i386-tbl.h: Re-generate.
1590
1591 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1592
1593         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1594         * i386-tbl.h: Re-generate.
1595
1596 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1597
1598         PR gas/24546
1599         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1600         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1601         Amd64 and Intel64 templates.
1602         (call, jmp): Likewise for far indirect variants. Dro
1603         Unspecified.
1604         * i386-tbl.h: Re-generate.
1605
1606 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1607
1608         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1609         * i386-opc.h (ShortForm): Delete.
1610         (struct i386_opcode_modifier): Remove shortform field.
1611         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1612         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1613         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1614         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1615         Drop ShortForm.
1616         * i386-tbl.h: Re-generate.
1617
1618 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1619
1620         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1621         fucompi): Drop ShortForm from operand-less templates.
1622         * i386-tbl.h: Re-generate.
1623
1624 2020-02-11  Alan Modra  <amodra@gmail.com>
1625
1626         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1627         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1628         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1629         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1630         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1631
1632 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1633
1634         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1635         (cde_opcodes): Add VCX* instructions.
1636
1637 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1638             Matthew Malcomson  <matthew.malcomson@arm.com>
1639
1640         * arm-dis.c (struct cdeopcode32): New.
1641         (CDE_OPCODE): New macro.
1642         (cde_opcodes): New disassembly table.
1643         (regnames): New option to table.
1644         (cde_coprocs): New global variable.
1645         (print_insn_cde): New
1646         (print_insn_thumb32): Use print_insn_cde.
1647         (parse_arm_disassembler_options): Parse coprocN args.
1648
1649 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1650
1651         PR gas/25516
1652         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1653         with ISA64.
1654         * i386-opc.h (AMD64): Removed.
1655         (Intel64): Likewose.
1656         (AMD64): New.
1657         (INTEL64): Likewise.
1658         (INTEL64ONLY): Likewise.
1659         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1660         * i386-opc.tbl (Amd64): New.
1661         (Intel64): Likewise.
1662         (Intel64Only): Likewise.
1663         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1664         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1665         * i386-tbl.h: Regenerated.
1666
1667 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1668
1669         PR 25469
1670         * z80-dis.c: Add support for GBZ80 opcodes.
1671
1672 2020-02-04  Alan Modra  <amodra@gmail.com>
1673
1674         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1675
1676 2020-02-03  Alan Modra  <amodra@gmail.com>
1677
1678         * m32c-ibld.c: Regenerate.
1679
1680 2020-02-01  Alan Modra  <amodra@gmail.com>
1681
1682         * frv-ibld.c: Regenerate.
1683
1684 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1685
1686         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1687         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1688         (OP_E_memory): Replace xmm_mdq_mode case label by
1689         vex_scalar_w_dq_mode one.
1690         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1691
1692 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1693
1694         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1695         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1696         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1697         (intel_operand_size): Drop vex_w_dq_mode case label.
1698
1699 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1700
1701         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1702         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1703
1704 2020-01-30  Alan Modra  <amodra@gmail.com>
1705
1706         * m32c-ibld.c: Regenerate.
1707
1708 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1709
1710         * bpf-opc.c: Regenerate.
1711
1712 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1713
1714         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1715         (dis386): Use them to replace C2/C3 table entries.
1716         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1717         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1718         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1719         * i386-tbl.h: Re-generate.
1720
1721 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1722
1723         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1724         forms.
1725         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1726         DefaultSize.
1727         * i386-tbl.h: Re-generate.
1728
1729 2020-01-30  Alan Modra  <amodra@gmail.com>
1730
1731         * tic4x-dis.c (tic4x_dp): Make unsigned.
1732
1733 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1734             Jan Beulich  <jbeulich@suse.com>
1735
1736         PR binutils/25445
1737         * i386-dis.c (MOVSXD_Fixup): New function.
1738         (movsxd_mode): New enum.
1739         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1740         (intel_operand_size): Handle movsxd_mode.
1741         (OP_E_register): Likewise.
1742         (OP_G): Likewise.
1743         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1744         register on movsxd.  Add movsxd with 16-bit destination register
1745         for AMD64 and Intel64 ISAs.
1746         * i386-tbl.h: Regenerated.
1747
1748 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1749
1750         PR 25403
1751         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1752         * aarch64-asm-2.c: Regenerate
1753         * aarch64-dis-2.c: Likewise.
1754         * aarch64-opc-2.c: Likewise.
1755
1756 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1757
1758         * i386-opc.tbl (sysret): Drop DefaultSize.
1759         * i386-tbl.h: Re-generate.
1760
1761 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1762
1763         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1764         Dword.
1765         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1766         * i386-tbl.h: Re-generate.
1767
1768 2020-01-20  Nick Clifton  <nickc@redhat.com>
1769
1770         * po/de.po: Updated German translation.
1771         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1772         * po/uk.po: Updated Ukranian translation.
1773
1774 2020-01-20  Alan Modra  <amodra@gmail.com>
1775
1776         * hppa-dis.c (fput_const): Remove useless cast.
1777
1778 2020-01-20  Alan Modra  <amodra@gmail.com>
1779
1780         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1781
1782 2020-01-18  Nick Clifton  <nickc@redhat.com>
1783
1784         * configure: Regenerate.
1785         * po/opcodes.pot: Regenerate.
1786
1787 2020-01-18  Nick Clifton  <nickc@redhat.com>
1788
1789         Binutils 2.34 branch created.
1790
1791 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1792
1793         * opintl.h: Fix spelling error (seperate).
1794
1795 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1796
1797         * i386-opc.tbl: Add {vex} pseudo prefix.
1798         * i386-tbl.h: Regenerated.
1799
1800 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1801
1802         PR 25376
1803         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1804         (neon_opcodes): Likewise.
1805         (select_arm_features): Make sure we enable MVE bits when selecting
1806         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1807         any architecture.
1808
1809 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1810
1811         * i386-opc.tbl: Drop stale comment from XOP section.
1812
1813 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1814
1815         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1816         (extractps): Add VexWIG to SSE2AVX forms.
1817         * i386-tbl.h: Re-generate.
1818
1819 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1820
1821         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1822         Size64 from and use VexW1 on SSE2AVX forms.
1823         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1824         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1825         * i386-tbl.h: Re-generate.
1826
1827 2020-01-15  Alan Modra  <amodra@gmail.com>
1828
1829         * tic4x-dis.c (tic4x_version): Make unsigned long.
1830         (optab, optab_special, registernames): New file scope vars.
1831         (tic4x_print_register): Set up registernames rather than
1832         malloc'd registertable.
1833         (tic4x_disassemble): Delete optable and optable_special.  Use
1834         optab and optab_special instead.  Throw away old optab,
1835         optab_special and registernames when info->mach changes.
1836
1837 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1838
1839         PR 25377
1840         * z80-dis.c (suffix): Use .db instruction to generate double
1841         prefix.
1842
1843 2020-01-14  Alan Modra  <amodra@gmail.com>
1844
1845         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1846         values to unsigned before shifting.
1847
1848 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1849
1850         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1851         flow instructions.
1852         (print_insn_thumb16, print_insn_thumb32): Likewise.
1853         (print_insn): Initialize the insn info.
1854         * i386-dis.c (print_insn): Initialize the insn info fields, and
1855         detect jumps.
1856
1857 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1858
1859         * arc-opc.c (C_NE): Make it required.
1860
1861 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1862
1863         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1864         reserved register name.
1865
1866 2020-01-13  Alan Modra  <amodra@gmail.com>
1867
1868         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1869         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1870
1871 2020-01-13  Alan Modra  <amodra@gmail.com>
1872
1873         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1874         result of wasm_read_leb128 in a uint64_t and check that bits
1875         are not lost when copying to other locals.  Use uint32_t for
1876         most locals.  Use PRId64 when printing int64_t.
1877
1878 2020-01-13  Alan Modra  <amodra@gmail.com>
1879
1880         * score-dis.c: Formatting.
1881         * score7-dis.c: Formatting.
1882
1883 2020-01-13  Alan Modra  <amodra@gmail.com>
1884
1885         * score-dis.c (print_insn_score48): Use unsigned variables for
1886         unsigned values.  Don't left shift negative values.
1887         (print_insn_score32): Likewise.
1888         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1889
1890 2020-01-13  Alan Modra  <amodra@gmail.com>
1891
1892         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1893
1894 2020-01-13  Alan Modra  <amodra@gmail.com>
1895
1896         * fr30-ibld.c: Regenerate.
1897
1898 2020-01-13  Alan Modra  <amodra@gmail.com>
1899
1900         * xgate-dis.c (print_insn): Don't left shift signed value.
1901         (ripBits): Formatting, use 1u.
1902
1903 2020-01-10  Alan Modra  <amodra@gmail.com>
1904
1905         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1906         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1907
1908 2020-01-10  Alan Modra  <amodra@gmail.com>
1909
1910         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1911         and XRREG value earlier to avoid a shift with negative exponent.
1912         * m10200-dis.c (disassemble): Similarly.
1913
1914 2020-01-09  Nick Clifton  <nickc@redhat.com>
1915
1916         PR 25224
1917         * z80-dis.c (ld_ii_ii): Use correct cast.
1918
1919 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1920
1921         PR 25224
1922         * z80-dis.c (ld_ii_ii): Use character constant when checking
1923         opcode byte value.
1924
1925 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1926
1927         * i386-dis.c (SEP_Fixup): New.
1928         (SEP): Define.
1929         (dis386_twobyte): Use it for sysenter/sysexit.
1930         (enum x86_64_isa): Change amd64 enumerator to value 1.
1931         (OP_J): Compare isa64 against intel64 instead of amd64.
1932         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1933         forms.
1934         * i386-tbl.h: Re-generate.
1935
1936 2020-01-08  Alan Modra  <amodra@gmail.com>
1937
1938         * z8k-dis.c: Include libiberty.h
1939         (instr_data_s): Make max_fetched unsigned.
1940         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1941         Don't exceed byte_info bounds.
1942         (output_instr): Make num_bytes unsigned.
1943         (unpack_instr): Likewise for nibl_count and loop.
1944         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1945         idx unsigned.
1946         * z8k-opc.h: Regenerate.
1947
1948 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1949
1950         * arc-tbl.h (llock): Use 'LLOCK' as class.
1951         (llockd): Likewise.
1952         (scond): Use 'SCOND' as class.
1953         (scondd): Likewise.
1954         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1955         (scondd): Likewise.
1956
1957 2020-01-06  Alan Modra  <amodra@gmail.com>
1958
1959         * m32c-ibld.c: Regenerate.
1960
1961 2020-01-06  Alan Modra  <amodra@gmail.com>
1962
1963         PR 25344
1964         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1965         Peek at next byte to prevent recursion on repeated prefix bytes.
1966         Ensure uninitialised "mybuf" is not accessed.
1967         (print_insn_z80): Don't zero n_fetch and n_used here,..
1968         (print_insn_z80_buf): ..do it here instead.
1969
1970 2020-01-04  Alan Modra  <amodra@gmail.com>
1971
1972         * m32r-ibld.c: Regenerate.
1973
1974 2020-01-04  Alan Modra  <amodra@gmail.com>
1975
1976         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1977
1978 2020-01-04  Alan Modra  <amodra@gmail.com>
1979
1980         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1981
1982 2020-01-04  Alan Modra  <amodra@gmail.com>
1983
1984         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1985
1986 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1987
1988         * aarch64-tbl.h (aarch64_opcode_table): Use
1989         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1990
1991 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1992
1993         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1994         forms of SUDOT and USDOT.
1995
1996 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1997
1998         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1999         uzip{1,2}.
2000         * opcodes/aarch64-dis-2.c: Re-generate.
2001
2002 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2003
2004         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2005         FMMLA encoding.
2006         * opcodes/aarch64-dis-2.c: Re-generate.
2007
2008 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
2009
2010         * z80-dis.c: Add support for eZ80 and Z80 instructions.
2011
2012 2020-01-01  Alan Modra  <amodra@gmail.com>
2013
2014         Update year range in copyright notice of all files.
2015
2016 For older changes see ChangeLog-2019
2017 \f
2018 Copyright (C) 2020 Free Software Foundation, Inc.
2019
2020 Copying and distribution of this file, with or without modification,
2021 are permitted in any medium without royalty provided the copyright
2022 notice and this notice are preserved.
2023
2024 Local Variables:
2025 mode: change-log
2026 left-margin: 8
2027 fill-column: 74
2028 version-control: never
2029 End: