1 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
4 * tic6x-dis.c: Add support for displaying 16-bit insns.
6 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
9 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
10 individual msb and lsb halves in src1 & src2 fields. Discard the
11 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
12 follow what Ti SDK does in that case as any value in the src1
13 field yields the same output with SDK disassembler.
15 2013-03-12 Michael Eager <eager@eagercon.com>
17 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
19 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
21 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
23 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
25 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
27 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
29 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
31 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
33 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
34 (thumb32_opcodes): Likewise.
35 (print_insn_thumb32): Handle 'S' control char.
37 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
39 * lm32-desc.c: Regenerate.
41 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
43 * i386-reg.tbl (riz): Add RegRex64.
44 * i386-tbl.h: Regenerated.
46 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
48 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
49 (aarch64_feature_crc): New static.
51 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
52 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
53 * aarch64-asm-2.c: Re-generate.
54 * aarch64-dis-2.c: Ditto.
55 * aarch64-opc-2.c: Ditto.
57 2013-02-27 Alan Modra <amodra@gmail.com>
59 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
60 * rl78-decode.c: Regenerate.
62 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
64 * rl78-decode.opc: Fix encoding of DIVWU insn.
65 * rl78-decode.c: Regenerate.
67 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
70 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
72 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
73 (cpu_flags): Add CpuSMAP.
75 * i386-opc.h (CpuSMAP): New.
76 (i386_cpu_flags): Add cpusmap.
78 * i386-opc.tbl: Add clac and stac.
80 * i386-init.h: Regenerated.
81 * i386-tbl.h: Likewise.
83 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
85 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
86 which also makes the disassembler output be in little
87 endian like it should be.
89 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
91 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
93 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
95 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
97 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
100 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
102 * arm-dis.c: Update strht pattern.
104 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
106 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
107 single-float. Disable ll, lld, sc and scd for EE. Disable the
108 trunc.w.s macro for EE.
110 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
111 Andrew Jenner <andrew@codesourcery.com>
113 Based on patches from Altera Corporation.
115 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
117 * Makefile.in: Regenerated.
118 * configure.in: Add case for bfd_nios2_arch.
119 * configure: Regenerated.
120 * disassemble.c (ARCH_nios2): Define.
121 (disassembler): Add case for bfd_arch_nios2.
122 * nios2-dis.c: New file.
123 * nios2-opc.c: New file.
125 2013-02-04 Alan Modra <amodra@gmail.com>
127 * po/POTFILES.in: Regenerate.
128 * rl78-decode.c: Regenerate.
129 * rx-decode.c: Regenerate.
131 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
133 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
134 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
135 * aarch64-asm.c (convert_xtl_to_shll): New function.
136 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
137 calling convert_xtl_to_shll.
138 * aarch64-dis.c (convert_shll_to_xtl): New function.
139 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
140 calling convert_shll_to_xtl.
141 * aarch64-gen.c: Update copyright year.
142 * aarch64-asm-2.c: Re-generate.
143 * aarch64-dis-2.c: Re-generate.
144 * aarch64-opc-2.c: Re-generate.
146 2013-01-24 Nick Clifton <nickc@redhat.com>
148 * v850-dis.c: Add support for e3v5 architecture.
149 * v850-opc.c: Likewise.
151 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
153 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
154 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
155 * aarch64-opc.c (operand_general_constraint_met_p): For
156 AARCH64_MOD_LSL, move the range check on the shift amount before the
157 alignment check; change to call set_sft_amount_out_of_range_error
158 instead of set_imm_out_of_range_error.
159 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
160 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
161 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
164 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
166 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
168 * i386-init.h: Regenerated.
169 * i386-tbl.h: Likewise.
171 2013-01-15 Nick Clifton <nickc@redhat.com>
173 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
175 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
177 2013-01-14 Will Newton <will.newton@imgtec.com>
179 * metag-dis.c (REG_WIDTH): Increase to 64.
181 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
183 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
184 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
185 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
187 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
188 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
189 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
190 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
192 2013-01-10 Will Newton <will.newton@imgtec.com>
194 * Makefile.am: Add Meta.
195 * configure.in: Add Meta.
196 * disassemble.c: Add Meta support.
197 * metag-dis.c: New file.
198 * Makefile.in: Regenerate.
199 * configure: Regenerate.
201 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
203 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
204 (match_opcode): Rename to cr16_match_opcode.
206 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
208 * mips-dis.c: Add names for CP0 registers of r5900.
209 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
210 instructions sq and lq.
211 Add support for MIPS r5900 CPU.
212 Add support for 128 bit MMI (Multimedia Instructions).
213 Add support for EE instructions (Emotion Engine).
214 Disable unsupported floating point instructions (64 bit and
215 undefined compare operations).
216 Enable instructions of MIPS ISA IV which are supported by r5900.
217 Disable 64 bit co processor instructions.
218 Disable 64 bit multiplication and division instructions.
219 Disable instructions for co-processor 2 and 3, because these are
220 not supported (preparation for later VU0 support (Vector Unit)).
221 Disable cvt.w.s because this behaves like trunc.w.s and the
222 correct execution can't be ensured on r5900.
223 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
224 will confuse less developers and compilers.
226 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
228 * aarch64-opc.c (aarch64_print_operand): Change to print
229 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
231 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
232 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
235 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
237 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
238 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
240 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
242 * i386-gen.c (process_copyright): Update copyright year to 2013.
244 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
246 * cr16-dis.c (match_opcode,make_instruction): Remove static
248 (dwordU,wordU): Moved typedefs to opcode/cr16.h
249 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
251 For older changes see ChangeLog-2012
253 Copyright (C) 2013 Free Software Foundation, Inc.
255 Copying and distribution of this file, with or without modification,
256 are permitted in any medium without royalty provided the copyright
257 notice and this notice are preserved.
263 version-control: never