opcodes/ChangeLog

   1 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (prefix_table): Revert the last vmgexit change.
   4
   5 2020-06-17  Lili Cui  <lili.cui@intel.com>
   6
   7         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
   8
   9 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
  10
  11         PR gas/26115
  12         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
  13         * i386-opc.tbl: Likewise.
  14         * i386-tbl.h: Regenerated.
  15
  16 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
  17
  18         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
  19
  20 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
  21
  22         * aarch64-opc.c (SYSREG): New macro for describing system registers.
  23         (SR_CORE): Likewise.
  24         (SR_FEAT): Likewise.
  25         (SR_RNG): Likewise.
  26         (SR_V8_1): Likewise.
  27         (SR_V8_2): Likewise.
  28         (SR_V8_3): Likewise.
  29         (SR_V8_4): Likewise.
  30         (SR_PAN): Likewise.
  31         (SR_RAS): Likewise.
  32         (SR_SSBS): Likewise.
  33         (SR_SVE): Likewise.
  34         (SR_ID_PFR2): Likewise.
  35         (SR_PROFILE): Likewise.
  36         (SR_MEMTAG): Likewise.
  37         (SR_SCXTNUM): Likewise.
  38         (aarch64_sys_regs): Refactor to store feature information in the table.
  39         (aarch64_sys_reg_supported_p): Collapse logic for system registers
  40         that now describe their own features.
  41         (aarch64_pstatefield_supported_p): Likewise.
  42
  43 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
  44
  45         * i386-dis.c (prefix_table): Fix a typo in comments.
  46
  47 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-dis.c (rex_ignored): Delete.
  50         (ckprefix): Drop rex_ignored initialization.
  51         (get_valid_dis386): Drop setting of rex_ignored.
  52         (print_insn): Drop checking of rex_ignored. Don't record data
  53         size prefix as used with VEX-and-alike encodings.
  54
  55 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
  58         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
  59         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
  60         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
  61         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
  62         VEX_0F12, and VEX_0F16.
  63         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
  64         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
  65         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
  66         from movlps and movhlps. New MOD_0F12_PREFIX_2,
  67         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
  68         MOD_VEX_0F16_PREFIX_2 entries.
  69
  70 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
  73         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
  74         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  75         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
  76         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
  77         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
  78         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
  79         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
  80         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
  81         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
  82         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
  83         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
  84         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
  85         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
  86         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
  87         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
  88         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
  89         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
  90         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
  91         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
  92         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
  93         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
  94         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
  95         EVEX_W_0FC6_P_2): Delete.
  96         (print_insn): Add EVEX.W vs embedded prefix consistency check
  97         to prefix validation.
  98         * i386-dis-evex.h (evex_table): Don't further descend for
  99         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 100         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 101         and 0F2B.
 102         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 103         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 104         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 105         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 106         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 107         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 108         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 109         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 110         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 111         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 112         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 113         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 114         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 115         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 116         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 117         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 118         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 119         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 120         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 121         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 122         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 123         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 124         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 125         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 126         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 127         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 128         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 129
 130 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 133         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 134         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 135         vmovmskpX.
 136         (print_insn): Drop pointless check against bad_opcode. Split
 137         prefix validation into legacy and VEX-and-alike parts.
 138         (putop): Re-work 'X' macro handling.
 139
 140 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-dis.c (MOD_0F51): Rename to ...
 143         (MOD_0F50): ... this.
 144
 145 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 146
 147         * arm-dis.c (arm_opcodes): Add dfb.
 148         (thumb32_opcodes): Add dfb.
 149
 150 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 153
 154 2020-06-06  Alan Modra  <amodra@gmail.com>
 155
 156         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 157
 158 2020-06-05  Alan Modra  <amodra@gmail.com>
 159
 160         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 161         size is large enough.
 162
 163 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 164
 165         * disassemble.c (disassemble_init_for_target): Set endian_code for
 166         bpf targets.
 167         * bpf-desc.c: Regenerate.
 168         * bpf-opc.c: Likewise.
 169         * bpf-dis.c: Likewise.
 170
 171 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 172
 173         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 174         (cgen_put_insn_value): Likewise.
 175         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 176         * cgen-dis.in (print_insn): Likewise.
 177         * cgen-ibld.in (insert_1): Likewise.
 178         (insert_1): Likewise.
 179         (insert_insn_normal): Likewise.
 180         (extract_1): Likewise.
 181         * bpf-dis.c: Regenerate.
 182         * bpf-ibld.c: Likewise.
 183         * bpf-ibld.c: Likewise.
 184         * cgen-dis.in: Likewise.
 185         * cgen-ibld.in: Likewise.
 186         * cgen-opc.c: Likewise.
 187         * epiphany-dis.c: Likewise.
 188         * epiphany-ibld.c: Likewise.
 189         * fr30-dis.c: Likewise.
 190         * fr30-ibld.c: Likewise.
 191         * frv-dis.c: Likewise.
 192         * frv-ibld.c: Likewise.
 193         * ip2k-dis.c: Likewise.
 194         * ip2k-ibld.c: Likewise.
 195         * iq2000-dis.c: Likewise.
 196         * iq2000-ibld.c: Likewise.
 197         * lm32-dis.c: Likewise.
 198         * lm32-ibld.c: Likewise.
 199         * m32c-dis.c: Likewise.
 200         * m32c-ibld.c: Likewise.
 201         * m32r-dis.c: Likewise.
 202         * m32r-ibld.c: Likewise.
 203         * mep-dis.c: Likewise.
 204         * mep-ibld.c: Likewise.
 205         * mt-dis.c: Likewise.
 206         * mt-ibld.c: Likewise.
 207         * or1k-dis.c: Likewise.
 208         * or1k-ibld.c: Likewise.
 209         * xc16x-dis.c: Likewise.
 210         * xc16x-ibld.c: Likewise.
 211         * xstormy16-dis.c: Likewise.
 212         * xstormy16-ibld.c: Likewise.
 213
 214 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 215
 216         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 217         (print_insn_): Handle instruction endian.
 218         * bpf-dis.c: Regenerate.
 219         * bpf-desc.c: Regenerate.
 220         * epiphany-dis.c: Likewise.
 221         * epiphany-desc.c: Likewise.
 222         * fr30-dis.c: Likewise.
 223         * fr30-desc.c: Likewise.
 224         * frv-dis.c: Likewise.
 225         * frv-desc.c: Likewise.
 226         * ip2k-dis.c: Likewise.
 227         * ip2k-desc.c: Likewise.
 228         * iq2000-dis.c: Likewise.
 229         * iq2000-desc.c: Likewise.
 230         * lm32-dis.c: Likewise.
 231         * lm32-desc.c: Likewise.
 232         * m32c-dis.c: Likewise.
 233         * m32c-desc.c: Likewise.
 234         * m32r-dis.c: Likewise.
 235         * m32r-desc.c: Likewise.
 236         * mep-dis.c: Likewise.
 237         * mep-desc.c: Likewise.
 238         * mt-dis.c: Likewise.
 239         * mt-desc.c: Likewise.
 240         * or1k-dis.c: Likewise.
 241         * or1k-desc.c: Likewise.
 242         * xc16x-dis.c: Likewise.
 243         * xc16x-desc.c: Likewise.
 244         * xstormy16-dis.c: Likewise.
 245         * xstormy16-desc.c: Likewise.
 246
 247 2020-06-03  Nick Clifton  <nickc@redhat.com>
 248
 249         * po/sr.po: Updated Serbian translation.
 250
 251 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 252
 253         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 254         (riscv_get_priv_spec_class): Likewise.
 255
 256 2020-06-01  Alan Modra  <amodra@gmail.com>
 257
 258         * bpf-desc.c: Regenerate.
 259
 260 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 261             David Faust <david.faust@oracle.com>
 262
 263         * bpf-desc.c: Regenerate.
 264         * bpf-opc.h: Likewise.
 265         * bpf-opc.c: Likewise.
 266         * bpf-dis.c: Likewise.
 267
 268 2020-05-28  Alan Modra  <amodra@gmail.com>
 269
 270         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 271         values.
 272
 273 2020-05-28  Alan Modra  <amodra@gmail.com>
 274
 275         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 276         immediates.
 277         (print_insn_ns32k): Revert last change.
 278
 279 2020-05-28  Nick Clifton  <nickc@redhat.com>
 280
 281         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 282         static.
 283
 284 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 285
 286         Fix extraction of signed constants in nios2 disassembler (again).
 287
 288         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 289         extractions of signed fields.
 290
 291 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 292
 293         * s390-opc.txt: Relocate vector load/store instructions with
 294         additional alignment parameter and change architecture level
 295         constraint from z14 to z13.
 296
 297 2020-05-21  Alan Modra  <amodra@gmail.com>
 298
 299         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 300         * sparc-dis.c: Likewise.
 301         * tic4x-dis.c: Likewise.
 302         * xtensa-dis.c: Likewise.
 303         * bpf-desc.c: Regenerate.
 304         * epiphany-desc.c: Regenerate.
 305         * fr30-desc.c: Regenerate.
 306         * frv-desc.c: Regenerate.
 307         * ip2k-desc.c: Regenerate.
 308         * iq2000-desc.c: Regenerate.
 309         * lm32-desc.c: Regenerate.
 310         * m32c-desc.c: Regenerate.
 311         * m32r-desc.c: Regenerate.
 312         * mep-asm.c: Regenerate.
 313         * mep-desc.c: Regenerate.
 314         * mt-desc.c: Regenerate.
 315         * or1k-desc.c: Regenerate.
 316         * xc16x-desc.c: Regenerate.
 317         * xstormy16-desc.c: Regenerate.
 318
 319 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 320
 321         * riscv-opc.c (riscv_ext_version_table): The table used to store
 322         all information about the supported spec and the corresponding ISA
 323         versions.  Currently, only Zicsr is supported to verify the
 324         correctness of Z sub extension settings.  Others will be supported
 325         in the future patches.
 326         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 327         classes and the corresponding strings.
 328         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 329         spec class by giving a ISA spec string.
 330         * riscv-opc.c (struct priv_spec_t): New structure.
 331         (struct priv_spec_t priv_specs): List for all supported privilege spec
 332         classes and the corresponding strings.
 333         (riscv_get_priv_spec_class): New function.  Get the corresponding
 334         privilege spec class by giving a spec string.
 335         (riscv_get_priv_spec_name): New function.  Get the corresponding
 336         privilege spec string by giving a CSR version class.
 337         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 338         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 339         according to the chosen version.  Build a hash table riscv_csr_hash to
 340         store the valid CSR for the chosen pirv verison.  Dump the direct
 341         CSR address rather than it's name if it is invalid.
 342         (parse_riscv_dis_option_without_args): New function.  Parse the options
 343         without arguments.
 344         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 345         parse the options without arguments first, and then handle the options
 346         with arguments.  Add the new option -Mpriv-spec, which has argument.
 347         * riscv-dis.c (print_riscv_disassembler_options): Add description
 348         about the new OBJDUMP option.
 349
 350 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 351
 352         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 353         WC values on POWER10 sync, dcbf  and wait instructions.
 354         (insert_pl, extract_pl): New functions.
 355         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 356         (LS3): New , 3-bit L for sync.
 357         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 358         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 359         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 360         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 361         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 362         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 363         <wait>: Enable PL operand on POWER10.
 364         <dcbf>: Enable L3OPT operand on POWER10.
 365         <sync>: Enable SC2 operand on POWER10.
 366
 367 2020-05-19  Stafford Horne  <shorne@gmail.com>
 368
 369         PR 25184
 370         * or1k-asm.c: Regenerate.
 371         * or1k-desc.c: Regenerate.
 372         * or1k-desc.h: Regenerate.
 373         * or1k-dis.c: Regenerate.
 374         * or1k-ibld.c: Regenerate.
 375         * or1k-opc.c: Regenerate.
 376         * or1k-opc.h: Regenerate.
 377         * or1k-opinst.c: Regenerate.
 378
 379 2020-05-11  Alan Modra  <amodra@gmail.com>
 380
 381         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 382         xsmaxcqp, xsmincqp.
 383
 384 2020-05-11  Alan Modra  <amodra@gmail.com>
 385
 386         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 387         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 388
 389 2020-05-11  Alan Modra  <amodra@gmail.com>
 390
 391         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 392
 393 2020-05-11  Alan Modra  <amodra@gmail.com>
 394
 395         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 396         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 397
 398 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 399
 400         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 401         mnemonics.
 402
 403 2020-05-11  Alan Modra  <amodra@gmail.com>
 404
 405         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 406         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 407         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 408         (prefix_opcodes): Add xxeval.
 409
 410 2020-05-11  Alan Modra  <amodra@gmail.com>
 411
 412         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 413         xxgenpcvwm, xxgenpcvdm.
 414
 415 2020-05-11  Alan Modra  <amodra@gmail.com>
 416
 417         * ppc-opc.c (MP, VXVAM_MASK): Define.
 418         (VXVAPS_MASK): Use VXVA_MASK.
 419         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 420         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 421         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 422         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 423
 424 2020-05-11  Alan Modra  <amodra@gmail.com>
 425             Peter Bergner  <bergner@linux.ibm.com>
 426
 427         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 428         New functions.
 429         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 430         YMSK2, XA6a, XA6ap, XB6a entries.
 431         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 432         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 433         (PPCVSX4): Define.
 434         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 435         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 436         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 437         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 438         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 439         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 440         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 441         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 442         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 443         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 444         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 445         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 446         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 447         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 448
 449 2020-05-11  Alan Modra  <amodra@gmail.com>
 450
 451         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 452         (insert_xts, extract_xts): New functions.
 453         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 454         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 455         (VXRC_MASK, VXSH_MASK): Define.
 456         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 457         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 458         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 459         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 460         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 461         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 462         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 463
 464 2020-05-11  Alan Modra  <amodra@gmail.com>
 465
 466         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 467         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 468         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 469         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 470         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 471
 472 2020-05-11  Alan Modra  <amodra@gmail.com>
 473
 474         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 475         (XTP, DQXP, DQXP_MASK): Define.
 476         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 477         (prefix_opcodes): Add plxvp and pstxvp.
 478
 479 2020-05-11  Alan Modra  <amodra@gmail.com>
 480
 481         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 482         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 483         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 484
 485 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 486
 487         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 488
 489 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 490
 491         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 492         (L1OPT): Define.
 493         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 494
 495 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 496
 497         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 498
 499 2020-05-11  Alan Modra  <amodra@gmail.com>
 500
 501         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 502
 503 2020-05-11  Alan Modra  <amodra@gmail.com>
 504
 505         * ppc-dis.c (ppc_opts): Add "power10" entry.
 506         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 507         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 508
 509 2020-05-11  Nick Clifton  <nickc@redhat.com>
 510
 511         * po/fr.po: Updated French translation.
 512
 513 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 514
 515         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 516         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 517         (operand_general_constraint_met_p): validate
 518         AARCH64_OPND_UNDEFINED.
 519         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 520         for FLD_imm16_2.
 521         * aarch64-asm-2.c: Regenerated.
 522         * aarch64-dis-2.c: Regenerated.
 523         * aarch64-opc-2.c: Regenerated.
 524
 525 2020-04-29  Nick Clifton  <nickc@redhat.com>
 526
 527         PR 22699
 528         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 529         and SETRC insns.
 530
 531 2020-04-29  Nick Clifton  <nickc@redhat.com>
 532
 533         * po/sv.po: Updated Swedish translation.
 534
 535 2020-04-29  Nick Clifton  <nickc@redhat.com>
 536
 537         PR 22699
 538         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 539         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 540         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 541         IMM0_8U case.
 542
 543 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 544
 545         PR 25848
 546         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 547         cmpi only on m68020up and cpu32.
 548
 549 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 550
 551         * aarch64-asm.c (aarch64_ins_none): New.
 552         * aarch64-asm.h (ins_none): New declaration.
 553         * aarch64-dis.c (aarch64_ext_none): New.
 554         * aarch64-dis.h (ext_none): New declaration.
 555         * aarch64-opc.c (aarch64_print_operand): Update case for
 556         AARCH64_OPND_BARRIER_PSB.
 557         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 558         (AARCH64_OPERANDS): Update inserter/extracter for
 559         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 560         * aarch64-asm-2.c: Regenerated.
 561         * aarch64-dis-2.c: Regenerated.
 562         * aarch64-opc-2.c: Regenerated.
 563
 564 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 565
 566         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 567         (aarch64_feature_ras, RAS): Likewise.
 568         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 569         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 570         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 571         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 572         * aarch64-asm-2.c: Regenerated.
 573         * aarch64-dis-2.c: Regenerated.
 574         * aarch64-opc-2.c: Regenerated.
 575
 576 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 577
 578         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 579         (print_insn_neon): Support disassembly of conditional
 580         instructions.
 581
 582 2020-02-16  David Faust  <david.faust@oracle.com>
 583
 584         * bpf-desc.c: Regenerate.
 585         * bpf-desc.h: Likewise.
 586         * bpf-opc.c: Regenerate.
 587         * bpf-opc.h: Likewise.
 588
 589 2020-04-07  Lili Cui  <lili.cui@intel.com>
 590
 591         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 592         (prefix_table): New instructions (see prefixes above).
 593         (rm_table): Likewise
 594         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 595         CPU_ANY_TSXLDTRK_FLAGS.
 596         (cpu_flags): Add CpuTSXLDTRK.
 597         * i386-opc.h (enum): Add CpuTSXLDTRK.
 598         (i386_cpu_flags): Add cputsxldtrk.
 599         * i386-opc.tbl: Add XSUSPLDTRK insns.
 600         * i386-init.h: Regenerate.
 601         * i386-tbl.h: Likewise.
 602
 603 2020-04-02  Lili Cui  <lili.cui@intel.com>
 604
 605         * i386-dis.c (prefix_table): New instructions serialize.
 606         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 607         CPU_ANY_SERIALIZE_FLAGS.
 608         (cpu_flags): Add CpuSERIALIZE.
 609         * i386-opc.h (enum): Add CpuSERIALIZE.
 610         (i386_cpu_flags): Add cpuserialize.
 611         * i386-opc.tbl: Add SERIALIZE insns.
 612         * i386-init.h: Regenerate.
 613         * i386-tbl.h: Likewise.
 614
 615 2020-03-26  Alan Modra  <amodra@gmail.com>
 616
 617         * disassemble.h (opcodes_assert): Declare.
 618         (OPCODES_ASSERT): Define.
 619         * disassemble.c: Don't include assert.h.  Include opintl.h.
 620         (opcodes_assert): New function.
 621         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 622         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 623         calculate maxlen.  Omit insn decoding when insn length exceeds
 624         maxlen.  Exit from nibble loop when looking for E, before
 625         accessing next data byte.  Move processing of E outside loop.
 626         Replace tests of maxlen in loop with assertions.
 627
 628 2020-03-26  Alan Modra  <amodra@gmail.com>
 629
 630         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 631
 632 2020-03-25  Alan Modra  <amodra@gmail.com>
 633
 634         * z80-dis.c (suffix): Init mybuf.
 635
 636 2020-03-22  Alan Modra  <amodra@gmail.com>
 637
 638         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 639         successflly read from section.
 640
 641 2020-03-22  Alan Modra  <amodra@gmail.com>
 642
 643         * arc-dis.c (find_format): Use ISO C string concatenation rather
 644         than line continuation within a string.  Don't access needs_limm
 645         before testing opcode != NULL.
 646
 647 2020-03-22  Alan Modra  <amodra@gmail.com>
 648
 649         * ns32k-dis.c (print_insn_arg): Update comment.
 650         (print_insn_ns32k): Reduce size of index_offset array, and
 651         initialize, passing -1 to print_insn_arg for args that are not
 652         an index.  Don't exit arg loop early.  Abort on bad arg number.
 653
 654 2020-03-22  Alan Modra  <amodra@gmail.com>
 655
 656         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 657         * s12z-opc.c: Formatting.
 658         (operands_f): Return an int.
 659         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 660         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 661         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 662         (exg_sex_discrim): Likewise.
 663         (create_immediate_operand, create_bitfield_operand),
 664         (create_register_operand_with_size, create_register_all_operand),
 665         (create_register_all16_operand, create_simple_memory_operand),
 666         (create_memory_operand, create_memory_auto_operand): Don't
 667         segfault on malloc failure.
 668         (z_ext24_decode): Return an int status, negative on fail, zero
 669         on success.
 670         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 671         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 672         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 673         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 674         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 675         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 676         (loop_primitive_decode, shift_decode, psh_pul_decode),
 677         (bit_field_decode): Similarly.
 678         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 679         to return value, update callers.
 680         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 681         Don't segfault on NULL operand.
 682         (decode_operation): Return OP_INVALID on first fail.
 683         (decode_s12z): Check all reads, returning -1 on fail.
 684
 685 2020-03-20  Alan Modra  <amodra@gmail.com>
 686
 687         * metag-dis.c (print_insn_metag): Don't ignore status from
 688         read_memory_func.
 689
 690 2020-03-20  Alan Modra  <amodra@gmail.com>
 691
 692         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 693         Initialize parts of buffer not written when handling a possible
 694         2-byte insn at end of section.  Don't attempt decoding of such
 695         an insn by the 4-byte machinery.
 696
 697 2020-03-20  Alan Modra  <amodra@gmail.com>
 698
 699         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 700         partially filled buffer.  Prevent lookup of 4-byte insns when
 701         only VLE 2-byte insns are possible due to section size.  Print
 702         ".word" rather than ".long" for 2-byte leftovers.
 703
 704 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 705
 706         PR 25641
 707         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 708
 709 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 710
 711         * i386-dis.c (X86_64_0D): Rename to ...
 712         (X86_64_0E): ... this.
 713
 714 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 715
 716         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 717         * Makefile.in: Regenerated.
 718
 719 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 720
 721         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 722         3-operand pseudos.
 723         * i386-tbl.h: Re-generate.
 724
 725 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 728         vprot*, vpsha*, and vpshl*.
 729         * i386-tbl.h: Re-generate.
 730
 731 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 732
 733         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 734         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 735         * i386-tbl.h: Re-generate.
 736
 737 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 738
 739         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 740         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 741         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 742         * i386-tbl.h: Re-generate.
 743
 744 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 745
 746         * i386-gen.c (struct template_arg, struct template_instance,
 747         struct template_param, struct template, templates,
 748         parse_template, expand_templates): New.
 749         (process_i386_opcodes): Various local variables moved to
 750         expand_templates. Call parse_template and expand_templates.
 751         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 752         * i386-tbl.h: Re-generate.
 753
 754 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 757         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 758         register and memory source templates. Replace VexW= by VexW*
 759         where applicable.
 760         * i386-tbl.h: Re-generate.
 761
 762 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 763
 764         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 765         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 766         * i386-tbl.h: Re-generate.
 767
 768 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 771         * i386-tbl.h: Re-generate.
 772
 773 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 774
 775         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 776         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 777         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 778         VexW0 on SSE2AVX variants.
 779         (vmovq): Drop NoRex64 from XMM/XMM variants.
 780         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 781         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 782         applicable use VexW0.
 783         * i386-tbl.h: Re-generate.
 784
 785 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 786
 787         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 788         * i386-opc.h (Rex64): Delete.
 789         (struct i386_opcode_modifier): Remove rex64 field.
 790         * i386-opc.tbl (crc32): Drop Rex64.
 791         Replace Rex64 with Size64 everywhere else.
 792         * i386-tbl.h: Re-generate.
 793
 794 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-dis.c (OP_E_memory): Exclude recording of used address
 797         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 798         addressed memory operands for MPX insns.
 799
 800 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 801
 802         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 803         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 804         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 805         (ptwrite): Split into non-64-bit and 64-bit forms.
 806         * i386-tbl.h: Re-generate.
 807
 808 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 809
 810         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 811         template.
 812         * i386-tbl.h: Re-generate.
 813
 814 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 817         (prefix_table): Move vmmcall here. Add vmgexit.
 818         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 819         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 820         (cpu_flags): Add CpuSEV_ES entry.
 821         * i386-opc.h (CpuSEV_ES): New.
 822         (union i386_cpu_flags): Add cpusev_es field.
 823         * i386-opc.tbl (vmgexit): New.
 824         * i386-init.h, i386-tbl.h: Re-generate.
 825
 826 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 827
 828         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 829         with MnemonicSize.
 830         * i386-opc.h (IGNORESIZE): New.
 831         (DEFAULTSIZE): Likewise.
 832         (IgnoreSize): Removed.
 833         (DefaultSize): Likewise.
 834         (MnemonicSize): New.
 835         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 836         mnemonicsize.
 837         * i386-opc.tbl (IgnoreSize): New.
 838         (DefaultSize): Likewise.
 839         * i386-tbl.h: Regenerated.
 840
 841 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 842
 843         PR 25627
 844         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 845         instructions.
 846
 847 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 848
 849         PR gas/25622
 850         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 851         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 852         * i386-tbl.h: Regenerated.
 853
 854 2020-02-26  Alan Modra  <amodra@gmail.com>
 855
 856         * aarch64-asm.c: Indent labels correctly.
 857         * aarch64-dis.c: Likewise.
 858         * aarch64-gen.c: Likewise.
 859         * aarch64-opc.c: Likewise.
 860         * alpha-dis.c: Likewise.
 861         * i386-dis.c: Likewise.
 862         * nds32-asm.c: Likewise.
 863         * nfp-dis.c: Likewise.
 864         * visium-dis.c: Likewise.
 865
 866 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 867
 868         * arc-regs.h (int_vector_base): Make it available for all ARC
 869         CPUs.
 870
 871 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 872
 873         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 874         changed.
 875
 876 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 877
 878         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 879         c.mv/c.li if rs1 is zero.
 880
 881 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 882
 883         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 884         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 885         CPU_POPCNT_FLAGS.
 886         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 887         * i386-opc.h (CpuABM): Removed.
 888         (CpuPOPCNT): New.
 889         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 890         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 891         popcnt.  Remove CpuABM from lzcnt.
 892         * i386-init.h: Regenerated.
 893         * i386-tbl.h: Likewise.
 894
 895 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 896
 897         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 898         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 899         VexW1 instead of open-coding them.
 900         * i386-tbl.h: Re-generate.
 901
 902 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 903
 904         * i386-opc.tbl (AddrPrefixOpReg): Define.
 905         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 906         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 907         templates. Drop NoRex64.
 908         * i386-tbl.h: Re-generate.
 909
 910 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 911
 912         PR gas/6518
 913         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 914         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 915         into Intel syntax instance (with Unpsecified) and AT&T one
 916         (without).
 917         (vcvtneps2bf16): Likewise, along with folding the two so far
 918         separate ones.
 919         * i386-tbl.h: Re-generate.
 920
 921 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 924         CPU_ANY_SSE4A_FLAGS.
 925
 926 2020-02-17  Alan Modra  <amodra@gmail.com>
 927
 928         * i386-gen.c (cpu_flag_init): Correct last change.
 929
 930 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 931
 932         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 933         CPU_ANY_SSE4_FLAGS.
 934
 935 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 936
 937         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 938         (movzx): Likewise.
 939
 940 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 941
 942         PR gas/25438
 943         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 944         destination for Cpu64-only variant.
 945         (movzx): Fold patterns.
 946         * i386-tbl.h: Re-generate.
 947
 948 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 951         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 952         CPU_ANY_SSE4_FLAGS entry.
 953         * i386-init.h: Re-generate.
 954
 955 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 956
 957         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 958         with Unspecified, making the present one AT&T syntax only.
 959         * i386-tbl.h: Re-generate.
 960
 961 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 962
 963         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 964         * i386-tbl.h: Re-generate.
 965
 966 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 967
 968         PR gas/24546
 969         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 970         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 971         Amd64 and Intel64 templates.
 972         (call, jmp): Likewise for far indirect variants. Dro
 973         Unspecified.
 974         * i386-tbl.h: Re-generate.
 975
 976 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 979         * i386-opc.h (ShortForm): Delete.
 980         (struct i386_opcode_modifier): Remove shortform field.
 981         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 982         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 983         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 984         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 985         Drop ShortForm.
 986         * i386-tbl.h: Re-generate.
 987
 988 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 989
 990         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 991         fucompi): Drop ShortForm from operand-less templates.
 992         * i386-tbl.h: Re-generate.
 993
 994 2020-02-11  Alan Modra  <amodra@gmail.com>
 995
 996         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 997         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 998         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 999         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1000         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1001
1002 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1003
1004         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1005         (cde_opcodes): Add VCX* instructions.
1006
1007 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1008             Matthew Malcomson  <matthew.malcomson@arm.com>
1009
1010         * arm-dis.c (struct cdeopcode32): New.
1011         (CDE_OPCODE): New macro.
1012         (cde_opcodes): New disassembly table.
1013         (regnames): New option to table.
1014         (cde_coprocs): New global variable.
1015         (print_insn_cde): New
1016         (print_insn_thumb32): Use print_insn_cde.
1017         (parse_arm_disassembler_options): Parse coprocN args.
1018
1019 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1020
1021         PR gas/25516
1022         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1023         with ISA64.
1024         * i386-opc.h (AMD64): Removed.
1025         (Intel64): Likewose.
1026         (AMD64): New.
1027         (INTEL64): Likewise.
1028         (INTEL64ONLY): Likewise.
1029         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1030         * i386-opc.tbl (Amd64): New.
1031         (Intel64): Likewise.
1032         (Intel64Only): Likewise.
1033         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1034         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1035         * i386-tbl.h: Regenerated.
1036
1037 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1038
1039         PR 25469
1040         * z80-dis.c: Add support for GBZ80 opcodes.
1041
1042 2020-02-04  Alan Modra  <amodra@gmail.com>
1043
1044         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1045
1046 2020-02-03  Alan Modra  <amodra@gmail.com>
1047
1048         * m32c-ibld.c: Regenerate.
1049
1050 2020-02-01  Alan Modra  <amodra@gmail.com>
1051
1052         * frv-ibld.c: Regenerate.
1053
1054 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1057         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1058         (OP_E_memory): Replace xmm_mdq_mode case label by
1059         vex_scalar_w_dq_mode one.
1060         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1061
1062 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1063
1064         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1065         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1066         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1067         (intel_operand_size): Drop vex_w_dq_mode case label.
1068
1069 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1070
1071         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1072         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1073
1074 2020-01-30  Alan Modra  <amodra@gmail.com>
1075
1076         * m32c-ibld.c: Regenerate.
1077
1078 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1079
1080         * bpf-opc.c: Regenerate.
1081
1082 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1083
1084         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1085         (dis386): Use them to replace C2/C3 table entries.
1086         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1087         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1088         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1089         * i386-tbl.h: Re-generate.
1090
1091 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1092
1093         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1094         forms.
1095         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1096         DefaultSize.
1097         * i386-tbl.h: Re-generate.
1098
1099 2020-01-30  Alan Modra  <amodra@gmail.com>
1100
1101         * tic4x-dis.c (tic4x_dp): Make unsigned.
1102
1103 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1104             Jan Beulich  <jbeulich@suse.com>
1105
1106         PR binutils/25445
1107         * i386-dis.c (MOVSXD_Fixup): New function.
1108         (movsxd_mode): New enum.
1109         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1110         (intel_operand_size): Handle movsxd_mode.
1111         (OP_E_register): Likewise.
1112         (OP_G): Likewise.
1113         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1114         register on movsxd.  Add movsxd with 16-bit destination register
1115         for AMD64 and Intel64 ISAs.
1116         * i386-tbl.h: Regenerated.
1117
1118 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1119
1120         PR 25403
1121         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1122         * aarch64-asm-2.c: Regenerate
1123         * aarch64-dis-2.c: Likewise.
1124         * aarch64-opc-2.c: Likewise.
1125
1126 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1127
1128         * i386-opc.tbl (sysret): Drop DefaultSize.
1129         * i386-tbl.h: Re-generate.
1130
1131 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1132
1133         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1134         Dword.
1135         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1136         * i386-tbl.h: Re-generate.
1137
1138 2020-01-20  Nick Clifton  <nickc@redhat.com>
1139
1140         * po/de.po: Updated German translation.
1141         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1142         * po/uk.po: Updated Ukranian translation.
1143
1144 2020-01-20  Alan Modra  <amodra@gmail.com>
1145
1146         * hppa-dis.c (fput_const): Remove useless cast.
1147
1148 2020-01-20  Alan Modra  <amodra@gmail.com>
1149
1150         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1151
1152 2020-01-18  Nick Clifton  <nickc@redhat.com>
1153
1154         * configure: Regenerate.
1155         * po/opcodes.pot: Regenerate.
1156
1157 2020-01-18  Nick Clifton  <nickc@redhat.com>
1158
1159         Binutils 2.34 branch created.
1160
1161 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1162
1163         * opintl.h: Fix spelling error (seperate).
1164
1165 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1166
1167         * i386-opc.tbl: Add {vex} pseudo prefix.
1168         * i386-tbl.h: Regenerated.
1169
1170 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1171
1172         PR 25376
1173         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1174         (neon_opcodes): Likewise.
1175         (select_arm_features): Make sure we enable MVE bits when selecting
1176         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1177         any architecture.
1178
1179 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1180
1181         * i386-opc.tbl: Drop stale comment from XOP section.
1182
1183 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1186         (extractps): Add VexWIG to SSE2AVX forms.
1187         * i386-tbl.h: Re-generate.
1188
1189 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1190
1191         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1192         Size64 from and use VexW1 on SSE2AVX forms.
1193         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1194         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1195         * i386-tbl.h: Re-generate.
1196
1197 2020-01-15  Alan Modra  <amodra@gmail.com>
1198
1199         * tic4x-dis.c (tic4x_version): Make unsigned long.
1200         (optab, optab_special, registernames): New file scope vars.
1201         (tic4x_print_register): Set up registernames rather than
1202         malloc'd registertable.
1203         (tic4x_disassemble): Delete optable and optable_special.  Use
1204         optab and optab_special instead.  Throw away old optab,
1205         optab_special and registernames when info->mach changes.
1206
1207 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1208
1209         PR 25377
1210         * z80-dis.c (suffix): Use .db instruction to generate double
1211         prefix.
1212
1213 2020-01-14  Alan Modra  <amodra@gmail.com>
1214
1215         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1216         values to unsigned before shifting.
1217
1218 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1219
1220         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1221         flow instructions.
1222         (print_insn_thumb16, print_insn_thumb32): Likewise.
1223         (print_insn): Initialize the insn info.
1224         * i386-dis.c (print_insn): Initialize the insn info fields, and
1225         detect jumps.
1226
1227 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1228
1229         * arc-opc.c (C_NE): Make it required.
1230
1231 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1232
1233         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1234         reserved register name.
1235
1236 2020-01-13  Alan Modra  <amodra@gmail.com>
1237
1238         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1239         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1240
1241 2020-01-13  Alan Modra  <amodra@gmail.com>
1242
1243         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1244         result of wasm_read_leb128 in a uint64_t and check that bits
1245         are not lost when copying to other locals.  Use uint32_t for
1246         most locals.  Use PRId64 when printing int64_t.
1247
1248 2020-01-13  Alan Modra  <amodra@gmail.com>
1249
1250         * score-dis.c: Formatting.
1251         * score7-dis.c: Formatting.
1252
1253 2020-01-13  Alan Modra  <amodra@gmail.com>
1254
1255         * score-dis.c (print_insn_score48): Use unsigned variables for
1256         unsigned values.  Don't left shift negative values.
1257         (print_insn_score32): Likewise.
1258         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1259
1260 2020-01-13  Alan Modra  <amodra@gmail.com>
1261
1262         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1263
1264 2020-01-13  Alan Modra  <amodra@gmail.com>
1265
1266         * fr30-ibld.c: Regenerate.
1267
1268 2020-01-13  Alan Modra  <amodra@gmail.com>
1269
1270         * xgate-dis.c (print_insn): Don't left shift signed value.
1271         (ripBits): Formatting, use 1u.
1272
1273 2020-01-10  Alan Modra  <amodra@gmail.com>
1274
1275         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1276         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1277
1278 2020-01-10  Alan Modra  <amodra@gmail.com>
1279
1280         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1281         and XRREG value earlier to avoid a shift with negative exponent.
1282         * m10200-dis.c (disassemble): Similarly.
1283
1284 2020-01-09  Nick Clifton  <nickc@redhat.com>
1285
1286         PR 25224
1287         * z80-dis.c (ld_ii_ii): Use correct cast.
1288
1289 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1290
1291         PR 25224
1292         * z80-dis.c (ld_ii_ii): Use character constant when checking
1293         opcode byte value.
1294
1295 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1296
1297         * i386-dis.c (SEP_Fixup): New.
1298         (SEP): Define.
1299         (dis386_twobyte): Use it for sysenter/sysexit.
1300         (enum x86_64_isa): Change amd64 enumerator to value 1.
1301         (OP_J): Compare isa64 against intel64 instead of amd64.
1302         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1303         forms.
1304         * i386-tbl.h: Re-generate.
1305
1306 2020-01-08  Alan Modra  <amodra@gmail.com>
1307
1308         * z8k-dis.c: Include libiberty.h
1309         (instr_data_s): Make max_fetched unsigned.
1310         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1311         Don't exceed byte_info bounds.
1312         (output_instr): Make num_bytes unsigned.
1313         (unpack_instr): Likewise for nibl_count and loop.
1314         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1315         idx unsigned.
1316         * z8k-opc.h: Regenerate.
1317
1318 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1319
1320         * arc-tbl.h (llock): Use 'LLOCK' as class.
1321         (llockd): Likewise.
1322         (scond): Use 'SCOND' as class.
1323         (scondd): Likewise.
1324         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1325         (scondd): Likewise.
1326
1327 2020-01-06  Alan Modra  <amodra@gmail.com>
1328
1329         * m32c-ibld.c: Regenerate.
1330
1331 2020-01-06  Alan Modra  <amodra@gmail.com>
1332
1333         PR 25344
1334         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1335         Peek at next byte to prevent recursion on repeated prefix bytes.
1336         Ensure uninitialised "mybuf" is not accessed.
1337         (print_insn_z80): Don't zero n_fetch and n_used here,..
1338         (print_insn_z80_buf): ..do it here instead.
1339
1340 2020-01-04  Alan Modra  <amodra@gmail.com>
1341
1342         * m32r-ibld.c: Regenerate.
1343
1344 2020-01-04  Alan Modra  <amodra@gmail.com>
1345
1346         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1347
1348 2020-01-04  Alan Modra  <amodra@gmail.com>
1349
1350         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1351
1352 2020-01-04  Alan Modra  <amodra@gmail.com>
1353
1354         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1355
1356 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1357
1358         * aarch64-tbl.h (aarch64_opcode_table): Use
1359         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1360
1361 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1362
1363         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1364         forms of SUDOT and USDOT.
1365
1366 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1367
1368         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1369         uzip{1,2}.
1370         * opcodes/aarch64-dis-2.c: Re-generate.
1371
1372 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1373
1374         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1375         FMMLA encoding.
1376         * opcodes/aarch64-dis-2.c: Re-generate.
1377
1378 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1379
1380         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1381
1382 2020-01-01  Alan Modra  <amodra@gmail.com>
1383
1384         Update year range in copyright notice of all files.
1385
1386 For older changes see ChangeLog-2019
1387 \f
1388 Copyright (C) 2020 Free Software Foundation, Inc.
1389
1390 Copying and distribution of this file, with or without modification,
1391 are permitted in any medium without royalty provided the copyright
1392 notice and this notice are preserved.
1393
1394 Local Variables:
1395 mode: change-log
1396 left-margin: 8
1397 fill-column: 74
1398 version-control: never
1399 End: