1 2018-10-05 Richard Henderson <rth@twiddle.net>
3 * or1k-asm.c: Regenerate.
5 2018-10-03 Tamar Christina <tamar.christina@arm.com>
7 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
8 * aarch64-dis.c (print_operands): Refactor to take notes.
9 (print_verifier_notes): New.
10 (print_aarch64_insn): Apply constraint verifier.
11 (print_insn_aarch64_word): Update call to print_aarch64_insn.
12 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
14 2018-10-03 Tamar Christina <tamar.christina@arm.com>
16 * aarch64-opc.c (init_insn_block): New.
17 (verify_constraints, aarch64_is_destructive_by_operands): New.
18 * aarch64-opc.h (verify_constraints): New.
20 2018-10-03 Tamar Christina <tamar.christina@arm.com>
22 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
23 * aarch64-opc.c (verify_ldpsw): Update arguments.
25 2018-10-03 Tamar Christina <tamar.christina@arm.com>
27 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
28 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
30 2018-10-03 Tamar Christina <tamar.christina@arm.com>
32 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
33 * aarch64-dis.c (insn_sequence): New.
35 2018-10-03 Tamar Christina <tamar.christina@arm.com>
37 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
38 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
39 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
40 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
43 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
45 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
47 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
48 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
49 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
50 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
51 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
52 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
53 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
55 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
57 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
59 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
61 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
62 are used when extracting signed fields and converting them to
63 potentially 64-bit types.
65 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
67 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
68 * Makefile.in: Re-generate.
69 * aclocal.m4: Re-generate.
70 * configure: Re-generate.
71 * configure.ac: Remove check for -Wno-missing-field-initializers.
72 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
73 (csky_v2_opcodes): Likewise.
75 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
77 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
79 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
81 * nds32-asm.c (operand_fields): Remove the unused fields.
82 (nds32_opcodes): Remove the unused instructions.
83 * nds32-dis.c (nds32_ex9_info): Removed.
84 (nds32_parse_opcode): Updated.
85 (print_insn_nds32): Likewise.
86 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
87 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
88 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
89 build_opcode_hash_table): New functions.
90 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
91 nds32_opcode_table): New.
92 (hw_ktabs): Declare it to a pointer rather than an array.
93 (build_hash_table): Removed.
94 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
95 SYN_ROPT and upadte HW_GPR and HW_INT.
96 * nds32-dis.c (keywords): Remove const.
97 (match_field): New function.
98 (nds32_parse_opcode): Updated.
99 * disassemble.c (disassemble_init_for_target):
100 Add disassemble_init_nds32.
101 * nds32-dis.c (eum map_type): New.
102 (nds32_private_data): Likewise.
103 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
104 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
105 (print_insn_nds32): Updated.
106 * nds32-asm.c (parse_aext_reg): Add new parameter.
107 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
110 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
111 (operand_fields): Add new fields.
112 (nds32_opcodes): Add new instructions.
113 (keyword_aridxi_mx): New keyword.
114 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
116 (ALU2_1, ALU2_2, ALU2_3): New macros.
117 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
119 2018-09-17 Kito Cheng <kito@andestech.com>
121 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
123 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
126 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
127 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
128 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
129 (EVEX_LEN_0F7E_P_1): Likewise.
130 (EVEX_LEN_0F7E_P_2): Likewise.
131 (EVEX_LEN_0FD6_P_2): Likewise.
132 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
133 (EVEX_LEN_TABLE): Likewise.
134 (EVEX_LEN_0F6E_P_2): New enum.
135 (EVEX_LEN_0F7E_P_1): Likewise.
136 (EVEX_LEN_0F7E_P_2): Likewise.
137 (EVEX_LEN_0FD6_P_2): Likewise.
138 (evex_len_table): New.
139 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
140 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
141 * i386-tbl.h: Regenerated.
143 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
146 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
147 VEX_LEN_0F7E_P_2 entries.
148 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
149 * i386-tbl.h: Regenerated.
151 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
153 * i386-dis.c (VZERO_Fixup): Removed.
155 (VEX_LEN_0F10_P_1): Likewise.
156 (VEX_LEN_0F10_P_3): Likewise.
157 (VEX_LEN_0F11_P_1): Likewise.
158 (VEX_LEN_0F11_P_3): Likewise.
159 (VEX_LEN_0F2E_P_0): Likewise.
160 (VEX_LEN_0F2E_P_2): Likewise.
161 (VEX_LEN_0F2F_P_0): Likewise.
162 (VEX_LEN_0F2F_P_2): Likewise.
163 (VEX_LEN_0F51_P_1): Likewise.
164 (VEX_LEN_0F51_P_3): Likewise.
165 (VEX_LEN_0F52_P_1): Likewise.
166 (VEX_LEN_0F53_P_1): Likewise.
167 (VEX_LEN_0F58_P_1): Likewise.
168 (VEX_LEN_0F58_P_3): Likewise.
169 (VEX_LEN_0F59_P_1): Likewise.
170 (VEX_LEN_0F59_P_3): Likewise.
171 (VEX_LEN_0F5A_P_1): Likewise.
172 (VEX_LEN_0F5A_P_3): Likewise.
173 (VEX_LEN_0F5C_P_1): Likewise.
174 (VEX_LEN_0F5C_P_3): Likewise.
175 (VEX_LEN_0F5D_P_1): Likewise.
176 (VEX_LEN_0F5D_P_3): Likewise.
177 (VEX_LEN_0F5E_P_1): Likewise.
178 (VEX_LEN_0F5E_P_3): Likewise.
179 (VEX_LEN_0F5F_P_1): Likewise.
180 (VEX_LEN_0F5F_P_3): Likewise.
181 (VEX_LEN_0FC2_P_1): Likewise.
182 (VEX_LEN_0FC2_P_3): Likewise.
183 (VEX_LEN_0F3A0A_P_2): Likewise.
184 (VEX_LEN_0F3A0B_P_2): Likewise.
185 (VEX_W_0F10_P_0): Likewise.
186 (VEX_W_0F10_P_1): Likewise.
187 (VEX_W_0F10_P_2): Likewise.
188 (VEX_W_0F10_P_3): Likewise.
189 (VEX_W_0F11_P_0): Likewise.
190 (VEX_W_0F11_P_1): Likewise.
191 (VEX_W_0F11_P_2): Likewise.
192 (VEX_W_0F11_P_3): Likewise.
193 (VEX_W_0F12_P_0_M_0): Likewise.
194 (VEX_W_0F12_P_0_M_1): Likewise.
195 (VEX_W_0F12_P_1): Likewise.
196 (VEX_W_0F12_P_2): Likewise.
197 (VEX_W_0F12_P_3): Likewise.
198 (VEX_W_0F13_M_0): Likewise.
199 (VEX_W_0F14): Likewise.
200 (VEX_W_0F15): Likewise.
201 (VEX_W_0F16_P_0_M_0): Likewise.
202 (VEX_W_0F16_P_0_M_1): Likewise.
203 (VEX_W_0F16_P_1): Likewise.
204 (VEX_W_0F16_P_2): Likewise.
205 (VEX_W_0F17_M_0): Likewise.
206 (VEX_W_0F28): Likewise.
207 (VEX_W_0F29): Likewise.
208 (VEX_W_0F2B_M_0): Likewise.
209 (VEX_W_0F2E_P_0): Likewise.
210 (VEX_W_0F2E_P_2): Likewise.
211 (VEX_W_0F2F_P_0): Likewise.
212 (VEX_W_0F2F_P_2): Likewise.
213 (VEX_W_0F50_M_0): Likewise.
214 (VEX_W_0F51_P_0): Likewise.
215 (VEX_W_0F51_P_1): Likewise.
216 (VEX_W_0F51_P_2): Likewise.
217 (VEX_W_0F51_P_3): Likewise.
218 (VEX_W_0F52_P_0): Likewise.
219 (VEX_W_0F52_P_1): Likewise.
220 (VEX_W_0F53_P_0): Likewise.
221 (VEX_W_0F53_P_1): Likewise.
222 (VEX_W_0F58_P_0): Likewise.
223 (VEX_W_0F58_P_1): Likewise.
224 (VEX_W_0F58_P_2): Likewise.
225 (VEX_W_0F58_P_3): Likewise.
226 (VEX_W_0F59_P_0): Likewise.
227 (VEX_W_0F59_P_1): Likewise.
228 (VEX_W_0F59_P_2): Likewise.
229 (VEX_W_0F59_P_3): Likewise.
230 (VEX_W_0F5A_P_0): Likewise.
231 (VEX_W_0F5A_P_1): Likewise.
232 (VEX_W_0F5A_P_3): Likewise.
233 (VEX_W_0F5B_P_0): Likewise.
234 (VEX_W_0F5B_P_1): Likewise.
235 (VEX_W_0F5B_P_2): Likewise.
236 (VEX_W_0F5C_P_0): Likewise.
237 (VEX_W_0F5C_P_1): Likewise.
238 (VEX_W_0F5C_P_2): Likewise.
239 (VEX_W_0F5C_P_3): Likewise.
240 (VEX_W_0F5D_P_0): Likewise.
241 (VEX_W_0F5D_P_1): Likewise.
242 (VEX_W_0F5D_P_2): Likewise.
243 (VEX_W_0F5D_P_3): Likewise.
244 (VEX_W_0F5E_P_0): Likewise.
245 (VEX_W_0F5E_P_1): Likewise.
246 (VEX_W_0F5E_P_2): Likewise.
247 (VEX_W_0F5E_P_3): Likewise.
248 (VEX_W_0F5F_P_0): Likewise.
249 (VEX_W_0F5F_P_1): Likewise.
250 (VEX_W_0F5F_P_2): Likewise.
251 (VEX_W_0F5F_P_3): Likewise.
252 (VEX_W_0F60_P_2): Likewise.
253 (VEX_W_0F61_P_2): Likewise.
254 (VEX_W_0F62_P_2): Likewise.
255 (VEX_W_0F63_P_2): Likewise.
256 (VEX_W_0F64_P_2): Likewise.
257 (VEX_W_0F65_P_2): Likewise.
258 (VEX_W_0F66_P_2): Likewise.
259 (VEX_W_0F67_P_2): Likewise.
260 (VEX_W_0F68_P_2): Likewise.
261 (VEX_W_0F69_P_2): Likewise.
262 (VEX_W_0F6A_P_2): Likewise.
263 (VEX_W_0F6B_P_2): Likewise.
264 (VEX_W_0F6C_P_2): Likewise.
265 (VEX_W_0F6D_P_2): Likewise.
266 (VEX_W_0F6F_P_1): Likewise.
267 (VEX_W_0F6F_P_2): Likewise.
268 (VEX_W_0F70_P_1): Likewise.
269 (VEX_W_0F70_P_2): Likewise.
270 (VEX_W_0F70_P_3): Likewise.
271 (VEX_W_0F71_R_2_P_2): Likewise.
272 (VEX_W_0F71_R_4_P_2): Likewise.
273 (VEX_W_0F71_R_6_P_2): Likewise.
274 (VEX_W_0F72_R_2_P_2): Likewise.
275 (VEX_W_0F72_R_4_P_2): Likewise.
276 (VEX_W_0F72_R_6_P_2): Likewise.
277 (VEX_W_0F73_R_2_P_2): Likewise.
278 (VEX_W_0F73_R_3_P_2): Likewise.
279 (VEX_W_0F73_R_6_P_2): Likewise.
280 (VEX_W_0F73_R_7_P_2): Likewise.
281 (VEX_W_0F74_P_2): Likewise.
282 (VEX_W_0F75_P_2): Likewise.
283 (VEX_W_0F76_P_2): Likewise.
284 (VEX_W_0F77_P_0): Likewise.
285 (VEX_W_0F7C_P_2): Likewise.
286 (VEX_W_0F7C_P_3): Likewise.
287 (VEX_W_0F7D_P_2): Likewise.
288 (VEX_W_0F7D_P_3): Likewise.
289 (VEX_W_0F7E_P_1): Likewise.
290 (VEX_W_0F7F_P_1): Likewise.
291 (VEX_W_0F7F_P_2): Likewise.
292 (VEX_W_0FAE_R_2_M_0): Likewise.
293 (VEX_W_0FAE_R_3_M_0): Likewise.
294 (VEX_W_0FC2_P_0): Likewise.
295 (VEX_W_0FC2_P_1): Likewise.
296 (VEX_W_0FC2_P_2): Likewise.
297 (VEX_W_0FC2_P_3): Likewise.
298 (VEX_W_0FD0_P_2): Likewise.
299 (VEX_W_0FD0_P_3): Likewise.
300 (VEX_W_0FD1_P_2): Likewise.
301 (VEX_W_0FD2_P_2): Likewise.
302 (VEX_W_0FD3_P_2): Likewise.
303 (VEX_W_0FD4_P_2): Likewise.
304 (VEX_W_0FD5_P_2): Likewise.
305 (VEX_W_0FD6_P_2): Likewise.
306 (VEX_W_0FD7_P_2_M_1): Likewise.
307 (VEX_W_0FD8_P_2): Likewise.
308 (VEX_W_0FD9_P_2): Likewise.
309 (VEX_W_0FDA_P_2): Likewise.
310 (VEX_W_0FDB_P_2): Likewise.
311 (VEX_W_0FDC_P_2): Likewise.
312 (VEX_W_0FDD_P_2): Likewise.
313 (VEX_W_0FDE_P_2): Likewise.
314 (VEX_W_0FDF_P_2): Likewise.
315 (VEX_W_0FE0_P_2): Likewise.
316 (VEX_W_0FE1_P_2): Likewise.
317 (VEX_W_0FE2_P_2): Likewise.
318 (VEX_W_0FE3_P_2): Likewise.
319 (VEX_W_0FE4_P_2): Likewise.
320 (VEX_W_0FE5_P_2): Likewise.
321 (VEX_W_0FE6_P_1): Likewise.
322 (VEX_W_0FE6_P_2): Likewise.
323 (VEX_W_0FE6_P_3): Likewise.
324 (VEX_W_0FE7_P_2_M_0): Likewise.
325 (VEX_W_0FE8_P_2): Likewise.
326 (VEX_W_0FE9_P_2): Likewise.
327 (VEX_W_0FEA_P_2): Likewise.
328 (VEX_W_0FEB_P_2): Likewise.
329 (VEX_W_0FEC_P_2): Likewise.
330 (VEX_W_0FED_P_2): Likewise.
331 (VEX_W_0FEE_P_2): Likewise.
332 (VEX_W_0FEF_P_2): Likewise.
333 (VEX_W_0FF0_P_3_M_0): Likewise.
334 (VEX_W_0FF1_P_2): Likewise.
335 (VEX_W_0FF2_P_2): Likewise.
336 (VEX_W_0FF3_P_2): Likewise.
337 (VEX_W_0FF4_P_2): Likewise.
338 (VEX_W_0FF5_P_2): Likewise.
339 (VEX_W_0FF6_P_2): Likewise.
340 (VEX_W_0FF7_P_2): Likewise.
341 (VEX_W_0FF8_P_2): Likewise.
342 (VEX_W_0FF9_P_2): Likewise.
343 (VEX_W_0FFA_P_2): Likewise.
344 (VEX_W_0FFB_P_2): Likewise.
345 (VEX_W_0FFC_P_2): Likewise.
346 (VEX_W_0FFD_P_2): Likewise.
347 (VEX_W_0FFE_P_2): Likewise.
348 (VEX_W_0F3800_P_2): Likewise.
349 (VEX_W_0F3801_P_2): Likewise.
350 (VEX_W_0F3802_P_2): Likewise.
351 (VEX_W_0F3803_P_2): Likewise.
352 (VEX_W_0F3804_P_2): Likewise.
353 (VEX_W_0F3805_P_2): Likewise.
354 (VEX_W_0F3806_P_2): Likewise.
355 (VEX_W_0F3807_P_2): Likewise.
356 (VEX_W_0F3808_P_2): Likewise.
357 (VEX_W_0F3809_P_2): Likewise.
358 (VEX_W_0F380A_P_2): Likewise.
359 (VEX_W_0F380B_P_2): Likewise.
360 (VEX_W_0F3817_P_2): Likewise.
361 (VEX_W_0F381C_P_2): Likewise.
362 (VEX_W_0F381D_P_2): Likewise.
363 (VEX_W_0F381E_P_2): Likewise.
364 (VEX_W_0F3820_P_2): Likewise.
365 (VEX_W_0F3821_P_2): Likewise.
366 (VEX_W_0F3822_P_2): Likewise.
367 (VEX_W_0F3823_P_2): Likewise.
368 (VEX_W_0F3824_P_2): Likewise.
369 (VEX_W_0F3825_P_2): Likewise.
370 (VEX_W_0F3828_P_2): Likewise.
371 (VEX_W_0F3829_P_2): Likewise.
372 (VEX_W_0F382A_P_2_M_0): Likewise.
373 (VEX_W_0F382B_P_2): Likewise.
374 (VEX_W_0F3830_P_2): Likewise.
375 (VEX_W_0F3831_P_2): Likewise.
376 (VEX_W_0F3832_P_2): Likewise.
377 (VEX_W_0F3833_P_2): Likewise.
378 (VEX_W_0F3834_P_2): Likewise.
379 (VEX_W_0F3835_P_2): Likewise.
380 (VEX_W_0F3837_P_2): Likewise.
381 (VEX_W_0F3838_P_2): Likewise.
382 (VEX_W_0F3839_P_2): Likewise.
383 (VEX_W_0F383A_P_2): Likewise.
384 (VEX_W_0F383B_P_2): Likewise.
385 (VEX_W_0F383C_P_2): Likewise.
386 (VEX_W_0F383D_P_2): Likewise.
387 (VEX_W_0F383E_P_2): Likewise.
388 (VEX_W_0F383F_P_2): Likewise.
389 (VEX_W_0F3840_P_2): Likewise.
390 (VEX_W_0F3841_P_2): Likewise.
391 (VEX_W_0F38DB_P_2): Likewise.
392 (VEX_W_0F3A08_P_2): Likewise.
393 (VEX_W_0F3A09_P_2): Likewise.
394 (VEX_W_0F3A0A_P_2): Likewise.
395 (VEX_W_0F3A0B_P_2): Likewise.
396 (VEX_W_0F3A0C_P_2): Likewise.
397 (VEX_W_0F3A0D_P_2): Likewise.
398 (VEX_W_0F3A0E_P_2): Likewise.
399 (VEX_W_0F3A0F_P_2): Likewise.
400 (VEX_W_0F3A21_P_2): Likewise.
401 (VEX_W_0F3A40_P_2): Likewise.
402 (VEX_W_0F3A41_P_2): Likewise.
403 (VEX_W_0F3A42_P_2): Likewise.
404 (VEX_W_0F3A62_P_2): Likewise.
405 (VEX_W_0F3A63_P_2): Likewise.
406 (VEX_W_0F3ADF_P_2): Likewise.
407 (VEX_LEN_0F77_P_0): New.
408 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
409 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
410 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
411 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
412 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
413 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
414 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
415 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
416 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
417 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
418 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
419 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
420 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
421 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
422 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
423 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
424 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
425 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
426 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
427 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
428 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
429 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
430 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
431 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
432 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
433 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
434 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
435 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
436 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
437 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
438 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
439 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
440 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
441 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
442 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
443 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
444 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
445 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
446 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
447 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
448 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
449 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
450 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
451 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
452 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
453 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
454 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
455 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
456 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
457 (vex_table): Update VEX 0F28 and 0F29 entries.
458 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
459 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
460 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
461 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
462 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
463 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
464 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
465 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
466 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
467 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
468 VEX_LEN_0F3A0B_P_2 entries.
469 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
470 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
471 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
472 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
473 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
474 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
475 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
476 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
477 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
478 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
479 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
480 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
481 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
482 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
483 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
484 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
485 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
486 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
487 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
488 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
489 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
490 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
491 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
492 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
493 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
494 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
495 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
496 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
497 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
498 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
499 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
500 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
501 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
502 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
503 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
504 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
505 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
506 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
507 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
508 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
509 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
510 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
511 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
512 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
513 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
514 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
515 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
516 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
517 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
518 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
519 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
520 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
521 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
522 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
523 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
524 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
525 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
526 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
527 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
528 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
529 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
530 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
531 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
532 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
533 VEX_W_0F3ADF_P_2 entries.
534 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
535 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
536 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
538 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
540 * i386-opc.tbl (VexWIG): New.
541 Replace VexW=3 with VexWIG.
543 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
545 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
546 * i386-tbl.h: Regenerated.
548 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
551 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
552 VEX_LEN_0FD6_P_2 entries.
553 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
554 * i386-tbl.h: Regenerated.
556 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
559 * i386-opc.h (VEXWIG): New.
560 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
561 * i386-tbl.h: Regenerated.
563 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
566 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
567 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
568 * i386-dis.c (EXxEVexR64): New.
569 (evex_rounding_64_mode): Likewise.
570 (OP_Rounding): Handle evex_rounding_64_mode.
572 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
575 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
576 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
577 * i386-dis.c (Edqa): New.
578 (dqa_mode): Likewise.
579 (intel_operand_size): Handle dqa_mode as m_mode.
580 (OP_E_register): Handle dqa_mode as dq_mode.
581 (OP_E_memory): Set shift for dqa_mode based on address_mode.
583 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
585 * i386-dis.c (OP_E_memory): Reformat.
587 2018-09-14 Jan Beulich <jbeulich@suse.com>
589 * i386-opc.tbl (crc32): Fold byte and word forms.
590 * i386-tbl.h: Re-generate.
592 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
594 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
595 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
596 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
597 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
598 * i386-tbl.h: Regenerated.
600 2018-09-13 Jan Beulich <jbeulich@suse.com>
602 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
604 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
605 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
606 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
607 * i386-tbl.h: Re-generate.
609 2018-09-13 Jan Beulich <jbeulich@suse.com>
611 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
613 * i386-tbl.h: Re-generate.
615 2018-09-13 Jan Beulich <jbeulich@suse.com>
617 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
619 * i386-tbl.h: Re-generate.
621 2018-09-13 Jan Beulich <jbeulich@suse.com>
623 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
625 * i386-tbl.h: Re-generate.
627 2018-09-13 Jan Beulich <jbeulich@suse.com>
629 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
631 * i386-tbl.h: Re-generate.
633 2018-09-13 Jan Beulich <jbeulich@suse.com>
635 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
637 * i386-tbl.h: Re-generate.
639 2018-09-13 Jan Beulich <jbeulich@suse.com>
641 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
643 * i386-tbl.h: Re-generate.
645 2018-09-13 Jan Beulich <jbeulich@suse.com>
647 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
648 * i386-tbl.h: Re-generate.
650 2018-09-13 Jan Beulich <jbeulich@suse.com>
652 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
653 * i386-tbl.h: Re-generate.
655 2018-09-13 Jan Beulich <jbeulich@suse.com>
657 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
659 * i386-tbl.h: Re-generate.
661 2018-09-13 Jan Beulich <jbeulich@suse.com>
663 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
665 * i386-tbl.h: Re-generate.
667 2018-09-13 Jan Beulich <jbeulich@suse.com>
669 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
670 * i386-tbl.h: Re-generate.
672 2018-09-13 Jan Beulich <jbeulich@suse.com>
674 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
675 * i386-tbl.h: Re-generate.
677 2018-09-13 Jan Beulich <jbeulich@suse.com>
679 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
680 * i386-tbl.h: Re-generate.
682 2018-09-13 Jan Beulich <jbeulich@suse.com>
684 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
686 * i386-tbl.h: Re-generate.
688 2018-09-13 Jan Beulich <jbeulich@suse.com>
690 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
692 * i386-tbl.h: Re-generate.
694 2018-09-13 Jan Beulich <jbeulich@suse.com>
696 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
698 * i386-tbl.h: Re-generate.
700 2018-09-13 Jan Beulich <jbeulich@suse.com>
702 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
703 * i386-tbl.h: Re-generate.
705 2018-09-13 Jan Beulich <jbeulich@suse.com>
707 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
708 * i386-tbl.h: Re-generate.
710 2018-09-13 Jan Beulich <jbeulich@suse.com>
712 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
713 * i386-tbl.h: Re-generate.
715 2018-09-13 Jan Beulich <jbeulich@suse.com>
717 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
718 (vpbroadcastw, rdpid): Drop NoRex64.
719 * i386-tbl.h: Re-generate.
721 2018-09-13 Jan Beulich <jbeulich@suse.com>
723 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
724 store templates, adding D.
725 * i386-tbl.h: Re-generate.
727 2018-09-13 Jan Beulich <jbeulich@suse.com>
729 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
730 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
731 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
732 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
733 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
734 Fold load and store templates where possible, adding D. Drop
735 IgnoreSize where it was pointlessly present. Drop redundant
737 * i386-tbl.h: Re-generate.
739 2018-09-13 Jan Beulich <jbeulich@suse.com>
741 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
742 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
743 (intel_operand_size): Handle v_bndmk_mode.
744 (OP_E_memory): Likewise. Produce (bad) when also riprel.
746 2018-09-08 John Darrington <john@darrington.wattle.id.au>
748 * disassemble.c (ARCH_s12z): Define if ARCH_all.
750 2018-08-31 Kito Cheng <kito@andestech.com>
752 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
753 compressed floating point instructions.
755 2018-08-30 Kito Cheng <kito@andestech.com>
757 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
758 riscv_opcode.xlen_requirement.
759 * riscv-opc.c (riscv_opcodes): Update for struct change.
761 2018-08-29 Martin Aberg <maberg@gaisler.com>
763 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
764 psr (PWRPSR) instruction.
766 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
768 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
770 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
772 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
774 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
776 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
777 loongson3a as an alias of gs464 for compatibility.
778 * mips-opc.c (mips_opcodes): Change Comments.
780 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
782 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
784 (print_mips_disassembler_options): Document -M loongson-ext.
785 * mips-opc.c (LEXT2): New macro.
786 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
788 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
790 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
792 (parse_mips_ase_option): Handle -M loongson-ext option.
793 (print_mips_disassembler_options): Document -M loongson-ext.
794 * mips-opc.c (IL3A): Delete.
795 * mips-opc.c (LEXT): New macro.
796 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
799 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
801 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
803 (parse_mips_ase_option): Handle -M loongson-cam option.
804 (print_mips_disassembler_options): Document -M loongson-cam.
805 * mips-opc.c (LCAM): New macro.
806 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
809 2018-08-21 Alan Modra <amodra@gmail.com>
811 * ppc-dis.c (operand_value_powerpc): Init "invalid".
812 (skip_optional_operands): Count optional operands, and update
813 ppc_optional_operand_value call.
814 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
815 (extract_vlensi): Likewise.
816 (extract_fxm): Return default value for missing optional operand.
817 (extract_ls, extract_raq, extract_tbr): Likewise.
818 (insert_sxl, extract_sxl): New functions.
819 (insert_esync, extract_esync): Remove Power9 handling and simplify.
820 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
821 flag and extra entry.
822 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
825 2018-08-20 Alan Modra <amodra@gmail.com>
827 * sh-opc.h (MASK): Simplify.
829 2018-08-18 John Darrington <john@darrington.wattle.id.au>
831 * s12z-dis.c (bm_decode): Deal with cases where the mode is
832 BM_RESERVED0 or BM_RESERVED1
833 (bm_rel_decode, bm_n_bytes): Ditto.
835 2018-08-18 John Darrington <john@darrington.wattle.id.au>
839 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
841 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
842 address with the addr32 prefix and without base nor index
845 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
847 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
848 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
849 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
850 (cpu_flags): Add CpuCMOV and CpuFXSR.
851 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
852 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
853 * i386-init.h: Regenerated.
854 * i386-tbl.h: Likewise.
856 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
858 * arc-regs.h: Update auxiliary registers.
860 2018-08-06 Jan Beulich <jbeulich@suse.com>
862 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
863 (RegIP, RegIZ): Define.
864 * i386-reg.tbl: Adjust comments.
865 (rip): Use Qword instead of BaseIndex. Use RegIP.
866 (eip): Use Dword instead of BaseIndex. Use RegIP.
867 (riz): Add Qword. Use RegIZ.
868 (eiz): Add Dword. Use RegIZ.
869 * i386-tbl.h: Re-generate.
871 2018-08-03 Jan Beulich <jbeulich@suse.com>
873 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
874 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
875 vpmovzxdq, vpmovzxwd): Remove NoRex64.
876 * i386-tbl.h: Re-generate.
878 2018-08-03 Jan Beulich <jbeulich@suse.com>
880 * i386-gen.c (operand_types): Remove Mem field.
881 * i386-opc.h (union i386_operand_type): Remove mem field.
882 * i386-init.h, i386-tbl.h: Re-generate.
884 2018-08-01 Alan Modra <amodra@gmail.com>
886 * po/POTFILES.in: Regenerate.
888 2018-07-31 Nick Clifton <nickc@redhat.com>
890 * po/sv.po: Updated Swedish translation.
892 2018-07-31 Jan Beulich <jbeulich@suse.com>
894 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
895 * i386-init.h, i386-tbl.h: Re-generate.
897 2018-07-31 Jan Beulich <jbeulich@suse.com>
899 * i386-opc.h (ZEROING_MASKING) Rename to ...
900 (DYNAMIC_MASKING): ... this. Adjust comment.
901 * i386-opc.tbl (MaskingMorZ): Define.
902 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
903 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
904 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
905 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
906 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
907 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
908 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
909 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
910 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
912 2018-07-31 Jan Beulich <jbeulich@suse.com>
914 * i386-opc.tbl: Use element rather than vector size for AVX512*
915 scatter/gather insns.
916 * i386-tbl.h: Re-generate.
918 2018-07-31 Jan Beulich <jbeulich@suse.com>
920 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
921 (cpu_flags): Drop CpuVREX.
922 * i386-opc.h (CpuVREX): Delete.
923 (union i386_cpu_flags): Remove cpuvrex.
924 * i386-init.h, i386-tbl.h: Re-generate.
926 2018-07-30 Jim Wilson <jimw@sifive.com>
928 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
930 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
932 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
934 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
935 * Makefile.in: Regenerated.
936 * configure.ac: Add C-SKY.
937 * configure: Regenerated.
938 * csky-dis.c: New file.
939 * csky-opc.h: New file.
940 * disassemble.c (ARCH_csky): Define.
941 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
942 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
944 2018-07-27 Alan Modra <amodra@gmail.com>
946 * ppc-opc.c (insert_sprbat): Correct function parameter and
948 (extract_sprbat): Likewise, variable too.
950 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
951 Alan Modra <amodra@gmail.com>
953 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
954 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
955 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
956 support disjointed BAT.
957 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
958 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
959 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
961 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
962 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
964 * i386-gen.c (adjust_broadcast_modifier): New function.
965 (process_i386_opcode_modifier): Add an argument for operands.
966 Adjust the Broadcast value based on operands.
967 (output_i386_opcode): Pass operand_types to
968 process_i386_opcode_modifier.
969 (process_i386_opcodes): Pass NULL as operands to
970 process_i386_opcode_modifier.
971 * i386-opc.h (BYTE_BROADCAST): New.
972 (WORD_BROADCAST): Likewise.
973 (DWORD_BROADCAST): Likewise.
974 (QWORD_BROADCAST): Likewise.
975 (i386_opcode_modifier): Expand broadcast to 3 bits.
976 * i386-tbl.h: Regenerated.
978 2018-07-24 Alan Modra <amodra@gmail.com>
981 * or1k-desc.h: Regenerate.
983 2018-07-24 Jan Beulich <jbeulich@suse.com>
985 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
986 vcvtusi2ss, and vcvtusi2sd.
987 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
988 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
989 * i386-tbl.h: Re-generate.
991 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
993 * arc-opc.c (extract_w6): Fix extending the sign.
995 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
997 * arc-tbl.h (vewt): Allow it for ARC EM family.
999 2018-07-23 Alan Modra <amodra@gmail.com>
1002 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1003 opcode variants for mtspr/mfspr encodings.
1005 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1006 Maciej W. Rozycki <macro@mips.com>
1008 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1009 loongson3a descriptors.
1010 (parse_mips_ase_option): Handle -M loongson-mmi option.
1011 (print_mips_disassembler_options): Document -M loongson-mmi.
1012 * mips-opc.c (LMMI): New macro.
1013 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1016 2018-07-19 Jan Beulich <jbeulich@suse.com>
1018 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1019 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1020 IgnoreSize and [XYZ]MMword where applicable.
1021 * i386-tbl.h: Re-generate.
1023 2018-07-19 Jan Beulich <jbeulich@suse.com>
1025 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1026 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1027 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1028 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1029 * i386-tbl.h: Re-generate.
1031 2018-07-19 Jan Beulich <jbeulich@suse.com>
1033 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1034 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1035 VPCLMULQDQ templates into their respective AVX512VL counterparts
1036 where possible, using Disp8ShiftVL and CheckRegSize instead of
1037 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1038 * i386-tbl.h: Re-generate.
1040 2018-07-19 Jan Beulich <jbeulich@suse.com>
1042 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1043 AVX512VL counterparts where possible, using Disp8ShiftVL and
1044 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1045 IgnoreSize) as appropriate.
1046 * i386-tbl.h: Re-generate.
1048 2018-07-19 Jan Beulich <jbeulich@suse.com>
1050 * i386-opc.tbl: Fold AVX512BW templates into their respective
1051 AVX512VL counterparts where possible, using Disp8ShiftVL and
1052 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1053 IgnoreSize) as appropriate.
1054 * i386-tbl.h: Re-generate.
1056 2018-07-19 Jan Beulich <jbeulich@suse.com>
1058 * i386-opc.tbl: Fold AVX512CD templates into their respective
1059 AVX512VL counterparts where possible, using Disp8ShiftVL and
1060 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1061 IgnoreSize) as appropriate.
1062 * i386-tbl.h: Re-generate.
1064 2018-07-19 Jan Beulich <jbeulich@suse.com>
1066 * i386-opc.h (DISP8_SHIFT_VL): New.
1067 * i386-opc.tbl (Disp8ShiftVL): Define.
1068 (various): Fold AVX512VL templates into their respective
1069 AVX512F counterparts where possible, using Disp8ShiftVL and
1070 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1071 IgnoreSize) as appropriate.
1072 * i386-tbl.h: Re-generate.
1074 2018-07-19 Jan Beulich <jbeulich@suse.com>
1076 * Makefile.am: Change dependencies and rule for
1077 $(srcdir)/i386-init.h.
1078 * Makefile.in: Re-generate.
1079 * i386-gen.c (process_i386_opcodes): New local variable
1080 "marker". Drop opening of input file. Recognize marker and line
1082 * i386-opc.tbl (OPCODE_I386_H): Define.
1083 (i386-opc.h): Include it.
1086 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1089 * i386-opc.h (Byte): Update comments.
1095 (Xmmword): Likewise.
1096 (Ymmword): Likewise.
1097 (Zmmword): Likewise.
1098 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1100 * i386-tbl.h: Regenerated.
1102 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1104 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1105 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1106 * aarch64-asm-2.c: Regenerate.
1107 * aarch64-dis-2.c: Regenerate.
1108 * aarch64-opc-2.c: Regenerate.
1110 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1113 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1114 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1115 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1116 sqdmulh, sqrdmulh): Use Em16.
1118 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1120 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1121 csdb together with them.
1122 (thumb32_opcodes): Likewise.
1124 2018-07-11 Jan Beulich <jbeulich@suse.com>
1126 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1127 requiring 32-bit registers as operands 2 and 3. Improve
1129 (mwait, mwaitx): Fold templates. Improve comments.
1130 OPERAND_TYPE_INOUTPORTREG.
1131 * i386-tbl.h: Re-generate.
1133 2018-07-11 Jan Beulich <jbeulich@suse.com>
1135 * i386-gen.c (operand_type_init): Remove
1136 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1137 OPERAND_TYPE_INOUTPORTREG.
1138 * i386-init.h: Re-generate.
1140 2018-07-11 Jan Beulich <jbeulich@suse.com>
1142 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1143 (wrssq, wrussq): Add Qword.
1144 * i386-tbl.h: Re-generate.
1146 2018-07-11 Jan Beulich <jbeulich@suse.com>
1148 * i386-opc.h: Rename OTMax to OTNum.
1149 (OTNumOfUints): Adjust calculation.
1150 (OTUnused): Directly alias to OTNum.
1152 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1154 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1156 (lea_reg_xys): Likewise.
1157 (print_insn_loop_primitive): Rename `reg' local variable to
1160 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1163 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1165 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1168 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1169 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1171 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1174 * mips-dis.c (mips_option_arg_t): New enumeration.
1175 (mips_options): New variable.
1176 (disassembler_options_mips): New function.
1177 (print_mips_disassembler_options): Reimplement in terms of
1178 `disassembler_options_mips'.
1179 * arm-dis.c (disassembler_options_arm): Adapt to using the
1180 `disasm_options_and_args_t' structure.
1181 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1182 * s390-dis.c (disassembler_options_s390): Likewise.
1184 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1186 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1188 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1189 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1190 * testsuite/ld-arm/tls-longplt.d: Likewise.
1192 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1195 * aarch64-asm-2.c: Regenerate.
1196 * aarch64-dis-2.c: Likewise.
1197 * aarch64-opc-2.c: Likewise.
1198 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1199 * aarch64-opc.c (operand_general_constraint_met_p,
1200 aarch64_print_operand): Likewise.
1201 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1202 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1204 (AARCH64_OPERANDS): Add Em2.
1206 2018-06-26 Nick Clifton <nickc@redhat.com>
1208 * po/uk.po: Updated Ukranian translation.
1209 * po/de.po: Updated German translation.
1210 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1212 2018-06-26 Nick Clifton <nickc@redhat.com>
1214 * nfp-dis.c: Fix spelling mistake.
1216 2018-06-24 Nick Clifton <nickc@redhat.com>
1218 * configure: Regenerate.
1219 * po/opcodes.pot: Regenerate.
1221 2018-06-24 Nick Clifton <nickc@redhat.com>
1223 2.31 branch created.
1225 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1227 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1228 * aarch64-asm-2.c: Regenerate.
1229 * aarch64-dis-2.c: Likewise.
1231 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1233 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1234 `-M ginv' option description.
1236 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1239 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1242 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1244 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1245 * configure.ac: Remove AC_PREREQ.
1246 * Makefile.in: Re-generate.
1247 * aclocal.m4: Re-generate.
1248 * configure: Re-generate.
1250 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1252 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1253 mips64r6 descriptors.
1254 (parse_mips_ase_option): Handle -Mginv option.
1255 (print_mips_disassembler_options): Document -Mginv.
1256 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1258 (mips_opcodes): Define ginvi and ginvt.
1260 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1261 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1263 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1264 * mips-opc.c (CRC, CRC64): New macros.
1265 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1266 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1269 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1272 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1273 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1275 2018-06-06 Alan Modra <amodra@gmail.com>
1277 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1278 setjmp. Move init for some other vars later too.
1280 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1282 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1283 (dis_private): Add new fields for property section tracking.
1284 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1285 (xtensa_instruction_fits): New functions.
1286 (fetch_data): Bump minimal fetch size to 4.
1287 (print_insn_xtensa): Make struct dis_private static.
1288 Load and prepare property table on section change.
1289 Don't disassemble literals. Don't disassemble instructions that
1290 cross property table boundaries.
1292 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1294 * configure: Regenerated.
1296 2018-06-01 Jan Beulich <jbeulich@suse.com>
1298 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1299 * i386-tbl.h: Re-generate.
1301 2018-06-01 Jan Beulich <jbeulich@suse.com>
1303 * i386-opc.tbl (sldt, str): Add NoRex64.
1304 * i386-tbl.h: Re-generate.
1306 2018-06-01 Jan Beulich <jbeulich@suse.com>
1308 * i386-opc.tbl (invpcid): Add Oword.
1309 * i386-tbl.h: Re-generate.
1311 2018-06-01 Alan Modra <amodra@gmail.com>
1313 * sysdep.h (_bfd_error_handler): Don't declare.
1314 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1315 * rl78-decode.opc: Likewise.
1316 * msp430-decode.c: Regenerate.
1317 * rl78-decode.c: Regenerate.
1319 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1321 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1322 * i386-init.h : Regenerated.
1324 2018-05-25 Alan Modra <amodra@gmail.com>
1326 * Makefile.in: Regenerate.
1327 * po/POTFILES.in: Regenerate.
1329 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1331 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1332 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1333 (insert_bab, extract_bab, insert_btab, extract_btab,
1334 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1335 (BAT, BBA VBA RBS XB6S): Delete macros.
1336 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1337 (BB, BD, RBX, XC6): Update for new macros.
1338 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1339 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1340 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1341 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1343 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1345 * Makefile.am: Add support for s12z architecture.
1346 * configure.ac: Likewise.
1347 * disassemble.c: Likewise.
1348 * disassemble.h: Likewise.
1349 * Makefile.in: Regenerate.
1350 * configure: Regenerate.
1351 * s12z-dis.c: New file.
1354 2018-05-18 Alan Modra <amodra@gmail.com>
1356 * nfp-dis.c: Don't #include libbfd.h.
1357 (init_nfp3200_priv): Use bfd_get_section_contents.
1358 (nit_nfp6000_mecsr_sec): Likewise.
1360 2018-05-17 Nick Clifton <nickc@redhat.com>
1362 * po/zh_CN.po: Updated simplified Chinese translation.
1364 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1367 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1368 * aarch64-dis-2.c: Regenerate.
1370 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1373 * aarch64-asm.c (opintl.h): Include.
1374 (aarch64_ins_sysreg): Enforce read/write constraints.
1375 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1376 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1377 (F_REG_READ, F_REG_WRITE): New.
1378 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1379 AARCH64_OPND_SYSREG.
1380 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1381 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1382 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1383 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1384 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1385 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1386 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1387 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1388 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1389 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1390 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1391 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1392 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1393 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1394 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1395 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1396 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1398 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1401 * aarch64-dis.c (no_notes: New.
1402 (parse_aarch64_dis_option): Support notes.
1403 (aarch64_decode_insn, print_operands): Likewise.
1404 (print_aarch64_disassembler_options): Document notes.
1405 * aarch64-opc.c (aarch64_print_operand): Support notes.
1407 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1410 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1411 and take error struct.
1412 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1413 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1414 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1415 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1416 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1417 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1418 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1419 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1420 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1421 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1422 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1423 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1424 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1425 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1426 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1427 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1428 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1429 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1430 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1431 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1432 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1433 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1434 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1435 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1436 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1437 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1438 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1439 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1440 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1441 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1442 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1443 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1444 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1445 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1446 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1447 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1448 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1449 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1450 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1451 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1452 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1453 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1454 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1455 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1456 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1457 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1458 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1459 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1460 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1461 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1462 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1463 (determine_disassembling_preference, aarch64_decode_insn,
1464 print_insn_aarch64_word, print_insn_data): Take errors struct.
1465 (print_insn_aarch64): Use errors.
1466 * aarch64-asm-2.c: Regenerate.
1467 * aarch64-dis-2.c: Regenerate.
1468 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1469 boolean in aarch64_insert_operan.
1470 (print_operand_extractor): Likewise.
1471 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1473 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1475 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1477 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1479 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1481 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1483 * cr16-opc.c (cr16_instruction): Comment typo fix.
1484 * hppa-dis.c (print_insn_hppa): Likewise.
1486 2018-05-08 Jim Wilson <jimw@sifive.com>
1488 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1489 (match_c_slli64, match_srxi_as_c_srxi): New.
1490 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1491 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1492 <c.slli, c.srli, c.srai>: Use match_s_slli.
1493 <c.slli64, c.srli64, c.srai64>: New.
1495 2018-05-08 Alan Modra <amodra@gmail.com>
1497 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1498 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1499 partition opcode space for index lookup.
1501 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1503 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1504 <insn_length>: ...with this. Update usage.
1505 Remove duplicate call to *info->memory_error_func.
1507 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1508 H.J. Lu <hongjiu.lu@intel.com>
1510 * i386-dis.c (Gva): New.
1511 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1512 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1513 (prefix_table): New instructions (see prefix above).
1514 (mod_table): New instructions (see prefix above).
1515 (OP_G): Handle va_mode.
1516 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1517 CPU_MOVDIR64B_FLAGS.
1518 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1519 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1520 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1521 * i386-opc.tbl: Add movidir{i,64b}.
1522 * i386-init.h: Regenerated.
1523 * i386-tbl.h: Likewise.
1525 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1527 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1529 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1530 (AddrPrefixOpReg): This.
1531 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1532 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1534 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1536 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1537 (vle_num_opcodes): Likewise.
1538 (spe2_num_opcodes): Likewise.
1539 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1540 initialization loop.
1541 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1542 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1545 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1547 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1549 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1551 Makefile.am: Added nfp-dis.c.
1552 configure.ac: Added bfd_nfp_arch.
1553 disassemble.h: Added print_insn_nfp prototype.
1554 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1555 nfp-dis.c: New, for NFP support.
1556 po/POTFILES.in: Added nfp-dis.c to the list.
1557 Makefile.in: Regenerate.
1558 configure: Regenerate.
1560 2018-04-26 Jan Beulich <jbeulich@suse.com>
1562 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1563 templates into their base ones.
1564 * i386-tlb.h: Re-generate.
1566 2018-04-26 Jan Beulich <jbeulich@suse.com>
1568 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1569 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1570 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1571 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1572 * i386-init.h: Re-generate.
1574 2018-04-26 Jan Beulich <jbeulich@suse.com>
1576 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1577 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1578 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1579 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1581 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1583 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1585 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1586 cpuregzmm, and cpuregmask.
1587 * i386-init.h: Re-generate.
1588 * i386-tbl.h: Re-generate.
1590 2018-04-26 Jan Beulich <jbeulich@suse.com>
1592 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1593 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1594 * i386-init.h: Re-generate.
1596 2018-04-26 Jan Beulich <jbeulich@suse.com>
1598 * i386-gen.c (VexImmExt): Delete.
1599 * i386-opc.h (VexImmExt, veximmext): Delete.
1600 * i386-opc.tbl: Drop all VexImmExt uses.
1601 * i386-tlb.h: Re-generate.
1603 2018-04-25 Jan Beulich <jbeulich@suse.com>
1605 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1606 register-only forms.
1607 * i386-tlb.h: Re-generate.
1609 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1611 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1613 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1615 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1617 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1618 (cpu_flags): Add CpuCLDEMOTE.
1619 * i386-init.h: Regenerate.
1620 * i386-opc.h (enum): Add CpuCLDEMOTE,
1621 (i386_cpu_flags): Add cpucldemote.
1622 * i386-opc.tbl: Add cldemote.
1623 * i386-tbl.h: Regenerate.
1625 2018-04-16 Alan Modra <amodra@gmail.com>
1627 * Makefile.am: Remove sh5 and sh64 support.
1628 * configure.ac: Likewise.
1629 * disassemble.c: Likewise.
1630 * disassemble.h: Likewise.
1631 * sh-dis.c: Likewise.
1632 * sh64-dis.c: Delete.
1633 * sh64-opc.c: Delete.
1634 * sh64-opc.h: Delete.
1635 * Makefile.in: Regenerate.
1636 * configure: Regenerate.
1637 * po/POTFILES.in: Regenerate.
1639 2018-04-16 Alan Modra <amodra@gmail.com>
1641 * Makefile.am: Remove w65 support.
1642 * configure.ac: Likewise.
1643 * disassemble.c: Likewise.
1644 * disassemble.h: Likewise.
1645 * w65-dis.c: Delete.
1646 * w65-opc.h: Delete.
1647 * Makefile.in: Regenerate.
1648 * configure: Regenerate.
1649 * po/POTFILES.in: Regenerate.
1651 2018-04-16 Alan Modra <amodra@gmail.com>
1653 * configure.ac: Remove we32k support.
1654 * configure: Regenerate.
1656 2018-04-16 Alan Modra <amodra@gmail.com>
1658 * Makefile.am: Remove m88k support.
1659 * configure.ac: Likewise.
1660 * disassemble.c: Likewise.
1661 * disassemble.h: Likewise.
1662 * m88k-dis.c: Delete.
1663 * Makefile.in: Regenerate.
1664 * configure: Regenerate.
1665 * po/POTFILES.in: Regenerate.
1667 2018-04-16 Alan Modra <amodra@gmail.com>
1669 * Makefile.am: Remove i370 support.
1670 * configure.ac: Likewise.
1671 * disassemble.c: Likewise.
1672 * disassemble.h: Likewise.
1673 * i370-dis.c: Delete.
1674 * i370-opc.c: Delete.
1675 * Makefile.in: Regenerate.
1676 * configure: Regenerate.
1677 * po/POTFILES.in: Regenerate.
1679 2018-04-16 Alan Modra <amodra@gmail.com>
1681 * Makefile.am: Remove h8500 support.
1682 * configure.ac: Likewise.
1683 * disassemble.c: Likewise.
1684 * disassemble.h: Likewise.
1685 * h8500-dis.c: Delete.
1686 * h8500-opc.h: Delete.
1687 * Makefile.in: Regenerate.
1688 * configure: Regenerate.
1689 * po/POTFILES.in: Regenerate.
1691 2018-04-16 Alan Modra <amodra@gmail.com>
1693 * configure.ac: Remove tahoe support.
1694 * configure: Regenerate.
1696 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1698 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1700 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1702 * i386-tbl.h: Regenerated.
1704 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1706 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1707 PREFIX_MOD_1_0FAE_REG_6.
1709 (OP_E_register): Use va_mode.
1710 * i386-dis-evex.h (prefix_table):
1711 New instructions (see prefixes above).
1712 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1713 (cpu_flags): Likewise.
1714 * i386-opc.h (enum): Likewise.
1715 (i386_cpu_flags): Likewise.
1716 * i386-opc.tbl: Add umonitor, umwait, tpause.
1717 * i386-init.h: Regenerate.
1718 * i386-tbl.h: Likewise.
1720 2018-04-11 Alan Modra <amodra@gmail.com>
1722 * opcodes/i860-dis.c: Delete.
1723 * opcodes/i960-dis.c: Delete.
1724 * Makefile.am: Remove i860 and i960 support.
1725 * configure.ac: Likewise.
1726 * disassemble.c: Likewise.
1727 * disassemble.h: Likewise.
1728 * Makefile.in: Regenerate.
1729 * configure: Regenerate.
1730 * po/POTFILES.in: Regenerate.
1732 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1735 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1737 (print_insn): Clear vex instead of vex.evex.
1739 2018-04-04 Nick Clifton <nickc@redhat.com>
1741 * po/es.po: Updated Spanish translation.
1743 2018-03-28 Jan Beulich <jbeulich@suse.com>
1745 * i386-gen.c (opcode_modifiers): Delete VecESize.
1746 * i386-opc.h (VecESize): Delete.
1747 (struct i386_opcode_modifier): Delete vecesize.
1748 * i386-opc.tbl: Drop VecESize.
1749 * i386-tlb.h: Re-generate.
1751 2018-03-28 Jan Beulich <jbeulich@suse.com>
1753 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1754 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1755 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1756 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1757 * i386-tlb.h: Re-generate.
1759 2018-03-28 Jan Beulich <jbeulich@suse.com>
1761 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1763 * i386-tlb.h: Re-generate.
1765 2018-03-28 Jan Beulich <jbeulich@suse.com>
1767 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1768 (vex_len_table): Drop Y for vcvt*2si.
1769 (putop): Replace plain 'Y' handling by abort().
1771 2018-03-28 Nick Clifton <nickc@redhat.com>
1774 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1775 instructions with only a base address register.
1776 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1777 handle AARHC64_OPND_SVE_ADDR_R.
1778 (aarch64_print_operand): Likewise.
1779 * aarch64-asm-2.c: Regenerate.
1780 * aarch64_dis-2.c: Regenerate.
1781 * aarch64-opc-2.c: Regenerate.
1783 2018-03-22 Jan Beulich <jbeulich@suse.com>
1785 * i386-opc.tbl: Drop VecESize from register only insn forms and
1786 memory forms not allowing broadcast.
1787 * i386-tlb.h: Re-generate.
1789 2018-03-22 Jan Beulich <jbeulich@suse.com>
1791 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1792 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1793 sha256*): Drop Disp<N>.
1795 2018-03-22 Jan Beulich <jbeulich@suse.com>
1797 * i386-dis.c (EbndS, bnd_swap_mode): New.
1798 (prefix_table): Use EbndS.
1799 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1800 * i386-opc.tbl (bndmov): Move misplaced Load.
1801 * i386-tlb.h: Re-generate.
1803 2018-03-22 Jan Beulich <jbeulich@suse.com>
1805 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1806 templates allowing memory operands and folded ones for register
1808 * i386-tlb.h: Re-generate.
1810 2018-03-22 Jan Beulich <jbeulich@suse.com>
1812 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1813 256-bit templates. Drop redundant leftover Disp<N>.
1814 * i386-tlb.h: Re-generate.
1816 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1818 * riscv-opc.c (riscv_insn_types): New.
1820 2018-03-13 Nick Clifton <nickc@redhat.com>
1822 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1824 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1826 * i386-opc.tbl: Add Optimize to clr.
1827 * i386-tbl.h: Regenerated.
1829 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1831 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1832 * i386-opc.h (OldGcc): Removed.
1833 (i386_opcode_modifier): Remove oldgcc.
1834 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1835 instructions for old (<= 2.8.1) versions of gcc.
1836 * i386-tbl.h: Regenerated.
1838 2018-03-08 Jan Beulich <jbeulich@suse.com>
1840 * i386-opc.h (EVEXDYN): New.
1841 * i386-opc.tbl: Fold various AVX512VL templates.
1842 * i386-tlb.h: Re-generate.
1844 2018-03-08 Jan Beulich <jbeulich@suse.com>
1846 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1847 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1848 vpexpandd, vpexpandq): Fold AFX512VF templates.
1849 * i386-tlb.h: Re-generate.
1851 2018-03-08 Jan Beulich <jbeulich@suse.com>
1853 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1854 Fold 128- and 256-bit VEX-encoded templates.
1855 * i386-tlb.h: Re-generate.
1857 2018-03-08 Jan Beulich <jbeulich@suse.com>
1859 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1860 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1861 vpexpandd, vpexpandq): Fold AVX512F templates.
1862 * i386-tlb.h: Re-generate.
1864 2018-03-08 Jan Beulich <jbeulich@suse.com>
1866 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1867 64-bit templates. Drop Disp<N>.
1868 * i386-tlb.h: Re-generate.
1870 2018-03-08 Jan Beulich <jbeulich@suse.com>
1872 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1873 and 256-bit templates.
1874 * i386-tlb.h: Re-generate.
1876 2018-03-08 Jan Beulich <jbeulich@suse.com>
1878 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1879 * i386-tlb.h: Re-generate.
1881 2018-03-08 Jan Beulich <jbeulich@suse.com>
1883 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1885 * i386-tlb.h: Re-generate.
1887 2018-03-08 Jan Beulich <jbeulich@suse.com>
1889 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1890 * i386-tlb.h: Re-generate.
1892 2018-03-08 Jan Beulich <jbeulich@suse.com>
1894 * i386-gen.c (opcode_modifiers): Delete FloatD.
1895 * i386-opc.h (FloatD): Delete.
1896 (struct i386_opcode_modifier): Delete floatd.
1897 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1899 * i386-tlb.h: Re-generate.
1901 2018-03-08 Jan Beulich <jbeulich@suse.com>
1903 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1905 2018-03-08 Jan Beulich <jbeulich@suse.com>
1907 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1908 * i386-tlb.h: Re-generate.
1910 2018-03-08 Jan Beulich <jbeulich@suse.com>
1912 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1914 * i386-tlb.h: Re-generate.
1916 2018-03-07 Alan Modra <amodra@gmail.com>
1918 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1920 * disassemble.h (print_insn_rs6000): Delete.
1921 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1922 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1923 (print_insn_rs6000): Delete.
1925 2018-03-03 Alan Modra <amodra@gmail.com>
1927 * sysdep.h (opcodes_error_handler): Define.
1928 (_bfd_error_handler): Declare.
1929 * Makefile.am: Remove stray #.
1930 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1932 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1933 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1934 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1935 opcodes_error_handler to print errors. Standardize error messages.
1936 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1937 and include opintl.h.
1938 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1939 * i386-gen.c: Standardize error messages.
1940 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1941 * Makefile.in: Regenerate.
1942 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1943 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1944 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1945 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1946 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1947 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1948 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1949 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1950 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1951 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1952 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1953 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1954 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1956 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1958 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1959 vpsub[bwdq] instructions.
1960 * i386-tbl.h: Regenerated.
1962 2018-03-01 Alan Modra <amodra@gmail.com>
1964 * configure.ac (ALL_LINGUAS): Sort.
1965 * configure: Regenerate.
1967 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1969 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1970 macro by assignements.
1972 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1975 * i386-gen.c (opcode_modifiers): Add Optimize.
1976 * i386-opc.h (Optimize): New enum.
1977 (i386_opcode_modifier): Add optimize.
1978 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1979 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1980 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1981 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1982 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1984 * i386-tbl.h: Regenerated.
1986 2018-02-26 Alan Modra <amodra@gmail.com>
1988 * crx-dis.c (getregliststring): Allocate a large enough buffer
1989 to silence false positive gcc8 warning.
1991 2018-02-22 Shea Levy <shea@shealevy.com>
1993 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1995 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1997 * i386-opc.tbl: Add {rex},
1998 * i386-tbl.h: Regenerated.
2000 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2002 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2003 (mips16_opcodes): Replace `M' with `m' for "restore".
2005 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2007 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2009 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2011 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2012 variable to `function_index'.
2014 2018-02-13 Nick Clifton <nickc@redhat.com>
2017 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2018 about truncation of printing.
2020 2018-02-12 Henry Wong <henry@stuffedcow.net>
2022 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2024 2018-02-05 Nick Clifton <nickc@redhat.com>
2026 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2028 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2030 * i386-dis.c (enum): Add pconfig.
2031 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2032 (cpu_flags): Add CpuPCONFIG.
2033 * i386-opc.h (enum): Add CpuPCONFIG.
2034 (i386_cpu_flags): Add cpupconfig.
2035 * i386-opc.tbl: Add PCONFIG instruction.
2036 * i386-init.h: Regenerate.
2037 * i386-tbl.h: Likewise.
2039 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2041 * i386-dis.c (enum): Add PREFIX_0F09.
2042 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2043 (cpu_flags): Add CpuWBNOINVD.
2044 * i386-opc.h (enum): Add CpuWBNOINVD.
2045 (i386_cpu_flags): Add cpuwbnoinvd.
2046 * i386-opc.tbl: Add WBNOINVD instruction.
2047 * i386-init.h: Regenerate.
2048 * i386-tbl.h: Likewise.
2050 2018-01-17 Jim Wilson <jimw@sifive.com>
2052 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2054 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2056 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2057 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2058 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2059 (cpu_flags): Add CpuIBT, CpuSHSTK.
2060 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2061 (i386_cpu_flags): Add cpuibt, cpushstk.
2062 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2063 * i386-init.h: Regenerate.
2064 * i386-tbl.h: Likewise.
2066 2018-01-16 Nick Clifton <nickc@redhat.com>
2068 * po/pt_BR.po: Updated Brazilian Portugese translation.
2069 * po/de.po: Updated German translation.
2071 2018-01-15 Jim Wilson <jimw@sifive.com>
2073 * riscv-opc.c (match_c_nop): New.
2074 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2076 2018-01-15 Nick Clifton <nickc@redhat.com>
2078 * po/uk.po: Updated Ukranian translation.
2080 2018-01-13 Nick Clifton <nickc@redhat.com>
2082 * po/opcodes.pot: Regenerated.
2084 2018-01-13 Nick Clifton <nickc@redhat.com>
2086 * configure: Regenerate.
2088 2018-01-13 Nick Clifton <nickc@redhat.com>
2090 2.30 branch created.
2092 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2094 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2095 * i386-tbl.h: Regenerate.
2097 2018-01-10 Jan Beulich <jbeulich@suse.com>
2099 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2100 * i386-tbl.h: Re-generate.
2102 2018-01-10 Jan Beulich <jbeulich@suse.com>
2104 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2105 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2106 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2107 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2108 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2109 Disp8MemShift of AVX512VL forms.
2110 * i386-tbl.h: Re-generate.
2112 2018-01-09 Jim Wilson <jimw@sifive.com>
2114 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2115 then the hi_addr value is zero.
2117 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2119 * arm-dis.c (arm_opcodes): Add csdb.
2120 (thumb32_opcodes): Add csdb.
2122 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2124 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2125 * aarch64-asm-2.c: Regenerate.
2126 * aarch64-dis-2.c: Regenerate.
2127 * aarch64-opc-2.c: Regenerate.
2129 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2132 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2133 Remove AVX512 vmovd with 64-bit operands.
2134 * i386-tbl.h: Regenerated.
2136 2018-01-05 Jim Wilson <jimw@sifive.com>
2138 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2141 2018-01-03 Alan Modra <amodra@gmail.com>
2143 Update year range in copyright notice of all files.
2145 2018-01-02 Jan Beulich <jbeulich@suse.com>
2147 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2148 and OPERAND_TYPE_REGZMM entries.
2150 For older changes see ChangeLog-2017
2152 Copyright (C) 2018 Free Software Foundation, Inc.
2154 Copying and distribution of this file, with or without modification,
2155 are permitted in any medium without royalty provided the copyright
2156 notice and this notice are preserved.
2162 version-control: never