1 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
3 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
4 (AARCH64_OPERANDS): Add Rm_SP.
5 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
6 * aarch64-asm-2.c: Regenerate.
7 * aarch64-dis-2.c: Regenerate.
8 * aarch64-opc-2.c: Regenerate.
10 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
12 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
13 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
15 * aarch64-asm-2.c: Regenerate.
16 * aarch64-dis-2.c: Regenerate.
17 * aarch64-opc-2.c: Regenerate.
19 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
21 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
22 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
23 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
24 (aarch64_sys_reg_supported_p): Add feature test for new registers.
26 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
28 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
29 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
30 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
32 * aarch64-asm-2.c: Regenerate.
33 * aarch64-dis-2.c: Regenerate.
35 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
37 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
39 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
42 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
43 * i386-dis.c (EdqwS): Removed.
44 (dqw_swap_mode): Likewise.
45 (intel_operand_size): Don't check dqw_swap_mode.
46 (OP_E_register): Likewise.
47 (OP_E_memory): Likewise.
50 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
51 * i386-tbl.h: Regerated.
53 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
55 * i386-opc.tbl: Merge AVX512F vmovq.
56 * i386-tbl.h: Regerated.
58 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
61 * i386-dis.c (THREE_BYTE_0F7A): Removed.
62 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
63 (three_byte_table): Remove THREE_BYTE_0F7A.
65 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
68 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
69 (FGRPd9_4): Replace 1 with 2.
70 (FGRPd9_5): Replace 2 with 3.
71 (FGRPd9_6): Replace 3 with 4.
72 (FGRPd9_7): Replace 4 with 5.
73 (FGRPda_5): Replace 5 with 6.
74 (FGRPdb_4): Replace 6 with 7.
75 (FGRPde_3): Replace 7 with 8.
76 (FGRPdf_4): Replace 8 with 9.
77 (fgrps): Add an entry for Bad_Opcode.
79 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
81 * arc-opc.c (arc_flag_operands): Add F_DI14.
82 (arc_flag_classes): Add C_DI14.
83 * arc-nps400-tbl.h: Add new exc instructions.
85 2016-11-03 Graham Markall <graham.markall@embecosm.com>
87 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
89 * arc-nps-400-tbl.h: Add dcmac instruction.
90 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
91 (insert_nps_rbdouble_64): Added.
92 (extract_nps_rbdouble_64): Added.
93 (insert_nps_proto_size): Added.
94 (extract_nps_proto_size): Added.
96 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
98 * arc-dis.c (struct arc_operand_iterator): Remove all fields
99 relating to long instruction processing, add new limm field.
100 (OPCODE): Rename to...
101 (OPCODE_32BIT_INSN): ...this.
103 (skip_this_opcode): Handle different instruction lengths, update
105 (special_flag_p): Update parameter type.
106 (find_format_from_table): Update for more instruction lengths.
107 (find_format_long_instructions): Delete.
108 (find_format): Update for more instruction lengths.
109 (arc_insn_length): Likewise.
110 (extract_operand_value): Update for more instruction lengths.
111 (operand_iterator_next): Remove code relating to long
113 (arc_opcode_to_insn_type): New function.
114 (print_insn_arc):Update for more instructions lengths.
115 * arc-ext.c (extInstruction_t): Change argument type.
116 * arc-ext.h (extInstruction_t): Change argument type.
117 * arc-fxi.h: Change type unsigned to unsigned long long
118 extensively throughout.
119 * arc-nps400-tbl.h: Add long instructions taken from
120 arc_long_opcodes table in arc-opc.c.
121 * arc-opc.c: Update parameter types on insert/extract handlers.
122 (arc_long_opcodes): Delete.
123 (arc_num_long_opcodes): Delete.
124 (arc_opcode_len): Update for more instruction lengths.
126 2016-11-03 Graham Markall <graham.markall@embecosm.com>
128 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
130 2016-11-03 Graham Markall <graham.markall@embecosm.com>
132 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
134 (find_format_long_instructions): Likewise.
135 * arc-opc.c (arc_opcode_len): New function.
137 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
139 * arc-nps400-tbl.h: Fix some instruction masks.
141 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
143 * i386-dis.c (REG_82): Removed.
144 (X86_64_82_REG_0): Likewise.
145 (X86_64_82_REG_1): Likewise.
146 (X86_64_82_REG_2): Likewise.
147 (X86_64_82_REG_3): Likewise.
148 (X86_64_82_REG_4): Likewise.
149 (X86_64_82_REG_5): Likewise.
150 (X86_64_82_REG_6): Likewise.
151 (X86_64_82_REG_7): Likewise.
153 (dis386): Use X86_64_82 instead of REG_82.
154 (reg_table): Remove REG_82.
155 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
156 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
157 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
160 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
163 * i386-dis.c (REG_82): New.
164 (X86_64_82_REG_0): Likewise.
165 (X86_64_82_REG_1): Likewise.
166 (X86_64_82_REG_2): Likewise.
167 (X86_64_82_REG_3): Likewise.
168 (X86_64_82_REG_4): Likewise.
169 (X86_64_82_REG_5): Likewise.
170 (X86_64_82_REG_6): Likewise.
171 (X86_64_82_REG_7): Likewise.
172 (dis386): Use REG_82.
173 (reg_table): Add REG_82.
174 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
175 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
176 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
178 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
180 * i386-dis.c (REG_82): Renamed to ...
183 (reg_table): Likewise.
185 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
187 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
188 * i386-dis-evex.h (evex_table): Updated.
189 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
190 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
191 (cpu_flags): Add CpuAVX512_4VNNIW.
192 * i386-opc.h (enum): (AVX512_4VNNIW): New.
193 (i386_cpu_flags): Add cpuavx512_4vnniw.
194 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
195 * i386-init.h: Regenerate.
198 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
200 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
201 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
202 * i386-dis-evex.h (evex_table): Updated.
203 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
204 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
205 (cpu_flags): Add CpuAVX512_4FMAPS.
206 (opcode_modifiers): Add ImplicitQuadGroup modifier.
207 * i386-opc.h (AVX512_4FMAP): New.
208 (i386_cpu_flags): Add cpuavx512_4fmaps.
209 (ImplicitQuadGroup): New.
210 (i386_opcode_modifier): Add implicitquadgroup.
211 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
212 * i386-init.h: Regenerate.
215 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
216 Andrew Waterman <andrew@sifive.com>
218 Add support for RISC-V architecture.
219 * configure.ac: Add entry for bfd_riscv_arch.
220 * configure: Regenerate.
221 * disassemble.c (disassembler): Add support for riscv.
222 (disassembler_usage): Likewise.
223 * riscv-dis.c: New file.
224 * riscv-opc.c: New file.
226 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
228 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
229 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
230 (rm_table): Update the RM_0FAE_REG_7 entry.
231 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
232 (cpu_flags): Remove CpuPCOMMIT.
233 * i386-opc.h (CpuPCOMMIT): Removed.
234 (i386_cpu_flags): Remove cpupcommit.
235 * i386-opc.tbl: Remove pcommit.
236 * i386-init.h: Regenerated.
237 * i386-tbl.h: Likewise.
239 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
242 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
243 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
244 32-bit mode. Don't check vex.register_specifier in 32-bit
246 (OP_VEX): Check for invalid mask registers.
248 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
251 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
254 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
257 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
259 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
261 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
262 local variable to `index_regno'.
264 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
266 * arc-tbl.h: Removed any "inv.+" instructions from the table.
268 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
270 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
273 2016-10-11 Jiong Wang <jiong.wang@arm.com>
276 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
278 2016-10-07 Jiong Wang <jiong.wang@arm.com>
281 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
284 2016-10-07 Alan Modra <amodra@gmail.com>
286 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
288 2016-10-06 Alan Modra <amodra@gmail.com>
290 * aarch64-opc.c: Spell fall through comments consistently.
291 * i386-dis.c: Likewise.
292 * aarch64-dis.c: Add missing fall through comments.
293 * aarch64-opc.c: Likewise.
294 * arc-dis.c: Likewise.
295 * arm-dis.c: Likewise.
296 * i386-dis.c: Likewise.
297 * m68k-dis.c: Likewise.
298 * mep-asm.c: Likewise.
299 * ns32k-dis.c: Likewise.
300 * sh-dis.c: Likewise.
301 * tic4x-dis.c: Likewise.
302 * tic6x-dis.c: Likewise.
303 * vax-dis.c: Likewise.
305 2016-10-06 Alan Modra <amodra@gmail.com>
307 * arc-ext.c (create_map): Add missing break.
308 * msp430-decode.opc (encode_as): Likewise.
309 * msp430-decode.c: Regenerate.
311 2016-10-06 Alan Modra <amodra@gmail.com>
313 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
314 * crx-dis.c (print_insn_crx): Likewise.
316 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
319 * i386-dis.c (putop): Don't assign alt twice.
321 2016-09-29 Jiong Wang <jiong.wang@arm.com>
324 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
326 2016-09-29 Alan Modra <amodra@gmail.com>
328 * ppc-opc.c (L): Make compulsory.
329 (LOPT): New, optional form of L.
330 (HTM_R): Define as LOPT.
332 (L32OPT): New, optional for 32-bit L.
333 (L2OPT): New, 2-bit L for dcbf.
336 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
337 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
339 <tlbiel, tlbie>: Use LOPT.
340 <wclr, wclrall>: Use L2.
342 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
344 * Makefile.in: Regenerate.
345 * configure: Likewise.
347 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
349 * arc-ext-tbl.h (EXTINSN2OPF): Define.
350 (EXTINSN2OP): Use EXTINSN2OPF.
351 (bspeekm, bspop, modapp): New extension instructions.
352 * arc-opc.c (F_DNZ_ND): Define.
357 * arc-tbl.h (dbnz): New instruction.
358 (prealloc): Allow it for ARC EM.
361 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
363 * aarch64-opc.c (print_immediate_offset_address): Print spaces
364 after commas in addresses.
365 (aarch64_print_operand): Likewise.
367 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
369 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
370 rather than "should be" or "expected to be" in error messages.
372 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
374 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
375 (print_mnemonic_name): ...here.
376 (print_comment): New function.
377 (print_aarch64_insn): Call it.
378 * aarch64-opc.c (aarch64_conds): Add SVE names.
379 (aarch64_print_operand): Print alternative condition names in
382 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
384 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
385 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
386 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
387 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
388 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
389 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
390 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
391 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
392 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
393 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
394 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
395 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
396 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
397 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
398 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
399 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
400 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
401 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
402 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
403 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
404 (OP_SVE_XWU, OP_SVE_XXU): New macros.
405 (aarch64_feature_sve): New variable.
407 (_SVE_INSN): Likewise.
408 (aarch64_opcode_table): Add SVE instructions.
409 * aarch64-opc.h (extract_fields): Declare.
410 * aarch64-opc-2.c: Regenerate.
411 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
412 * aarch64-asm-2.c: Regenerate.
413 * aarch64-dis.c (extract_fields): Make global.
414 (do_misc_decoding): Handle the new SVE aarch64_ops.
415 * aarch64-dis-2.c: Regenerate.
417 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
419 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
420 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
422 * aarch64-opc.c (fields): Add corresponding entries.
423 * aarch64-asm.c (aarch64_get_variant): New function.
424 (aarch64_encode_variant_using_iclass): Likewise.
425 (aarch64_opcode_encode): Call it.
426 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
427 (aarch64_opcode_decode): Call it.
429 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
431 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
432 and FP register operands.
433 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
434 (FLD_SVE_Vn): New aarch64_field_kinds.
435 * aarch64-opc.c (fields): Add corresponding entries.
436 (aarch64_print_operand): Handle the new SVE core and FP register
438 * aarch64-opc-2.c: Regenerate.
439 * aarch64-asm-2.c: Likewise.
440 * aarch64-dis-2.c: Likewise.
442 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
444 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
446 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
447 * aarch64-opc.c (fields): Add corresponding entry.
448 (operand_general_constraint_met_p): Handle the new SVE FP immediate
450 (aarch64_print_operand): Likewise.
451 * aarch64-opc-2.c: Regenerate.
452 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
453 (ins_sve_float_zero_one): New inserters.
454 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
455 (aarch64_ins_sve_float_half_two): Likewise.
456 (aarch64_ins_sve_float_zero_one): Likewise.
457 * aarch64-asm-2.c: Regenerate.
458 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
459 (ext_sve_float_zero_one): New extractors.
460 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
461 (aarch64_ext_sve_float_half_two): Likewise.
462 (aarch64_ext_sve_float_zero_one): Likewise.
463 * aarch64-dis-2.c: Regenerate.
465 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
467 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
468 integer immediate operands.
469 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
470 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
471 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
472 * aarch64-opc.c (fields): Add corresponding entries.
473 (operand_general_constraint_met_p): Handle the new SVE integer
475 (aarch64_print_operand): Likewise.
476 (aarch64_sve_dupm_mov_immediate_p): New function.
477 * aarch64-opc-2.c: Regenerate.
478 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
479 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
480 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
481 (aarch64_ins_limm): ...here.
482 (aarch64_ins_inv_limm): New function.
483 (aarch64_ins_sve_aimm): Likewise.
484 (aarch64_ins_sve_asimm): Likewise.
485 (aarch64_ins_sve_limm_mov): Likewise.
486 (aarch64_ins_sve_shlimm): Likewise.
487 (aarch64_ins_sve_shrimm): Likewise.
488 * aarch64-asm-2.c: Regenerate.
489 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
490 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
491 * aarch64-dis.c (decode_limm): New function, split out from...
492 (aarch64_ext_limm): ...here.
493 (aarch64_ext_inv_limm): New function.
494 (decode_sve_aimm): Likewise.
495 (aarch64_ext_sve_aimm): Likewise.
496 (aarch64_ext_sve_asimm): Likewise.
497 (aarch64_ext_sve_limm_mov): Likewise.
498 (aarch64_top_bit): Likewise.
499 (aarch64_ext_sve_shlimm): Likewise.
500 (aarch64_ext_sve_shrimm): Likewise.
501 * aarch64-dis-2.c: Regenerate.
503 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
505 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
507 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
508 the AARCH64_MOD_MUL_VL entry.
509 (value_aligned_p): Cope with non-power-of-two alignments.
510 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
511 (print_immediate_offset_address): Likewise.
512 (aarch64_print_operand): Likewise.
513 * aarch64-opc-2.c: Regenerate.
514 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
515 (ins_sve_addr_ri_s9xvl): New inserters.
516 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
517 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
518 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
519 * aarch64-asm-2.c: Regenerate.
520 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
521 (ext_sve_addr_ri_s9xvl): New extractors.
522 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
523 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
524 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
525 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
526 * aarch64-dis-2.c: Regenerate.
528 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
530 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
532 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
533 (FLD_SVE_xs_22): New aarch64_field_kinds.
534 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
535 (get_operand_specific_data): New function.
536 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
537 FLD_SVE_xs_14 and FLD_SVE_xs_22.
538 (operand_general_constraint_met_p): Handle the new SVE address
540 (sve_reg): New array.
541 (get_addr_sve_reg_name): New function.
542 (aarch64_print_operand): Handle the new SVE address operands.
543 * aarch64-opc-2.c: Regenerate.
544 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
545 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
546 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
547 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
548 (aarch64_ins_sve_addr_rr_lsl): Likewise.
549 (aarch64_ins_sve_addr_rz_xtw): Likewise.
550 (aarch64_ins_sve_addr_zi_u5): Likewise.
551 (aarch64_ins_sve_addr_zz): Likewise.
552 (aarch64_ins_sve_addr_zz_lsl): Likewise.
553 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
554 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
555 * aarch64-asm-2.c: Regenerate.
556 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
557 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
558 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
559 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
560 (aarch64_ext_sve_addr_ri_u6): Likewise.
561 (aarch64_ext_sve_addr_rr_lsl): Likewise.
562 (aarch64_ext_sve_addr_rz_xtw): Likewise.
563 (aarch64_ext_sve_addr_zi_u5): Likewise.
564 (aarch64_ext_sve_addr_zz): Likewise.
565 (aarch64_ext_sve_addr_zz_lsl): Likewise.
566 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
567 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
568 * aarch64-dis-2.c: Regenerate.
570 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
572 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
573 AARCH64_OPND_SVE_PATTERN_SCALED.
574 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
575 * aarch64-opc.c (fields): Add a corresponding entry.
576 (set_multiplier_out_of_range_error): New function.
577 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
578 (operand_general_constraint_met_p): Handle
579 AARCH64_OPND_SVE_PATTERN_SCALED.
580 (print_register_offset_address): Use PRIi64 to print the
582 (aarch64_print_operand): Likewise. Handle
583 AARCH64_OPND_SVE_PATTERN_SCALED.
584 * aarch64-opc-2.c: Regenerate.
585 * aarch64-asm.h (ins_sve_scale): New inserter.
586 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
587 * aarch64-asm-2.c: Regenerate.
588 * aarch64-dis.h (ext_sve_scale): New inserter.
589 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
590 * aarch64-dis-2.c: Regenerate.
592 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
594 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
595 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
596 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
597 (FLD_SVE_prfop): Likewise.
598 * aarch64-opc.c: Include libiberty.h.
599 (aarch64_sve_pattern_array): New variable.
600 (aarch64_sve_prfop_array): Likewise.
601 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
602 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
603 AARCH64_OPND_SVE_PRFOP.
604 * aarch64-asm-2.c: Regenerate.
605 * aarch64-dis-2.c: Likewise.
606 * aarch64-opc-2.c: Likewise.
608 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
610 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
611 AARCH64_OPND_QLF_P_[ZM].
612 (aarch64_print_operand): Print /z and /m where appropriate.
614 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
616 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
617 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
618 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
619 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
620 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
621 * aarch64-opc.c (fields): Add corresponding entries here.
622 (operand_general_constraint_met_p): Check that SVE register lists
623 have the correct length. Check the ranges of SVE index registers.
624 Check for cases where p8-p15 are used in 3-bit predicate fields.
625 (aarch64_print_operand): Handle the new SVE operands.
626 * aarch64-opc-2.c: Regenerate.
627 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
628 * aarch64-asm.c (aarch64_ins_sve_index): New function.
629 (aarch64_ins_sve_reglist): Likewise.
630 * aarch64-asm-2.c: Regenerate.
631 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
632 * aarch64-dis.c (aarch64_ext_sve_index): New function.
633 (aarch64_ext_sve_reglist): Likewise.
634 * aarch64-dis-2.c: Regenerate.
636 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
638 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
639 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
640 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
641 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
644 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
646 * aarch64-opc.c (get_offset_int_reg_name): New function.
647 (print_immediate_offset_address): Likewise.
648 (print_register_offset_address): Take the base and offset
649 registers as parameters.
650 (aarch64_print_operand): Update caller accordingly. Use
651 print_immediate_offset_address.
653 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
655 * aarch64-opc.c (BANK): New macro.
656 (R32, R64): Take a register number as argument
659 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
661 * aarch64-opc.c (print_register_list): Add a prefix parameter.
662 (aarch64_print_operand): Update accordingly.
664 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
666 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
668 * aarch64-asm.h (ins_fpimm): New inserter.
669 * aarch64-asm.c (aarch64_ins_fpimm): New function.
670 * aarch64-asm-2.c: Regenerate.
671 * aarch64-dis.h (ext_fpimm): New extractor.
672 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
673 (aarch64_ext_fpimm): New function.
674 * aarch64-dis-2.c: Regenerate.
676 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
678 * aarch64-asm.c: Include libiberty.h.
679 (insert_fields): New function.
680 (aarch64_ins_imm): Use it.
681 * aarch64-dis.c (extract_fields): New function.
682 (aarch64_ext_imm): Use it.
684 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
686 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
687 with an esize parameter.
688 (operand_general_constraint_met_p): Update accordingly.
689 Fix misindented code.
690 * aarch64-asm.c (aarch64_ins_limm): Update call to
691 aarch64_logical_immediate_p.
693 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
695 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
697 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
699 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
701 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
703 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
705 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
707 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
708 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
709 xor3>: Delete mnemonics.
710 <cp_abort>: Rename mnemonic from ...
711 <cpabort>: ...to this.
712 <setb>: Change to a X form instruction.
713 <sync>: Change to 1 operand form.
714 <copy>: Delete mnemonic.
715 <copy_first>: Rename mnemonic from ...
717 <paste, paste.>: Delete mnemonics.
718 <paste_last>: Rename mnemonic from ...
719 <paste.>: ...to this.
721 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
723 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
725 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
727 * s390-mkopc.c (main): Support alternate arch strings.
729 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
731 * s390-opc.txt: Fix kmctr instruction type.
733 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
735 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
736 * i386-init.h: Regenerated.
738 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
740 * opcodes/arc-dis.c (print_insn_arc): Changed.
742 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
744 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
747 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
749 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
750 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
751 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
753 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
755 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
756 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
757 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
758 PREFIX_MOD_3_0FAE_REG_4.
759 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
760 PREFIX_MOD_3_0FAE_REG_4.
761 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
762 (cpu_flags): Add CpuPTWRITE.
763 * i386-opc.h (CpuPTWRITE): New.
764 (i386_cpu_flags): Add cpuptwrite.
765 * i386-opc.tbl: Add ptwrite instruction.
766 * i386-init.h: Regenerated.
767 * i386-tbl.h: Likewise.
769 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
771 * arc-dis.h: Wrap around in extern "C".
773 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
775 * aarch64-tbl.h (V8_2_INSN): New macro.
776 (aarch64_opcode_table): Use it.
778 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
780 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
781 CORE_INSN, __FP_INSN and SIMD_INSN.
783 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
785 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
786 (aarch64_opcode_table): Update uses accordingly.
788 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
789 Kwok Cheung Yeung <kcy@codesourcery.com>
792 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
793 'e_cmplwi' to 'e_cmpli' instead.
794 (OPVUPRT, OPVUPRT_MASK): Define.
795 (powerpc_opcodes): Add E200Z4 insns.
796 (vle_opcodes): Add context save/restore insns.
798 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
800 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
801 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
804 2016-07-27 Graham Markall <graham.markall@embecosm.com>
806 * arc-nps400-tbl.h: Change block comments to GNU format.
807 * arc-dis.c: Add new globals addrtypenames,
808 addrtypenames_max, and addtypeunknown.
809 (get_addrtype): New function.
810 (print_insn_arc): Print colons and address types when
812 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
813 define insert and extract functions for all address types.
814 (arc_operands): Add operands for colon and all address
816 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
817 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
818 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
819 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
820 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
821 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
823 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
825 * configure: Regenerated.
827 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
829 * arc-dis.c (skipclass): New structure.
830 (decodelist): New variable.
831 (is_compatible_p): New function.
832 (new_element): Likewise.
833 (skip_class_p): Likewise.
834 (find_format_from_table): Use skip_class_p function.
835 (find_format): Decode first the extension instructions.
836 (print_insn_arc): Select either ARCEM or ARCHS based on elf
838 (parse_option): New function.
839 (parse_disassembler_options): Likewise.
840 (print_arc_disassembler_options): Likewise.
841 (print_insn_arc): Use parse_disassembler_options function. Proper
842 select ARCv2 cpu variant.
843 * disassemble.c (disassembler_usage): Add ARC disassembler
846 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
848 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
849 annotation from the "nal" entry and reorder it beyond "bltzal".
851 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
853 * sparc-opc.c (ldtxa): New macro.
854 (sparc_opcodes): Use the macro defined above to add entries for
855 the LDTXA instructions.
856 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
859 2016-07-07 James Bowman <james.bowman@ftdichip.com>
861 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
864 2016-07-01 Jan Beulich <jbeulich@suse.com>
866 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
867 (movzb): Adjust to cover all permitted suffixes.
869 * i386-tbl.h: Re-generate.
871 2016-07-01 Jan Beulich <jbeulich@suse.com>
873 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
874 (lgdt): Remove Tbyte from non-64-bit variant.
875 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
876 xsaves64, xsavec64): Remove Disp16.
877 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
878 Remove Disp32S from non-64-bit variants. Remove Disp16 from
880 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
881 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
882 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
884 * i386-tbl.h: Re-generate.
886 2016-07-01 Jan Beulich <jbeulich@suse.com>
888 * i386-opc.tbl (xlat): Remove RepPrefixOk.
889 * i386-tbl.h: Re-generate.
891 2016-06-30 Yao Qi <yao.qi@linaro.org>
893 * arm-dis.c (print_insn): Fix typo in comment.
895 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
897 * aarch64-opc.c (operand_general_constraint_met_p): Check the
898 range of ldst_elemlist operands.
899 (print_register_list): Use PRIi64 to print the index.
900 (aarch64_print_operand): Likewise.
902 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
904 * mcore-opc.h: Remove sentinal.
905 * mcore-dis.c (print_insn_mcore): Adjust.
907 2016-06-23 Graham Markall <graham.markall@embecosm.com>
909 * arc-opc.c: Correct description of availability of NPS400
912 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
914 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
915 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
916 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
917 xor3>: New mnemonics.
918 <setb>: Change to a VX form instruction.
919 (insert_sh6): Add support for rldixor.
920 (extract_sh6): Likewise.
922 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
924 * arc-ext.h: Wrap in extern C.
926 2016-06-21 Graham Markall <graham.markall@embecosm.com>
928 * arc-dis.c (arc_insn_length): Add comment on instruction length.
929 Use same method for determining instruction length on ARC700 and
931 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
932 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
933 with the NPS400 subclass.
934 * arc-opc.c: Likewise.
936 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
938 * sparc-opc.c (rdasr): New macro.
944 (sparc_opcodes): Use the macros above to fix and expand the
945 definition of read/write instructions from/to
946 asr/privileged/hyperprivileged instructions.
947 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
948 %hva_mask_nz. Prefer softint_set and softint_clear over
949 set_softint and clear_softint.
950 (print_insn_sparc): Support %ver in Rd.
952 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
954 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
955 architecture according to the hardware capabilities they require.
957 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
959 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
960 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
961 bfd_mach_sparc_v9{c,d,e,v,m}.
962 * sparc-opc.c (MASK_V9C): Define.
963 (MASK_V9D): Likewise.
964 (MASK_V9E): Likewise.
965 (MASK_V9V): Likewise.
966 (MASK_V9M): Likewise.
967 (v6): Add MASK_V9{C,D,E,V,M}.
968 (v6notlet): Likewise.
972 (v9andleon): Likewise.
980 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
982 2016-06-15 Nick Clifton <nickc@redhat.com>
984 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
985 constants to match expected behaviour.
986 (nds32_parse_opcode): Likewise. Also for whitespace.
988 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
990 * arc-opc.c (extract_rhv1): Extract value from insn.
992 2016-06-14 Graham Markall <graham.markall@embecosm.com>
994 * arc-nps400-tbl.h: Add ldbit instruction.
995 * arc-opc.c: Add flag classes required for ldbit.
997 2016-06-14 Graham Markall <graham.markall@embecosm.com>
999 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1000 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1001 support the above instructions.
1003 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1005 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1006 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1007 csma, cbba, zncv, and hofs.
1008 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1009 support the above instructions.
1011 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1013 * arc-nps400-tbl.h: Add andab and orab instructions.
1015 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1017 * arc-nps400-tbl.h: Add addl-like instructions.
1019 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1021 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1023 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1025 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1028 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1030 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1032 (init_disasm): Handle new command line option "insnlength".
1033 (print_s390_disassembler_options): Mention new option in help
1035 (print_insn_s390): Use the encoded insn length when dumping
1036 unknown instructions.
1038 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1040 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1041 to the address and set as symbol address for LDS/ STS immediate operands.
1043 2016-06-07 Alan Modra <amodra@gmail.com>
1045 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1046 cpu for "vle" to e500.
1047 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1048 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1049 (PPCNONE): Delete, substitute throughout.
1050 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1051 except for major opcode 4 and 31.
1052 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1054 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1056 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1057 ARM_EXT_RAS in relevant entries.
1059 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1062 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1065 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1068 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1069 (indir_v_mode): New.
1070 Add comments for '&'.
1071 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1072 (putop): Handle '&'.
1073 (intel_operand_size): Handle indir_v_mode.
1074 (OP_E_register): Likewise.
1075 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1076 64-bit indirect call/jmp for AMD64.
1077 * i386-tbl.h: Regenerated
1079 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1081 * arc-dis.c (struct arc_operand_iterator): New structure.
1082 (find_format_from_table): All the old content from find_format,
1083 with some minor adjustments, and parameter renaming.
1084 (find_format_long_instructions): New function.
1085 (find_format): Rewritten.
1086 (arc_insn_length): Add LSB parameter.
1087 (extract_operand_value): New function.
1088 (operand_iterator_next): New function.
1089 (print_insn_arc): Use new functions to find opcode, and iterator
1091 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1092 (extract_nps_3bit_dst_short): New function.
1093 (insert_nps_3bit_src2_short): New function.
1094 (extract_nps_3bit_src2_short): New function.
1095 (insert_nps_bitop1_size): New function.
1096 (extract_nps_bitop1_size): New function.
1097 (insert_nps_bitop2_size): New function.
1098 (extract_nps_bitop2_size): New function.
1099 (insert_nps_bitop_mod4_msb): New function.
1100 (extract_nps_bitop_mod4_msb): New function.
1101 (insert_nps_bitop_mod4_lsb): New function.
1102 (extract_nps_bitop_mod4_lsb): New function.
1103 (insert_nps_bitop_dst_pos3_pos4): New function.
1104 (extract_nps_bitop_dst_pos3_pos4): New function.
1105 (insert_nps_bitop_ins_ext): New function.
1106 (extract_nps_bitop_ins_ext): New function.
1107 (arc_operands): Add new operands.
1108 (arc_long_opcodes): New global array.
1109 (arc_num_long_opcodes): New global.
1110 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1112 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1114 * nds32-asm.h: Add extern "C".
1115 * sh-opc.h: Likewise.
1117 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1119 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1120 0,b,limm to the rflt instruction.
1122 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1124 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1127 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1130 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1131 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1132 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1133 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1134 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1135 * i386-init.h: Regenerated.
1137 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1140 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1141 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1142 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1143 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1144 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1145 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1146 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1147 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1148 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1149 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1150 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1151 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1152 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1153 CpuRegMask for AVX512.
1154 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1156 (set_bitfield_from_cpu_flag_init): New function.
1157 (set_bitfield): Remove const on f. Call
1158 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1159 * i386-opc.h (CpuRegMMX): New.
1160 (CpuRegXMM): Likewise.
1161 (CpuRegYMM): Likewise.
1162 (CpuRegZMM): Likewise.
1163 (CpuRegMask): Likewise.
1164 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1166 * i386-init.h: Regenerated.
1167 * i386-tbl.h: Likewise.
1169 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1172 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1173 (opcode_modifiers): Add AMD64 and Intel64.
1174 (main): Properly verify CpuMax.
1175 * i386-opc.h (CpuAMD64): Removed.
1176 (CpuIntel64): Likewise.
1177 (CpuMax): Set to CpuNo64.
1178 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1180 (Intel64): Likewise.
1181 (i386_opcode_modifier): Add amd64 and intel64.
1182 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1184 * i386-init.h: Regenerated.
1185 * i386-tbl.h: Likewise.
1187 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1190 * i386-gen.c (main): Fail if CpuMax is incorrect.
1191 * i386-opc.h (CpuMax): Set to CpuIntel64.
1192 * i386-tbl.h: Regenerated.
1194 2016-05-27 Nick Clifton <nickc@redhat.com>
1197 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1198 (msp430dis_opcode_unsigned): New function.
1199 (msp430dis_opcode_signed): New function.
1200 (msp430_singleoperand): Use the new opcode reading functions.
1201 Only disassenmble bytes if they were successfully read.
1202 (msp430_doubleoperand): Likewise.
1203 (msp430_branchinstr): Likewise.
1204 (msp430x_callx_instr): Likewise.
1205 (print_insn_msp430): Check that it is safe to read bytes before
1206 attempting disassembly. Use the new opcode reading functions.
1208 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1210 * ppc-opc.c (CY): New define. Document it.
1211 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1213 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1215 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1216 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1217 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1218 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1220 * i386-init.h: Regenerated.
1222 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1225 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1226 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1227 * i386-init.h: Regenerated.
1229 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1231 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1232 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1233 * i386-init.h: Regenerated.
1235 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1237 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1239 (print_insn_arc): Set insn_type information.
1240 * arc-opc.c (C_CC): Add F_CLASS_COND.
1241 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1242 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1243 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1244 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1245 (brne, brne_s, jeq_s, jne_s): Likewise.
1247 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1249 * arc-tbl.h (neg): New instruction variant.
1251 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1253 * arc-dis.c (find_format, find_format, get_auxreg)
1254 (print_insn_arc): Changed.
1255 * arc-ext.h (INSERT_XOP): Likewise.
1257 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1259 * tic54x-dis.c (sprint_mmr): Adjust.
1260 * tic54x-opc.c: Likewise.
1262 2016-05-19 Alan Modra <amodra@gmail.com>
1264 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1266 2016-05-19 Alan Modra <amodra@gmail.com>
1268 * ppc-opc.c: Formatting.
1269 (NSISIGNOPT): Define.
1270 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1272 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1274 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1275 replacing references to `micromips_ase' throughout.
1276 (_print_insn_mips): Don't use file-level microMIPS annotation to
1277 determine the disassembly mode with the symbol table.
1279 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1281 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1283 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1285 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1287 * mips-opc.c (D34): New macro.
1288 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1290 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1292 * i386-dis.c (prefix_table): Add RDPID instruction.
1293 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1294 (cpu_flags): Add RDPID bitfield.
1295 * i386-opc.h (enum): Add RDPID element.
1296 (i386_cpu_flags): Add RDPID field.
1297 * i386-opc.tbl: Add RDPID instruction.
1298 * i386-init.h: Regenerate.
1299 * i386-tbl.h: Regenerate.
1301 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1303 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1304 branch type of a symbol.
1305 (print_insn): Likewise.
1307 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1309 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1310 Mainline Security Extensions instructions.
1311 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1312 Extensions instructions.
1313 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1315 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1318 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1320 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1322 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1324 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1325 (arcExtMap_genOpcode): Likewise.
1326 * arc-opc.c (arg_32bit_rc): Define new variable.
1327 (arg_32bit_u6): Likewise.
1328 (arg_32bit_limm): Likewise.
1330 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1332 * aarch64-gen.c (VERIFIER): Define.
1333 * aarch64-opc.c (VERIFIER): Define.
1334 (verify_ldpsw): Use static linkage.
1335 * aarch64-opc.h (verify_ldpsw): Remove.
1336 * aarch64-tbl.h: Use VERIFIER for verifiers.
1338 2016-04-28 Nick Clifton <nickc@redhat.com>
1341 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1342 * aarch64-opc.c (verify_ldpsw): New function.
1343 * aarch64-opc.h (verify_ldpsw): New prototype.
1344 * aarch64-tbl.h: Add initialiser for verifier field.
1345 (LDPSW): Set verifier to verify_ldpsw.
1347 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1351 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1352 smaller than address size.
1354 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1356 * alpha-dis.c: Regenerate.
1357 * crx-dis.c: Likewise.
1358 * disassemble.c: Likewise.
1359 * epiphany-opc.c: Likewise.
1360 * fr30-opc.c: Likewise.
1361 * frv-opc.c: Likewise.
1362 * ip2k-opc.c: Likewise.
1363 * iq2000-opc.c: Likewise.
1364 * lm32-opc.c: Likewise.
1365 * lm32-opinst.c: Likewise.
1366 * m32c-opc.c: Likewise.
1367 * m32r-opc.c: Likewise.
1368 * m32r-opinst.c: Likewise.
1369 * mep-opc.c: Likewise.
1370 * mt-opc.c: Likewise.
1371 * or1k-opc.c: Likewise.
1372 * or1k-opinst.c: Likewise.
1373 * tic80-opc.c: Likewise.
1374 * xc16x-opc.c: Likewise.
1375 * xstormy16-opc.c: Likewise.
1377 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1379 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1380 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1381 calcsd, and calcxd instructions.
1382 * arc-opc.c (insert_nps_bitop_size): Delete.
1383 (extract_nps_bitop_size): Delete.
1384 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1385 (extract_nps_qcmp_m3): Define.
1386 (extract_nps_qcmp_m2): Define.
1387 (extract_nps_qcmp_m1): Define.
1388 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1389 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1390 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1391 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1392 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1395 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1397 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1399 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1401 * Makefile.in: Regenerated with automake 1.11.6.
1402 * aclocal.m4: Likewise.
1404 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1406 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1408 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1409 (extract_nps_cmem_uimm16): New function.
1410 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1412 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1414 * arc-dis.c (arc_insn_length): New function.
1415 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1416 (find_format): Change insnLen parameter to unsigned.
1418 2016-04-13 Nick Clifton <nickc@redhat.com>
1421 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1422 the LD.B and LD.BU instructions.
1424 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1426 * arc-dis.c (find_format): Check for extension flags.
1427 (print_flags): New function.
1428 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1430 * arc-ext.c (arcExtMap_coreRegName): Use
1431 LAST_EXTENSION_CORE_REGISTER.
1432 (arcExtMap_coreReadWrite): Likewise.
1433 (dump_ARC_extmap): Update printing.
1434 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1435 (arc_aux_regs): Add cpu field.
1436 * arc-regs.h: Add cpu field, lower case name aux registers.
1438 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1440 * arc-tbl.h: Add rtsc, sleep with no arguments.
1442 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1444 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1446 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1447 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1448 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1449 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1450 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1451 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1452 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1453 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1454 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1455 (arc_opcode arc_opcodes): Null terminate the array.
1456 (arc_num_opcodes): Remove.
1457 * arc-ext.h (INSERT_XOP): Define.
1458 (extInstruction_t): Likewise.
1459 (arcExtMap_instName): Delete.
1460 (arcExtMap_insn): New function.
1461 (arcExtMap_genOpcode): Likewise.
1462 * arc-ext.c (ExtInstruction): Remove.
1463 (create_map): Zero initialize instruction fields.
1464 (arcExtMap_instName): Remove.
1465 (arcExtMap_insn): New function.
1466 (dump_ARC_extmap): More info while debuging.
1467 (arcExtMap_genOpcode): New function.
1468 * arc-dis.c (find_format): New function.
1469 (print_insn_arc): Use find_format.
1470 (arc_get_disassembler): Enable dump_ARC_extmap only when
1473 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1475 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1476 instruction bits out.
1478 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1480 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1481 * arc-opc.c (arc_flag_operands): Add new flags.
1482 (arc_flag_classes): Add new classes.
1484 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1486 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1488 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1490 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1491 encode1, rflt, crc16, and crc32 instructions.
1492 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1493 (arc_flag_classes): Add C_NPS_R.
1494 (insert_nps_bitop_size_2b): New function.
1495 (extract_nps_bitop_size_2b): Likewise.
1496 (insert_nps_bitop_uimm8): Likewise.
1497 (extract_nps_bitop_uimm8): Likewise.
1498 (arc_operands): Add new operand entries.
1500 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1502 * arc-regs.h: Add a new subclass field. Add double assist
1503 accumulator register values.
1504 * arc-tbl.h: Use DPA subclass to mark the double assist
1505 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1506 * arc-opc.c (RSP): Define instead of SP.
1507 (arc_aux_regs): Add the subclass field.
1509 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1511 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1513 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1515 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1518 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1520 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1521 issues. No functional changes.
1523 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1525 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1526 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1527 (RTT): Remove duplicate.
1528 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1529 (PCT_CONFIG*): Remove.
1530 (D1L, D1H, D2H, D2L): Define.
1532 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1534 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1536 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1538 * arc-tbl.h (invld07): Remove.
1539 * arc-ext-tbl.h: New file.
1540 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1541 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1543 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1545 Fix -Wstack-usage warnings.
1546 * aarch64-dis.c (print_operands): Substitute size.
1547 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1549 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1551 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1552 to get a proper diagnostic when an invalid ASR register is used.
1554 2016-03-22 Nick Clifton <nickc@redhat.com>
1556 * configure: Regenerate.
1558 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1560 * arc-nps400-tbl.h: New file.
1561 * arc-opc.c: Add top level comment.
1562 (insert_nps_3bit_dst): New function.
1563 (extract_nps_3bit_dst): New function.
1564 (insert_nps_3bit_src2): New function.
1565 (extract_nps_3bit_src2): New function.
1566 (insert_nps_bitop_size): New function.
1567 (extract_nps_bitop_size): New function.
1568 (arc_flag_operands): Add nps400 entries.
1569 (arc_flag_classes): Add nps400 entries.
1570 (arc_operands): Add nps400 entries.
1571 (arc_opcodes): Add nps400 include.
1573 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1575 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1576 the new class enum values.
1578 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1580 * arc-dis.c (print_insn_arc): Handle nps400.
1582 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1584 * arc-opc.c (BASE): Delete.
1586 2016-03-18 Nick Clifton <nickc@redhat.com>
1589 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1590 of MOV insn that aliases an ORR insn.
1592 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1594 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1596 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1598 * mcore-opc.h: Add const qualifiers.
1599 * microblaze-opc.h (struct op_code_struct): Likewise.
1600 * sh-opc.h: Likewise.
1601 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1602 (tic4x_print_op): Likewise.
1604 2016-03-02 Alan Modra <amodra@gmail.com>
1606 * or1k-desc.h: Regenerate.
1607 * fr30-ibld.c: Regenerate.
1608 * rl78-decode.c: Regenerate.
1610 2016-03-01 Nick Clifton <nickc@redhat.com>
1613 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1615 2016-02-24 Renlin Li <renlin.li@arm.com>
1617 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1618 (print_insn_coprocessor): Support fp16 instructions.
1620 2016-02-24 Renlin Li <renlin.li@arm.com>
1622 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1623 vminnm, vrint(mpna).
1625 2016-02-24 Renlin Li <renlin.li@arm.com>
1627 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1628 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1630 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1632 * i386-dis.c (print_insn): Parenthesize expression to prevent
1633 truncated addresses.
1636 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1637 Janek van Oirschot <jvanoirs@synopsys.com>
1639 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1642 2016-02-04 Nick Clifton <nickc@redhat.com>
1645 * msp430-dis.c (print_insn_msp430): Add a special case for
1646 decoding an RRC instruction with the ZC bit set in the extension
1649 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1651 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1652 * epiphany-ibld.c: Regenerate.
1653 * fr30-ibld.c: Regenerate.
1654 * frv-ibld.c: Regenerate.
1655 * ip2k-ibld.c: Regenerate.
1656 * iq2000-ibld.c: Regenerate.
1657 * lm32-ibld.c: Regenerate.
1658 * m32c-ibld.c: Regenerate.
1659 * m32r-ibld.c: Regenerate.
1660 * mep-ibld.c: Regenerate.
1661 * mt-ibld.c: Regenerate.
1662 * or1k-ibld.c: Regenerate.
1663 * xc16x-ibld.c: Regenerate.
1664 * xstormy16-ibld.c: Regenerate.
1666 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1668 * epiphany-dis.c: Regenerated from latest cpu files.
1670 2016-02-01 Michael McConville <mmcco@mykolab.com>
1672 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1675 2016-01-25 Renlin Li <renlin.li@arm.com>
1677 * arm-dis.c (mapping_symbol_for_insn): New function.
1678 (find_ifthen_state): Call mapping_symbol_for_insn().
1680 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1682 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1683 of MSR UAO immediate operand.
1685 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1687 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1688 instruction support.
1690 2016-01-17 Alan Modra <amodra@gmail.com>
1692 * configure: Regenerate.
1694 2016-01-14 Nick Clifton <nickc@redhat.com>
1696 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1697 instructions that can support stack pointer operations.
1698 * rl78-decode.c: Regenerate.
1699 * rl78-dis.c: Fix display of stack pointer in MOVW based
1702 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1704 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1705 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1706 erxtatus_el1 and erxaddr_el1.
1708 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1710 * arm-dis.c (arm_opcodes): Add "esb".
1711 (thumb_opcodes): Likewise.
1713 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1715 * ppc-opc.c <xscmpnedp>: Delete.
1716 <xvcmpnedp>: Likewise.
1717 <xvcmpnedp.>: Likewise.
1718 <xvcmpnesp>: Likewise.
1719 <xvcmpnesp.>: Likewise.
1721 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1724 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1727 2016-01-01 Alan Modra <amodra@gmail.com>
1729 Update year range in copyright notice of all files.
1731 For older changes see ChangeLog-2015
1733 Copyright (C) 2016 Free Software Foundation, Inc.
1735 Copying and distribution of this file, with or without modification,
1736 are permitted in any medium without royalty provided the copyright
1737 notice and this notice are preserved.
1743 version-control: never