opcodes/ChangeLog

   1 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
   2
   3         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
   4         mode.
   5         * crx-dis.c: Likewise.
   6
   7 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
   8
   9         Generally, handle CRISv32.
  10         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
  11         (struct cris_disasm_data): New type.
  12         (format_reg, format_hex, cris_constraint, print_flags)
  13         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
  14         callers changed.
  15         (format_sup_reg, print_insn_crisv32_with_register_prefix)
  16         (print_insn_crisv32_without_register_prefix)
  17         (print_insn_crisv10_v32_with_register_prefix)
  18         (print_insn_crisv10_v32_without_register_prefix)
  19         (cris_parse_disassembler_options): New functions.
  20         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
  21         parameter.  All callers changed.
  22         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
  23         failure.
  24         (cris_constraint) <case 'Y', 'U'>: New cases.
  25         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
  26         for constraint 'n'.
  27         (print_with_operands) <case 'Y'>: New case.
  28         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
  29         <case 'N', 'Y', 'Q'>: New cases.
  30         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
  31         (print_insn_cris_with_register_prefix)
  32         (print_insn_cris_without_register_prefix): Call
  33         cris_parse_disassembler_options.
  34         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
  35         for CRISv32 and the size of immediate operands.  New v32-only
  36         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
  37         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
  38         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
  39         Change brp to be v3..v10.
  40         (cris_support_regs): New vector.
  41         (cris_opcodes): Update head comment.  New format characters '[',
  42         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
  43         Add new opcodes for v32 and adjust existing opcodes to accommodate
  44         differences to earlier variants.
  45         (cris_cond15s): New vector.
  46
  47 2004-11-04 Jan Beulich <jbeulich@novell.com>
  48
  49         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
  50         (indirEb): Remove.
  51         (Mp): Use f_mode rather than none at all.
  52         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
  53         replaces what previously was x_mode; x_mode now means 128-bit SSE
  54         operands.
  55         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
  56         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
  57         pinsrw's second operand is Edqw.
  58         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
  59         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
  60         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
  61         mode when an operand size override is present or always suffixing.
  62         More instructions will need to be added to this group.
  63         (putop): Handle new macro chars 'C' (short/long suffix selector),
  64         'I' (Intel mode override for following macro char), and 'J' (for
  65         adding the 'l' prefix to far branches in AT&T mode). When an
  66         alternative was specified in the template, honor macro character when
  67         specified for Intel mode.
  68         (OP_E): Handle new *_mode values. Correct pointer specifications for
  69         memory operands. Consolidate output of index register.
  70         (OP_G): Handle new *_mode values.
  71         (OP_I): Handle const_1_mode.
  72         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
  73         respective opcode prefix bits have been consumed.
  74         (OP_EM, OP_EX): Provide some default handling for generating pointer
  75         specifications.
  76
  77 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
  78
  79         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
  80         COP_INST macro.
  81
  82 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  83
  84         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
  85         (getregliststring): Support HI/LO and user registers.
  86         * crx-opc.c (crx_instruction): Update data structure according to the
  87         rearrangement done in CRX opcode header file.
  88         (crx_regtab):  Likewise.
  89         (crx_optab):  Likewise.
  90         (crx_instruction): Reorder load/stor instructions, remove unsupported
  91         formats.
  92         support new Co-Processor instruction 'cpi'.
  93
  94 2004-10-27  Nick Clifton  <nickc@redhat.com>
  95
  96         * opcodes/iq2000-asm.c: Regenerate.
  97         * opcodes/iq2000-desc.c: Regenerate.
  98         * opcodes/iq2000-desc.h: Regenerate.
  99         * opcodes/iq2000-dis.c: Regenerate.
 100         * opcodes/iq2000-ibld.c: Regenerate.
 101         * opcodes/iq2000-opc.c: Regenerate.
 102         * opcodes/iq2000-opc.h: Regenerate.
 103
 104 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 105
 106         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 107         us4, us5 (respectively).
 108         Remove unsupported 'popa' instruction.
 109         Reverse operands order in store co-processor instructions.
 110
 111 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 112
 113         * Makefile.am: Run "make dep-am"
 114         * Makefile.in: Regenerate.
 115
 116 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 117
 118         * xtensa-dis.c: Use ISO C90 formatting.
 119
 120 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 121
 122         * ppc-opc.c: Revert 2004-09-09 change.
 123
 124 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 125
 126         * xtensa-dis.c (state_names): Delete.
 127         (fetch_data): Use xtensa_isa_maxlength.
 128         (print_xtensa_operand): Replace operand parameter with opcode/operand
 129         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 130         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 131         instruction bundles.  Use xmalloc instead of malloc.
 132
 133 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 134
 135         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 136         initializers.
 137
 138 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 139
 140         * crx-opc.c (crx_instruction): Support Co-processor insns.
 141         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 142         (getregliststring): Change function to use the above enum.
 143         (print_arg): Handle CO-Processor insns.
 144         (crx_cinvs): Add 'b' option to invalidate the branch-target
 145         cache.
 146
 147 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 148
 149         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 150         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 151         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 152         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 153         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 154
 155 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 156
 157         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 158         rather than add it.
 159
 160 2004-09-30  Paul Brook  <paul@codesourcery.com>
 161
 162         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 163         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 164
 165 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 166
 167         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 168         (CONFIG_STATUS_DEPENDENCIES): New.
 169         (Makefile): Removed.
 170         (config.status): Likewise.
 171         * Makefile.in: Regenerated.
 172
 173 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 174
 175         * Makefile.am: Run "make dep-am".
 176         * Makefile.in: Regenerate.
 177         * aclocal.m4: Regenerate.
 178         * configure: Regenerate.
 179         * po/POTFILES.in: Regenerate.
 180         * po/opcodes.pot: Regenerate.
 181
 182 2004-09-11  Andreas Schwab  <schwab@suse.de>
 183
 184         * configure: Rebuild.
 185
 186 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 187
 188         * ppc-opc.c (L): Make this field not optional.
 189
 190 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 191
 192         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 193         Fix parameter to 'm[t|f]csr' insns.
 194
 195 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 196
 197         * configure.in: Autoupdate to autoconf 2.59.
 198         * aclocal.m4: Rebuild with aclocal 1.4p6.
 199         * configure: Rebuild with autoconf 2.59.
 200         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 201         bfd changes for autoconf 2.59 on the way).
 202         * config.in: Rebuild with autoheader 2.59.
 203
 204 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 205
 206         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 207
 208 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 209
 210         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 211         (GRPPADLCK2): New define.
 212         (twobyte_has_modrm): True for 0xA6.
 213         (grps): GRPPADLCK2 for opcode 0xA6.
 214
 215 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 216
 217         Introduce SH2a support.
 218         * sh-opc.h (arch_sh2a_base): Renumber.
 219         (arch_sh2a_nofpu_base): Remove.
 220         (arch_sh_base_mask): Adjust.
 221         (arch_opann_mask): New.
 222         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 223         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 224         (sh_table): Adjust whitespace.
 225         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 226         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 227         instruction list throughout.
 228         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 229         of arch_sh2a in instruction list throughout.
 230         (arch_sh2e_up): Accomodate above changes.
 231         (arch_sh2_up): Ditto.
 232         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 233         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 234         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 235         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 236         * sh-opc.h (arch_sh2a_nofpu): New.
 237         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 238         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 239         instruction.
 240         2004-01-20  DJ Delorie  <dj@redhat.com>
 241         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 242         2003-12-29  DJ Delorie  <dj@redhat.com>
 243         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 244         sh_opcode_info, sh_table): Add sh2a support.
 245         (arch_op32): New, to tag 32-bit opcodes.
 246         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 247         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 248         * sh-opc.h (arch_sh2a): Add.
 249         * sh-dis.c (arch_sh2a): Handle.
 250         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 251
 252 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 253
 254         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 255
 256 2004-07-22  Nick Clifton  <nickc@redhat.com>
 257
 258         PR/280
 259         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 260         insns - this is done by objdump itself.
 261         * h8500-dis.c (print_insn_h8500): Likewise.
 262
 263 2004-07-21  Jan Beulich <jbeulich@novell.com>
 264
 265         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 266         regardless of address size prefix in effect.
 267         (ptr_reg): Size or address registers does not depend on rex64, but
 268         on the presence of an address size override.
 269         (OP_MMX): Use rex.x only for xmm registers.
 270         (OP_EM): Use rex.z only for xmm registers.
 271
 272 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 273
 274         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 275         move/branch operations to the bottom so that VR5400 multimedia
 276         instructions take precedence in disassembly.
 277
 278 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 279
 280         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 281         ISA-specific "break" encoding.
 282
 283 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 284
 285         * arm-opc.h: Fix typo in comment.
 286
 287 2004-07-11  Andreas Schwab  <schwab@suse.de>
 288
 289         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 290
 291 2004-07-09  Andreas Schwab  <schwab@suse.de>
 292
 293         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 294
 295 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 296
 297         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 298         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 299         (crx-dis.lo): New target.
 300         (crx-opc.lo): Likewise.
 301         * Makefile.in: Regenerate.
 302         * configure.in: Handle bfd_crx_arch.
 303         * configure: Regenerate.
 304         * crx-dis.c: New file.
 305         * crx-opc.c: New file.
 306         * disassemble.c (ARCH_crx): Define.
 307         (disassembler): Handle ARCH_crx.
 308
 309 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 310
 311         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 312         * ia64-asmtab.c: Regnerate.
 313
 314 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 315
 316         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 317         (extract_fxm): Don't test dialect.
 318         (XFXFXM_MASK): Include the power4 bit.
 319         (XFXM): Add p4 param.
 320         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 321
 322 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 323
 324         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 325         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 326
 327 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 328
 329         * ppc-opc.c (BH, XLBH_MASK): Define.
 330         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 331
 332 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 333
 334         * i386-dis.c (x_mode): Comment.
 335         (two_source_ops): File scope.
 336         (float_mem): Correct fisttpll and fistpll.
 337         (float_mem_mode): New table.
 338         (dofloat): Use it.
 339         (OP_E): Correct intel mode PTR output.
 340         (ptr_reg): Use open_char and close_char.
 341         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 342         operands.  Set two_source_ops.
 343
 344 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 345
 346         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 347         instead of _raw_size.
 348
 349 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 350
 351         * ia64-gen.c (in_iclass): Handle more postinc st
 352         and ld variants.
 353         * ia64-asmtab.c: Rebuilt.
 354
 355 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 356
 357         * s390-opc.txt: Correct architecture mask for some opcodes.
 358         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 359         in the esa mode as well.
 360
 361 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 362
 363         * sh-dis.c (target_arch): Make unsigned.
 364         (print_insn_sh): Replace (most of) switch with a call to
 365         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 366         * sh-opc.h: Redefine architecture flags values.
 367         Add sh3-nommu architecture.
 368         Reorganise <arch>_up macros so they make more visual sense.
 369         (SH_MERGE_ARCH_SET): Define new macro.
 370         (SH_VALID_BASE_ARCH_SET): Likewise.
 371         (SH_VALID_MMU_ARCH_SET): Likewise.
 372         (SH_VALID_CO_ARCH_SET): Likewise.
 373         (SH_VALID_ARCH_SET): Likewise.
 374         (SH_MERGE_ARCH_SET_VALID): Likewise.
 375         (SH_ARCH_SET_HAS_FPU): Likewise.
 376         (SH_ARCH_SET_HAS_DSP): Likewise.
 377         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 378         (sh_get_arch_from_bfd_mach): Add prototype.
 379         (sh_get_arch_up_from_bfd_mach): Likewise.
 380         (sh_get_bfd_mach_from_arch_set): Likewise.
 381         (sh_merge_bfd_arc): Likewise.
 382
 383 2004-05-24  Peter Barada  <peter@the-baradas.com>
 384
 385         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 386         into new match_insn_m68k function.  Loop over canidate
 387         matches and select first that completely matches.
 388         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 389         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 390         to verify addressing for MAC/EMAC.
 391         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 392         reigster halves since 'fpu' and 'spl' look misleading.
 393         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 394         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 395         first, tighten up match masks.
 396         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 397         'size' from special case code in print_insn_m68k to
 398         determine decode size of insns.
 399
 400 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 401
 402         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 403         well as when -mpower4.
 404
 405 2004-05-13  Nick Clifton  <nickc@redhat.com>
 406
 407         * po/fr.po: Updated French translation.
 408
 409 2004-05-05  Peter Barada  <peter@the-baradas.com>
 410
 411         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 412         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 413         * m68k-op.c: Switch from ColdFire chips to core variants.
 414
 415 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 416
 417         PR 147.
 418         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 419
 420 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 421
 422         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 423         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 424
 425 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 426
 427         * sh-dis.c (print_insn_sh): Print the value in constant pool
 428         as a symbol if it looks like a symbol.
 429
 430 2004-04-22  Peter Barada <peter@the-baradas.com>
 431
 432         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 433         appropriate ColdFire architectures.
 434         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 435         mask addressing.
 436         Add EMAC instructions, fix MAC instructions. Remove
 437         macmw/macml/msacmw/msacml instructions since mask addressing now
 438         supported.
 439
 440 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 441
 442         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 443         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 444         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 445         macro.  Adjust all users.
 446
 447 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 448
 449         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 450         separately.
 451
 452 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 453
 454         * m32r-asm.c: Regenerate.
 455
 456 2004-03-29  Stan Shebs  <shebs@apple.com>
 457
 458         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 459         used.
 460
 461 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 462
 463         * aclocal.m4: Regenerate.
 464         * config.in: Regenerate.
 465         * configure: Regenerate.
 466         * po/POTFILES.in: Regenerate.
 467         * po/opcodes.pot: Regenerate.
 468
 469 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 470
 471         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 472         PPC_OPERANDS_GPR_0.
 473         * ppc-opc.c (RA0): Define.
 474         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 475         (RAOPT): Rename from RAO.  Update all uses.
 476         (powerpc_opcodes): Use RA0 as appropriate.
 477
 478 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 479
 480         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 481
 482 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 483
 484         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 485
 486 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 487
 488         * i386-dis.c (GRPPLOCK): Delete.
 489         (grps): Delete GRPPLOCK entry.
 490
 491 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 492
 493         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 494         (M, Mp): Use OP_M.
 495         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 496         (GRPPADLCK): Define.
 497         (dis386): Use NOP_Fixup on "nop".
 498         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 499         (twobyte_has_modrm): Set for 0xa7.
 500         (padlock_table): Delete.  Move to..
 501         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 502         and clflush.
 503         (print_insn): Revert PADLOCK_SPECIAL code.
 504         (OP_E): Delete sfence, lfence, mfence checks.
 505
 506 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 507
 508         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 509         (INVLPG_Fixup): New function.
 510         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 511
 512 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 513
 514         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 515         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 516         (padlock_table): New struct with PadLock instructions.
 517         (print_insn): Handle PADLOCK_SPECIAL.
 518
 519 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 520
 521         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 522         (OP_E): Twiddle clflush to sfence here.
 523
 524 2004-03-08  Nick Clifton  <nickc@redhat.com>
 525
 526         * po/de.po: Updated German translation.
 527
 528 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 529
 530         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 531         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 532         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 533         accordingly.
 534
 535 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 536
 537         * frv-asm.c: Regenerate.
 538         * frv-desc.c: Regenerate.
 539         * frv-desc.h: Regenerate.
 540         * frv-dis.c: Regenerate.
 541         * frv-ibld.c: Regenerate.
 542         * frv-opc.c: Regenerate.
 543         * frv-opc.h: Regenerate.
 544
 545 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 546
 547         * frv-desc.c, frv-opc.c: Regenerate.
 548
 549 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 550
 551         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 552
 553 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 554
 555         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 556         Also correct mistake in the comment.
 557
 558 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 559
 560         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 561         ensure that double registers have even numbers.
 562         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 563         that reserved instruction 0xfffd does not decode the same
 564         as 0xfdfd (ftrv).
 565         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 566         REG_N refers to a double register.
 567         Add REG_N_B01 nibble type and use it instead of REG_NM
 568         in ftrv.
 569         Adjust the bit patterns in a few comments.
 570
 571 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 572
 573         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 574
 575 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 576
 577         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 578
 579 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 580
 581         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 582
 583 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 584
 585         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 586         mtivor32, mtivor33, mtivor34.
 587
 588 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 589
 590         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 591
 592 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 593
 594         * arm-opc.h Maverick accumulator register opcode fixes.
 595
 596 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 597
 598         * m32r-dis.c: Regenerate.
 599
 600 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 601
 602         * sh-opc.h (sh_table): "fsrra", not "fssra".
 603
 604 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 605
 606         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 607         contraints.
 608
 609 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 610
 611         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 612
 613 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 614
 615         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 616         1.  Don't print scale factor on AT&T mode when index missing.
 617
 618 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 619
 620         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 621         when loaded into XR registers.
 622
 623 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 624
 625         * frv-desc.h: Regenerate.
 626         * frv-desc.c: Regenerate.
 627         * frv-opc.c: Regenerate.
 628
 629 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 630
 631         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 632
 633 2004-01-09  Paul Brook  <paul@codesourcery.com>
 634
 635         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 636         specific opcodes.
 637
 638 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 639
 640         * Makefile.am (libopcodes_la_DEPENDENCIES)
 641         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 642         comment about the problem.
 643         * Makefile.in: Regenerate.
 644
 645 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 646
 647         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 648         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 649         cut&paste errors in shifting/truncating numerical operands.
 650         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 651         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 652         (parse_uslo16): Likewise.
 653         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 654         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 655         (parse_s12): Likewise.
 656         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 657         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 658         (parse_uslo16): Likewise.
 659         (parse_uhi16): Parse gothi and gotfuncdeschi.
 660         (parse_d12): Parse got12 and gotfuncdesc12.
 661         (parse_s12): Likewise.
 662
 663 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 664
 665         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 666         instruction which looks similar to an 'rla' instruction.
 667
 668 For older changes see ChangeLog-0203
 669 \f
 670 Local Variables:
 671 mode: change-log
 672 left-margin: 8
 673 fill-column: 74
 674 version-control: never
 675 End: