opcodes/ChangeLog

   1 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
   4         * i386-init.h: Regenerated.
   5
   6 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
   7
   8         * opcodes/arc-dis.c (print_insn_arc): Changed.
   9
  10 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  11
  12         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
  13         camellia_fl.
  14
  15 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  16
  17         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
  18         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
  19         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
  20
  21 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
  24         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
  25         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
  26         PREFIX_MOD_3_0FAE_REG_4.
  27         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
  28         PREFIX_MOD_3_0FAE_REG_4.
  29         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
  30         (cpu_flags): Add CpuPTWRITE.
  31         * i386-opc.h (CpuPTWRITE): New.
  32         (i386_cpu_flags): Add cpuptwrite.
  33         * i386-opc.tbl: Add ptwrite instruction.
  34         * i386-init.h: Regenerated.
  35         * i386-tbl.h: Likewise.
  36
  37 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  38
  39         * arc-dis.h: Wrap around in extern "C".
  40
  41 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  42
  43         * aarch64-tbl.h (V8_2_INSN): New macro.
  44         (aarch64_opcode_table): Use it.
  45
  46 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  47
  48         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
  49         CORE_INSN, __FP_INSN and SIMD_INSN.
  50
  51 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  52
  53         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
  54         (aarch64_opcode_table): Update uses accordingly.
  55
  56 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
  57         Kwok Cheung Yeung  <kcy@codesourcery.com>
  58
  59         opcodes/
  60         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
  61         'e_cmplwi' to 'e_cmpli' instead.
  62         (OPVUPRT, OPVUPRT_MASK): Define.
  63         (powerpc_opcodes): Add E200Z4 insns.
  64         (vle_opcodes): Add context save/restore insns.
  65
  66 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
  67
  68         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
  69         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
  70         "j".
  71
  72 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
  73
  74         * arc-nps400-tbl.h: Change block comments to GNU format.
  75         * arc-dis.c: Add new globals addrtypenames,
  76         addrtypenames_max, and addtypeunknown.
  77         (get_addrtype): New function.
  78         (print_insn_arc): Print colons and address types when
  79         required.
  80         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
  81         define insert and extract functions for all address types.
  82         (arc_operands): Add operands for colon and all address
  83         types.
  84         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
  85         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
  86         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
  87         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
  88         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
  89         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
  90
  91 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         * configure: Regenerated.
  94
  95 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
  96
  97         * arc-dis.c (skipclass): New structure.
  98         (decodelist): New variable.
  99         (is_compatible_p): New function.
 100         (new_element): Likewise.
 101         (skip_class_p): Likewise.
 102         (find_format_from_table): Use skip_class_p function.
 103         (find_format): Decode first the extension instructions.
 104         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 105         e_flags.
 106         (parse_option): New function.
 107         (parse_disassembler_options): Likewise.
 108         (print_arc_disassembler_options): Likewise.
 109         (print_insn_arc): Use parse_disassembler_options function.  Proper
 110         select ARCv2 cpu variant.
 111         * disassemble.c (disassembler_usage): Add ARC disassembler
 112         options.
 113
 114 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 115
 116         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 117         annotation from the "nal" entry and reorder it beyond "bltzal".
 118
 119 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 120
 121         * sparc-opc.c (ldtxa): New macro.
 122         (sparc_opcodes): Use the macro defined above to add entries for
 123         the LDTXA instructions.
 124         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 125         instruction.
 126
 127 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 128
 129         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 130         and "jmpc".
 131
 132 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 133
 134         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 135         (movzb): Adjust to cover all permitted suffixes.
 136         (movzw): New.
 137         * i386-tbl.h: Re-generate.
 138
 139 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 140
 141         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 142         (lgdt): Remove Tbyte from non-64-bit variant.
 143         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 144         xsaves64, xsavec64): Remove Disp16.
 145         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 146         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 147         64-bit variants.
 148         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 149         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 150         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 151         64-bit variants.
 152         * i386-tbl.h: Re-generate.
 153
 154 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 157         * i386-tbl.h: Re-generate.
 158
 159 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 160
 161         * arm-dis.c (print_insn): Fix typo in comment.
 162
 163 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 164
 165         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 166         range of ldst_elemlist operands.
 167         (print_register_list): Use PRIi64 to print the index.
 168         (aarch64_print_operand): Likewise.
 169
 170 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 171
 172         * mcore-opc.h: Remove sentinal.
 173         * mcore-dis.c (print_insn_mcore): Adjust.
 174
 175 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 176
 177         * arc-opc.c: Correct description of availability of NPS400
 178         features.
 179
 180 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 181
 182         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 183         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 184         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 185         xor3>: New mnemonics.
 186         <setb>: Change to a VX form instruction.
 187         (insert_sh6): Add support for rldixor.
 188         (extract_sh6): Likewise.
 189
 190 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 191
 192         * arc-ext.h: Wrap in extern C.
 193
 194 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 195
 196         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 197         Use same method for determining instruction length on ARC700 and
 198         NPS-400.
 199         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 200         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 201         with the NPS400 subclass.
 202         * arc-opc.c: Likewise.
 203
 204 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 205
 206         * sparc-opc.c (rdasr): New macro.
 207         (wrasr): Likewise.
 208         (rdpr): Likewise.
 209         (wrpr): Likewise.
 210         (rdhpr): Likewise.
 211         (wrhpr): Likewise.
 212         (sparc_opcodes): Use the macros above to fix and expand the
 213         definition of read/write instructions from/to
 214         asr/privileged/hyperprivileged instructions.
 215         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 216         %hva_mask_nz.  Prefer softint_set and softint_clear over
 217         set_softint and clear_softint.
 218         (print_insn_sparc): Support %ver in Rd.
 219
 220 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 221
 222         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 223         architecture according to the hardware capabilities they require.
 224
 225 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 226
 227         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 228         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 229         bfd_mach_sparc_v9{c,d,e,v,m}.
 230         * sparc-opc.c (MASK_V9C): Define.
 231         (MASK_V9D): Likewise.
 232         (MASK_V9E): Likewise.
 233         (MASK_V9V): Likewise.
 234         (MASK_V9M): Likewise.
 235         (v6): Add MASK_V9{C,D,E,V,M}.
 236         (v6notlet): Likewise.
 237         (v7): Likewise.
 238         (v8): Likewise.
 239         (v9): Likewise.
 240         (v9andleon): Likewise.
 241         (v9a): Likewise.
 242         (v9b): Likewise.
 243         (v9c): Define.
 244         (v9d): Likewise.
 245         (v9e): Likewise.
 246         (v9v): Likewise.
 247         (v9m): Likewise.
 248         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 249
 250 2016-06-15  Nick Clifton  <nickc@redhat.com>
 251
 252         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 253         constants to match expected behaviour.
 254         (nds32_parse_opcode): Likewise.  Also for whitespace.
 255
 256 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 257
 258         * arc-opc.c (extract_rhv1): Extract value from insn.
 259
 260 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 261
 262         * arc-nps400-tbl.h: Add ldbit instruction.
 263         * arc-opc.c: Add flag classes required for ldbit.
 264
 265 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 266
 267         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 268         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 269         support the above instructions.
 270
 271 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 272
 273         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 274         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 275         csma, cbba, zncv, and hofs.
 276         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 277         support the above instructions.
 278
 279 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 280
 281         * arc-nps400-tbl.h: Add andab and orab instructions.
 282
 283 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 284
 285         * arc-nps400-tbl.h: Add addl-like instructions.
 286
 287 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 288
 289         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 290
 291 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 292
 293         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 294         instructions.
 295
 296 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 297
 298         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 299         variable.
 300         (init_disasm): Handle new command line option "insnlength".
 301         (print_s390_disassembler_options): Mention new option in help
 302         output.
 303         (print_insn_s390): Use the encoded insn length when dumping
 304         unknown instructions.
 305
 306 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 307
 308         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 309          to the address and set as symbol address for LDS/ STS immediate operands.
 310
 311 2016-06-07  Alan Modra  <amodra@gmail.com>
 312
 313         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 314         cpu for "vle" to e500.
 315         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 316         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 317         (PPCNONE): Delete, substitute throughout.
 318         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 319         except for major opcode 4 and 31.
 320         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 321
 322 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 323
 324         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 325         ARM_EXT_RAS in relevant entries.
 326
 327 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 328
 329         PR binutils/20196
 330         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 331         opcodes for E6500.
 332
 333 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         PR binutis/18386
 336         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 337         (indir_v_mode): New.
 338         Add comments for '&'.
 339         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 340         (putop): Handle '&'.
 341         (intel_operand_size): Handle indir_v_mode.
 342         (OP_E_register): Likewise.
 343         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 344         64-bit indirect call/jmp for AMD64.
 345         * i386-tbl.h: Regenerated
 346
 347 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 348
 349         * arc-dis.c (struct arc_operand_iterator): New structure.
 350         (find_format_from_table): All the old content from find_format,
 351         with some minor adjustments, and parameter renaming.
 352         (find_format_long_instructions): New function.
 353         (find_format): Rewritten.
 354         (arc_insn_length): Add LSB parameter.
 355         (extract_operand_value): New function.
 356         (operand_iterator_next): New function.
 357         (print_insn_arc): Use new functions to find opcode, and iterator
 358         over operands.
 359         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 360         (extract_nps_3bit_dst_short): New function.
 361         (insert_nps_3bit_src2_short): New function.
 362         (extract_nps_3bit_src2_short): New function.
 363         (insert_nps_bitop1_size): New function.
 364         (extract_nps_bitop1_size): New function.
 365         (insert_nps_bitop2_size): New function.
 366         (extract_nps_bitop2_size): New function.
 367         (insert_nps_bitop_mod4_msb): New function.
 368         (extract_nps_bitop_mod4_msb): New function.
 369         (insert_nps_bitop_mod4_lsb): New function.
 370         (extract_nps_bitop_mod4_lsb): New function.
 371         (insert_nps_bitop_dst_pos3_pos4): New function.
 372         (extract_nps_bitop_dst_pos3_pos4): New function.
 373         (insert_nps_bitop_ins_ext): New function.
 374         (extract_nps_bitop_ins_ext): New function.
 375         (arc_operands): Add new operands.
 376         (arc_long_opcodes): New global array.
 377         (arc_num_long_opcodes): New global.
 378         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 379
 380 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 381
 382         * nds32-asm.h: Add extern "C".
 383         * sh-opc.h: Likewise.
 384
 385 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 386
 387         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 388         0,b,limm to the rflt instruction.
 389
 390 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 391
 392         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 393         constant.
 394
 395 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         PR gas/20145
 398         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 399         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 400         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 401         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 402         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 403         * i386-init.h: Regenerated.
 404
 405 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 406
 407         PR gas/20145
 408         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 409         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 410         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 411         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 412         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 413         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 414         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 415         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 416         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 417         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 418         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 419         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 420         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 421         CpuRegMask for AVX512.
 422         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 423         and CpuRegMask.
 424         (set_bitfield_from_cpu_flag_init): New function.
 425         (set_bitfield): Remove const on f.  Call
 426         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 427         * i386-opc.h (CpuRegMMX): New.
 428         (CpuRegXMM): Likewise.
 429         (CpuRegYMM): Likewise.
 430         (CpuRegZMM): Likewise.
 431         (CpuRegMask): Likewise.
 432         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 433         and cpuregmask.
 434         * i386-init.h: Regenerated.
 435         * i386-tbl.h: Likewise.
 436
 437 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         PR gas/20154
 440         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 441         (opcode_modifiers): Add AMD64 and Intel64.
 442         (main): Properly verify CpuMax.
 443         * i386-opc.h (CpuAMD64): Removed.
 444         (CpuIntel64): Likewise.
 445         (CpuMax): Set to CpuNo64.
 446         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 447         (AMD64): New.
 448         (Intel64): Likewise.
 449         (i386_opcode_modifier): Add amd64 and intel64.
 450         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 451         on call and jmp.
 452         * i386-init.h: Regenerated.
 453         * i386-tbl.h: Likewise.
 454
 455 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         PR gas/20154
 458         * i386-gen.c (main): Fail if CpuMax is incorrect.
 459         * i386-opc.h (CpuMax): Set to CpuIntel64.
 460         * i386-tbl.h: Regenerated.
 461
 462 2016-05-27  Nick Clifton  <nickc@redhat.com>
 463
 464         PR target/20150
 465         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 466         (msp430dis_opcode_unsigned): New function.
 467         (msp430dis_opcode_signed): New function.
 468         (msp430_singleoperand): Use the new opcode reading functions.
 469         Only disassenmble bytes if they were successfully read.
 470         (msp430_doubleoperand): Likewise.
 471         (msp430_branchinstr): Likewise.
 472         (msp430x_callx_instr): Likewise.
 473         (print_insn_msp430): Check that it is safe to read bytes before
 474         attempting disassembly.  Use the new opcode reading functions.
 475
 476 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 477
 478         * ppc-opc.c (CY): New define.  Document it.
 479         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 480
 481 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 482
 483         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 484         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 485         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 486         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 487         CPU_ANY_AVX_FLAGS.
 488         * i386-init.h: Regenerated.
 489
 490 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 491
 492         PR gas/20141
 493         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 494         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 495         * i386-init.h: Regenerated.
 496
 497 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 498
 499         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 500         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 501         * i386-init.h: Regenerated.
 502
 503 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 504
 505         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 506         information.
 507         (print_insn_arc): Set insn_type information.
 508         * arc-opc.c (C_CC): Add F_CLASS_COND.
 509         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 510         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 511         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 512         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 513         (brne, brne_s, jeq_s, jne_s): Likewise.
 514
 515 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 516
 517         * arc-tbl.h (neg): New instruction variant.
 518
 519 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 520
 521         * arc-dis.c (find_format, find_format, get_auxreg)
 522         (print_insn_arc): Changed.
 523         * arc-ext.h (INSERT_XOP): Likewise.
 524
 525 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 526
 527         * tic54x-dis.c (sprint_mmr): Adjust.
 528         * tic54x-opc.c: Likewise.
 529
 530 2016-05-19  Alan Modra  <amodra@gmail.com>
 531
 532         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 533
 534 2016-05-19  Alan Modra  <amodra@gmail.com>
 535
 536         * ppc-opc.c: Formatting.
 537         (NSISIGNOPT): Define.
 538         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 539
 540 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 541
 542         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 543         replacing references to `micromips_ase' throughout.
 544         (_print_insn_mips): Don't use file-level microMIPS annotation to
 545         determine the disassembly mode with the symbol table.
 546
 547 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 548
 549         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 550
 551 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 552
 553         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 554         mips64r6.
 555         * mips-opc.c (D34): New macro.
 556         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 557
 558 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 559
 560         * i386-dis.c (prefix_table): Add RDPID instruction.
 561         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 562         (cpu_flags): Add RDPID bitfield.
 563         * i386-opc.h (enum): Add RDPID element.
 564         (i386_cpu_flags): Add RDPID field.
 565         * i386-opc.tbl: Add RDPID instruction.
 566         * i386-init.h: Regenerate.
 567         * i386-tbl.h: Regenerate.
 568
 569 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 570
 571         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 572         branch type of a symbol.
 573         (print_insn): Likewise.
 574
 575 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 576
 577         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 578         Mainline Security Extensions instructions.
 579         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 580         Extensions instructions.
 581         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 582         instructions.
 583         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 584         special registers.
 585
 586 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 587
 588         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 589
 590 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 591
 592         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 593         (arcExtMap_genOpcode): Likewise.
 594         * arc-opc.c (arg_32bit_rc): Define new variable.
 595         (arg_32bit_u6): Likewise.
 596         (arg_32bit_limm): Likewise.
 597
 598 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 599
 600         * aarch64-gen.c (VERIFIER): Define.
 601         * aarch64-opc.c (VERIFIER): Define.
 602         (verify_ldpsw): Use static linkage.
 603         * aarch64-opc.h (verify_ldpsw): Remove.
 604         * aarch64-tbl.h: Use VERIFIER for verifiers.
 605
 606 2016-04-28  Nick Clifton  <nickc@redhat.com>
 607
 608         PR target/19722
 609         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 610         * aarch64-opc.c (verify_ldpsw): New function.
 611         * aarch64-opc.h (verify_ldpsw): New prototype.
 612         * aarch64-tbl.h: Add initialiser for verifier field.
 613         (LDPSW): Set verifier to verify_ldpsw.
 614
 615 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 616
 617         PR binutils/19983
 618         PR binutils/19984
 619         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 620         smaller than address size.
 621
 622 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 623
 624         * alpha-dis.c: Regenerate.
 625         * crx-dis.c: Likewise.
 626         * disassemble.c: Likewise.
 627         * epiphany-opc.c: Likewise.
 628         * fr30-opc.c: Likewise.
 629         * frv-opc.c: Likewise.
 630         * ip2k-opc.c: Likewise.
 631         * iq2000-opc.c: Likewise.
 632         * lm32-opc.c: Likewise.
 633         * lm32-opinst.c: Likewise.
 634         * m32c-opc.c: Likewise.
 635         * m32r-opc.c: Likewise.
 636         * m32r-opinst.c: Likewise.
 637         * mep-opc.c: Likewise.
 638         * mt-opc.c: Likewise.
 639         * or1k-opc.c: Likewise.
 640         * or1k-opinst.c: Likewise.
 641         * tic80-opc.c: Likewise.
 642         * xc16x-opc.c: Likewise.
 643         * xstormy16-opc.c: Likewise.
 644
 645 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 646
 647         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 648         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 649         calcsd, and calcxd instructions.
 650         * arc-opc.c (insert_nps_bitop_size): Delete.
 651         (extract_nps_bitop_size): Delete.
 652         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 653         (extract_nps_qcmp_m3): Define.
 654         (extract_nps_qcmp_m2): Define.
 655         (extract_nps_qcmp_m1): Define.
 656         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 657         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 658         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 659         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 660         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 661         NPS_QCMP_M3.
 662
 663 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 664
 665         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 666
 667 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 668
 669         * Makefile.in: Regenerated with automake 1.11.6.
 670         * aclocal.m4: Likewise.
 671
 672 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 673
 674         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 675         instructions.
 676         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 677         (extract_nps_cmem_uimm16): New function.
 678         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 679
 680 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 681
 682         * arc-dis.c (arc_insn_length): New function.
 683         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 684         (find_format): Change insnLen parameter to unsigned.
 685
 686 2016-04-13  Nick Clifton  <nickc@redhat.com>
 687
 688         PR target/19937
 689         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 690         the LD.B and LD.BU instructions.
 691
 692 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 693
 694         * arc-dis.c (find_format): Check for extension flags.
 695         (print_flags): New function.
 696         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 697         .extAuxRegister.
 698         * arc-ext.c (arcExtMap_coreRegName): Use
 699         LAST_EXTENSION_CORE_REGISTER.
 700         (arcExtMap_coreReadWrite): Likewise.
 701         (dump_ARC_extmap): Update printing.
 702         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 703         (arc_aux_regs): Add cpu field.
 704         * arc-regs.h: Add cpu field, lower case name aux registers.
 705
 706 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 707
 708         * arc-tbl.h: Add rtsc, sleep with no arguments.
 709
 710 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 711
 712         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 713         Initialize.
 714         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 715         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 716         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 717         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 718         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 719         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 720         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 721         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 722         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 723         (arc_opcode arc_opcodes): Null terminate the array.
 724         (arc_num_opcodes): Remove.
 725         * arc-ext.h (INSERT_XOP): Define.
 726         (extInstruction_t): Likewise.
 727         (arcExtMap_instName): Delete.
 728         (arcExtMap_insn): New function.
 729         (arcExtMap_genOpcode): Likewise.
 730         * arc-ext.c (ExtInstruction): Remove.
 731         (create_map): Zero initialize instruction fields.
 732         (arcExtMap_instName): Remove.
 733         (arcExtMap_insn): New function.
 734         (dump_ARC_extmap): More info while debuging.
 735         (arcExtMap_genOpcode): New function.
 736         * arc-dis.c (find_format): New function.
 737         (print_insn_arc): Use find_format.
 738         (arc_get_disassembler): Enable dump_ARC_extmap only when
 739         debugging.
 740
 741 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 742
 743         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 744         instruction bits out.
 745
 746 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 747
 748         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 749         * arc-opc.c (arc_flag_operands): Add new flags.
 750         (arc_flag_classes): Add new classes.
 751
 752 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 753
 754         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 755
 756 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 757
 758         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 759         encode1, rflt, crc16, and crc32 instructions.
 760         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 761         (arc_flag_classes): Add C_NPS_R.
 762         (insert_nps_bitop_size_2b): New function.
 763         (extract_nps_bitop_size_2b): Likewise.
 764         (insert_nps_bitop_uimm8): Likewise.
 765         (extract_nps_bitop_uimm8): Likewise.
 766         (arc_operands): Add new operand entries.
 767
 768 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 769
 770         * arc-regs.h: Add a new subclass field.  Add double assist
 771         accumulator register values.
 772         * arc-tbl.h: Use DPA subclass to mark the double assist
 773         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 774         * arc-opc.c (RSP): Define instead of SP.
 775         (arc_aux_regs): Add the subclass field.
 776
 777 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 778
 779         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 780
 781 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 782
 783         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 784         NPS_R_SRC1.
 785
 786 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 787
 788         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 789         issues.  No functional changes.
 790
 791 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 792
 793         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 794         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 795         (RTT): Remove duplicate.
 796         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 797         (PCT_CONFIG*): Remove.
 798         (D1L, D1H, D2H, D2L): Define.
 799
 800 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 801
 802         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 803
 804 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 805
 806         * arc-tbl.h (invld07): Remove.
 807         * arc-ext-tbl.h: New file.
 808         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 809         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 810
 811 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 812
 813         Fix -Wstack-usage warnings.
 814         * aarch64-dis.c (print_operands): Substitute size.
 815         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 816
 817 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 818
 819         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 820         to get a proper diagnostic when an invalid ASR register is used.
 821
 822 2016-03-22  Nick Clifton  <nickc@redhat.com>
 823
 824         * configure: Regenerate.
 825
 826 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 827
 828         * arc-nps400-tbl.h: New file.
 829         * arc-opc.c: Add top level comment.
 830         (insert_nps_3bit_dst): New function.
 831         (extract_nps_3bit_dst): New function.
 832         (insert_nps_3bit_src2): New function.
 833         (extract_nps_3bit_src2): New function.
 834         (insert_nps_bitop_size): New function.
 835         (extract_nps_bitop_size): New function.
 836         (arc_flag_operands): Add nps400 entries.
 837         (arc_flag_classes): Add nps400 entries.
 838         (arc_operands): Add nps400 entries.
 839         (arc_opcodes): Add nps400 include.
 840
 841 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 842
 843         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 844         the new class enum values.
 845
 846 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 847
 848         * arc-dis.c (print_insn_arc): Handle nps400.
 849
 850 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 851
 852         * arc-opc.c (BASE): Delete.
 853
 854 2016-03-18  Nick Clifton  <nickc@redhat.com>
 855
 856         PR target/19721
 857         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 858         of MOV insn that aliases an ORR insn.
 859
 860 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 861
 862         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 863
 864 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 865
 866         * mcore-opc.h: Add const qualifiers.
 867         * microblaze-opc.h (struct op_code_struct): Likewise.
 868         * sh-opc.h: Likewise.
 869         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 870         (tic4x_print_op): Likewise.
 871
 872 2016-03-02  Alan Modra  <amodra@gmail.com>
 873
 874         * or1k-desc.h: Regenerate.
 875         * fr30-ibld.c: Regenerate.
 876         * rl78-decode.c: Regenerate.
 877
 878 2016-03-01  Nick Clifton  <nickc@redhat.com>
 879
 880         PR target/19747
 881         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 882
 883 2016-02-24  Renlin Li  <renlin.li@arm.com>
 884
 885         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 886         (print_insn_coprocessor): Support fp16 instructions.
 887
 888 2016-02-24  Renlin Li  <renlin.li@arm.com>
 889
 890         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 891         vminnm, vrint(mpna).
 892
 893 2016-02-24  Renlin Li  <renlin.li@arm.com>
 894
 895         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 896         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 897
 898 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         * i386-dis.c (print_insn): Parenthesize expression to prevent
 901         truncated addresses.
 902         (OP_J): Likewise.
 903
 904 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 905             Janek van Oirschot  <jvanoirs@synopsys.com>
 906
 907         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 908         variable.
 909
 910 2016-02-04  Nick Clifton  <nickc@redhat.com>
 911
 912         PR target/19561
 913         * msp430-dis.c (print_insn_msp430): Add a special case for
 914         decoding an RRC instruction with the ZC bit set in the extension
 915         word.
 916
 917 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 918
 919         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 920         * epiphany-ibld.c: Regenerate.
 921         * fr30-ibld.c: Regenerate.
 922         * frv-ibld.c: Regenerate.
 923         * ip2k-ibld.c: Regenerate.
 924         * iq2000-ibld.c: Regenerate.
 925         * lm32-ibld.c: Regenerate.
 926         * m32c-ibld.c: Regenerate.
 927         * m32r-ibld.c: Regenerate.
 928         * mep-ibld.c: Regenerate.
 929         * mt-ibld.c: Regenerate.
 930         * or1k-ibld.c: Regenerate.
 931         * xc16x-ibld.c: Regenerate.
 932         * xstormy16-ibld.c: Regenerate.
 933
 934 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 935
 936         * epiphany-dis.c: Regenerated from latest cpu files.
 937
 938 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 939
 940         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 941         test bit.
 942
 943 2016-01-25  Renlin Li  <renlin.li@arm.com>
 944
 945         * arm-dis.c (mapping_symbol_for_insn): New function.
 946         (find_ifthen_state): Call mapping_symbol_for_insn().
 947
 948 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 949
 950         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 951         of MSR UAO immediate operand.
 952
 953 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 954
 955         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 956         instruction support.
 957
 958 2016-01-17  Alan Modra  <amodra@gmail.com>
 959
 960         * configure: Regenerate.
 961
 962 2016-01-14  Nick Clifton  <nickc@redhat.com>
 963
 964         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 965         instructions that can support stack pointer operations.
 966         * rl78-decode.c: Regenerate.
 967         * rl78-dis.c: Fix display of stack pointer in MOVW based
 968         instructions.
 969
 970 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 971
 972         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 973         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 974         erxtatus_el1 and erxaddr_el1.
 975
 976 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 977
 978         * arm-dis.c (arm_opcodes): Add "esb".
 979         (thumb_opcodes): Likewise.
 980
 981 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 982
 983         * ppc-opc.c <xscmpnedp>: Delete.
 984         <xvcmpnedp>: Likewise.
 985         <xvcmpnedp.>: Likewise.
 986         <xvcmpnesp>: Likewise.
 987         <xvcmpnesp.>: Likewise.
 988
 989 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 990
 991         PR gas/13050
 992         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 993         addition to ISA_A.
 994
 995 2016-01-01  Alan Modra  <amodra@gmail.com>
 996
 997         Update year range in copyright notice of all files.
 998
 999 For older changes see ChangeLog-2015
1000 \f
1001 Copyright (C) 2016 Free Software Foundation, Inc.
1002
1003 Copying and distribution of this file, with or without modification,
1004 are permitted in any medium without royalty provided the copyright
1005 notice and this notice are preserved.
1006
1007 Local Variables:
1008 mode: change-log
1009 left-margin: 8
1010 fill-column: 74
1011 version-control: never
1012 End: