opcodes/ChangeLog

   1 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-asm-2.c: Regenerate.
   4         * aarch64-dis-2.c: Regenerate.
   5         * aarch64-opc-2.c: Regenerate.
   6         * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
   7         (QL_S_2SAMEH): New.
   8         (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
   9         fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
  10         frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
  11         fcvtzu and frsqrte to the scalar two register misc. group.
  12
  13 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  14
  15         * aarch64-asm-2.c: Regenerate.
  16         * aarch64-dis-2.c: Regenerate.
  17         * aarch64-opc-2.c: Regenerate.
  18         * aarch64-tbl.h (QL_V2SAMEH): New.
  19         (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
  20         fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
  21         frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
  22         fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
  23         and fsqrt to the vector register misc. group.
  24
  25 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  26
  27         * aarch64-asm-2.c: Regenerate.
  28         * aarch64-dis-2.c: Regenerate.
  29         * aarch64-opc-2.c: Regenerate.
  30         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
  31         fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
  32         to the scalar three same group.
  33
  34 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  35
  36         * aarch64-asm-2.c: Regenerate.
  37         * aarch64-dis-2.c: Regenerate.
  38         * aarch64-opc-2.c: Regenerate.
  39         * aarch64-tbl.h (QL_V3SAMEH): New.
  40         (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
  41         fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
  42         fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
  43         fcmgt, facgt and fminp to the vector three same group.
  44
  45 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  46
  47         * aarch64-tbl.h (aarch64_feature_simd_f16): New.
  48         (SIMD_F16): New.
  49
  50 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  51
  52         * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
  53         removed statement.
  54         (aarch64_pstatefield_supported_p): Move feature checks for AT
  55         registers ..
  56         (aarch64_sys_ins_reg_supported_p): .. to here.
  57
  58 2015-12-12  Alan Modra  <amodra@gmail.com>
  59
  60         PR 19359
  61         * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
  62         (powerpc_opcodes): Remove single-operand mfcr.
  63
  64 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  65
  66         * aarch64-asm.c (aarch64_ins_hint): New.
  67         * aarch64-asm.h (aarch64_ins_hint): Declare.
  68         * aarch64-dis.c (aarch64_ext_hint): New.
  69         * aarch64-dis.h (aarch64_ext_hint): Declare.
  70         * aarch64-opc-2.c: Regenerate.
  71         * aarch64-opc.c (aarch64_hint_options): New.
  72         * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
  73
  74 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  75
  76         * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
  77
  78 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  79
  80         * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
  81         pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
  82         pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
  83         pmscr_el2.
  84         (aarch64_sys_reg_supported_p): Add architecture feature tests for
  85         the new registers.
  86
  87 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  88
  89         * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
  90         (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
  91         feature test for "s1e1rp" and "s1e1wp".
  92
  93 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  94
  95         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
  96         (aarch64_sys_ins_reg_supported_p): New.
  97
  98 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  99
 100         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
 101         with aarch64_sys_ins_reg_has_xt.
 102         (aarch64_ext_sysins_op): Likewise.
 103         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
 104         (F_HASXT): New.
 105         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
 106         (aarch64_sys_regs_dc): Likewise.
 107         (aarch64_sys_regs_at): Likewise.
 108         (aarch64_sys_regs_tlbi): Likewise.
 109         (aarch64_sys_ins_reg_has_xt): New.
 110
 111 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 112
 113         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
 114         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
 115         (aarch64_pstatefields): Add "uao".
 116         (aarch64_pstatefield_supported_p): Add checks for "uao".
 117
 118 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 119
 120         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
 121         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
 122         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
 123         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 124         new registers.
 125
 126 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 127
 128         * aarch64-asm-2.c: Regenerate.
 129         * aarch64-dis-2.c: Regenerate.
 130         * aarch64-tbl.h (aarch64_feature_ras): New.
 131         (RAS): New.
 132         (aarch64_opcode_table): Add "esb".
 133
 134 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
 135
 136         * i386-dis.c (MOD_0F01_REG_5): New.
 137         (RM_0F01_REG_5): Likewise.
 138         (reg_table): Use MOD_0F01_REG_5.
 139         (mod_table): Add MOD_0F01_REG_5.
 140         (rm_table): Add RM_0F01_REG_5.
 141         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
 142         (cpu_flags): Add CpuOSPKE.
 143         * i386-opc.h (CpuOSPKE): New.
 144         (i386_cpu_flags): Add cpuospke.
 145         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
 146         * i386-init.h: Regenerated.
 147         * i386-tbl.h: Likewise.
 148
 149 2015-12-07  DJ Delorie  <dj@redhat.com>
 150
 151         * rl78-decode.opc: Enable MULU for all ISAs.
 152         * rl78-decode.c: Regenerate.
 153
 154 2015-12-07  Alan Modra  <amodra@gmail.com>
 155
 156         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
 157         major opcode/xop.
 158
 159 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 160
 161         * arc-dis.c (special_flag_p): Match full mnemonic.
 162         * arc-opc.c (print_insn_arc): Check section size to read
 163         appropriate number of bytes. Fix printing.
 164         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
 165         arguments.
 166
 167 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 168
 169         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
 170         <ldah>: ... to this.
 171
 172 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 173
 174         * aarch64-asm-2.c: Regenerate.
 175         * aarch64-dis-2.c: Regenerate.
 176         * aarch64-opc-2.c: Regenerate.
 177         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
 178         (QL_INT2FP_H, QL_FP2INT_H): New.
 179         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
 180         (QL_DST_H): New.
 181         (QL_FCCMP_H): New.
 182         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
 183         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
 184         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
 185         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
 186         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
 187         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
 188         fcsel.
 189
 190 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 191
 192         * aarch64-opc.c (half_conv_t): New.
 193         (expand_fp_imm): Replace is_dp flag with the parameter size to
 194         specify the number of bytes for the required expansion.  Treat
 195         a 16-bit expansion like a 32-bit expansion.  Add check for an
 196         unsupported size request.  Update comment.
 197         (aarch64_print_operand): Update to support 16-bit floating point
 198         values.  Update for changes to expand_fp_imm.
 199
 200 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 201
 202         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 203         (FP_F16): New.
 204
 205 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 206
 207         * aarch64-asm-2.c: Regenerate.
 208         * aarch64-dis-2.c: Regenerate.
 209         * aarch64-opc-2.c: Regenerate.
 210         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 211         "rev64".
 212
 213 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 214
 215         * aarch64-asm-2.c: Regenerate.
 216         * aarch64-asm.c (convert_bfc_to_bfm): New.
 217         (convert_to_real): Add case for OP_BFC.
 218         * aarch64-dis-2.c: Regenerate.
 219         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 220         (convert_to_alias): Add case for OP_BFC.
 221         * aarch64-opc-2.c: Regenerate.
 222         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 223         to allow width operand in three-operand instructions.
 224         * aarch64-tbl.h (QL_BF1): New.
 225         (aarch64_feature_v8_2): New.
 226         (ARMV8_2): New.
 227         (aarch64_opcode_table): Add "bfc".
 228
 229 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 230
 231         * aarch64-asm-2.c: Regenerate.
 232         * aarch64-dis-2.c: Regenerate.
 233         * aarch64-dis.c: Weaken assert.
 234         * aarch64-gen.c: Include the instruction in the list of its
 235         possible aliases.
 236
 237 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 238
 239         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 240         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 241         feature test.
 242
 243 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 244
 245         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 246
 247 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 248
 249         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 250         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 251         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 252         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 253         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 254         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 255         cnthv_ctl_el2, cnthv_cval_el2.
 256         (aarch64_sys_reg_supported_p): Update for the new system
 257         registers.
 258
 259 2015-11-20  Nick Clifton  <nickc@redhat.com>
 260
 261         PR binutils/19224
 262         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 263
 264 2015-11-20  Nick Clifton  <nickc@redhat.com>
 265
 266         * po/zh_CN.po: Updated simplified Chinese translation.
 267
 268 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 269
 270         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 271         of MSR PAN immediate operand.
 272
 273 2015-11-16  Nick Clifton  <nickc@redhat.com>
 274
 275         * rx-dis.c (condition_names): Replace always and never with
 276         invalid, since the always/never conditions can never be legal.
 277
 278 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 279
 280         * configure: Regenerate.
 281
 282 2015-11-11  Alan Modra  <amodra@gmail.com>
 283             Peter Bergner <bergner@vnet.ibm.com>
 284
 285         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 286         Add PPC_OPCODE_VSX3 to the vsx entry.
 287         (powerpc_init_dialect): Set default dialect to power9.
 288         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 289         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 290         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 291         (insert_esync): Test for illegal L operand value.
 292         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 293         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 294         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 295         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 296         PPCVSX3): New defines.
 297         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 298         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 299         <mcrxr>: Use XBFRARB_MASK.
 300         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 301         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 302         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 303         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 304         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 305         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 306         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 307         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 308         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 309         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 310         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 311         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 312         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 313         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 314         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 315         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 316         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 317         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 318         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 319         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 320         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 321         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 322         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 323         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 324         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 325         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 326         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 327         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 328         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 329         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 330         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 331         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 332
 333 2015-11-02  Nick Clifton  <nickc@redhat.com>
 334
 335         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 336         instructions.
 337         * rx-decode.c: Regenerate.
 338
 339 2015-11-02  Nick Clifton  <nickc@redhat.com>
 340
 341         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 342         type to RX_Operand_Zero_Indirect.
 343         * rx-decode.c: Regenerate.
 344         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 345
 346 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 347
 348         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 349         noaliases_p.  Update comments.  Pass noaliases_p rather than
 350         no_aliases to aarch64_opcode_decode.
 351         (print_insn_aarch64_word): Pass no_aliases to
 352         aarch64_decode_insn.
 353
 354 2015-10-27  Vinay  <Vinay.G@kpit.com>
 355
 356         PR binutils/19159
 357         * rl78-decode.opc (MOV): Added offset to DE register in index
 358         addressing mode.
 359         * rl78-decode.c: Regenerate.
 360
 361 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 362
 363         PR binutils/19158
 364         * rl78-decode.opc: Add 's' print operator to instructions that
 365         access system registers.
 366         * rl78-decode.c: Regenerate.
 367         * rl78-dis.c (print_insn_rl78_common): Decode all system
 368         registers.
 369
 370 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 371
 372         PR binutils/19157
 373         * rl78-decode.opc: Add 'a' print operator to mov instructions
 374         using stack pointer plus index addressing.
 375         * rl78-decode.c: Regenerate.
 376
 377 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 378
 379         * s390-opc.c: Fix comment.
 380         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 381         trtt to RRF_U0RER since the second parameter does not need to be a
 382         register pair.
 383
 384 2015-10-08  Nick Clifton  <nickc@redhat.com>
 385
 386         * arc-dis.c (print_insn_arc): Initiallise insn array.
 387
 388 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 389
 390         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 391         'name' rather than 'template'.
 392         * aarch64-opc.c (aarch64_print_operand): Likewise.
 393
 394 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 395
 396         * arc-dis.c: Revamped file for ARC support
 397         * arc-dis.h: Likewise.
 398         * arc-ext.c: Likewise.
 399         * arc-ext.h: Likewise.
 400         * arc-opc.c: Likewise.
 401         * arc-fxi.h: New file.
 402         * arc-regs.h: Likewise.
 403         * arc-tbl.h: Likewise.
 404
 405 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 406
 407         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 408         argument insn type to aarch64_insn.  Rename to ...
 409         (aarch64_decode_insn): ... it.
 410         (print_insn_aarch64_word): Caller updated.
 411
 412 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 413
 414         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 415         (print_insn_aarch64_word): Caller updated.
 416
 417 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 418
 419         * s390-mkopc.c (main): Parse htm and vx flag.
 420         * s390-opc.txt: Mark instructions from the hardware transactional
 421         memory and vector facilities with the "htm"/"vx" flag.
 422
 423 2015-09-28  Nick Clifton  <nickc@redhat.com>
 424
 425         * po/de.po: Updated German translation.
 426
 427 2015-09-28  Tom Rix  <tom@bumblecow.com>
 428
 429         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 430
 431 2015-09-23  Nick Clifton  <nickc@redhat.com>
 432
 433         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 434         function.
 435         * tic30-dis.c (print_branch): Likewise.
 436         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 437         value before left shifting.
 438         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 439         * hppa-dis.c (print_insn_hppa): Likewise.
 440         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 441         array.
 442         * msp430-dis.c (msp430_singleoperand): Likewise.
 443         (msp430_doubleoperand): Likewise.
 444         (print_insn_msp430): Likewise.
 445         * nds32-asm.c (parse_operand): Likewise.
 446         * sh-opc.h (MASK): Likewise.
 447         * v850-dis.c (get_operand_value): Likewise.
 448
 449 2015-09-22  Nick Clifton  <nickc@redhat.com>
 450
 451         * rx-decode.opc (bwl): Use RX_Bad_Size.
 452         (sbwl): Likewise.
 453         (ubwl): Likewise.  Rename to ubw.
 454         (uBWL): Rename to uBW.
 455         Replace all references to uBWL with uBW.
 456         * rx-decode.c: Regenerate.
 457         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 458         (opsize_names): Likewise.
 459         (print_insn_rx): Detect and report RX_Bad_Size.
 460
 461 2015-09-22  Anton Blanchard  <anton@samba.org>
 462
 463         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 464
 465 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 466
 467         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 468         %pmcdper.
 469
 470 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 471
 472         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 473
 474 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 475
 476         PR binutils/18257
 477         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 478         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 479         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 480         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 481         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 482         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 483         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 484         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 485         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 486         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 487         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 488         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 489         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 490         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 491         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 492         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 493         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 494         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 495         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 496         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 497         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 498         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 499         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 500         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 501         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 502         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 503         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 504         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 505         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 506         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 507         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 508         (vex_w_table): Replace terminals with MOD_TABLE entries for
 509         most of mask instructions.
 510
 511 2015-08-17  Alan Modra  <amodra@gmail.com>
 512
 513         * cgen.sh: Trim trailing space from cgen output.
 514         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 515         (print_dis_table): Likewise.
 516         * opc2c.c (dump_lines): Likewise.
 517         (orig_filename): Warning fix.
 518         * ia64-asmtab.c: Regenerate.
 519
 520 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 521
 522         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 523         and higher with ARM instruction set will now mark the 26-bit
 524         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 525         (arm_opcodes): Fix for unpredictable nop being recognized as a
 526         teq.
 527
 528 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 529
 530         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 531         based on 'or' is first.
 532         * mips-opc.c (mips_builtin_opcodes): Ditto.
 533
 534 2015-08-11  Nick Clifton  <nickc@redhat.com>
 535
 536         PR 18800
 537         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 538         instruction.
 539
 540 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 541
 542         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 543
 544 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 545
 546         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 547         * i386-init.h: Regenerated.
 548
 549 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 550
 551         PR binutils/13571
 552         * i386-dis.c (MOD_0FC3): New.
 553         (PREFIX_0FC3): Renamed to ...
 554         (PREFIX_MOD_0_0FC3): This.
 555         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 556         (prefix_table): Replace Ma with Ev on movntiS.
 557         (mod_table): Add MOD_0FC3.
 558
 559 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         * configure: Regenerated.
 562
 563 2015-07-23  Alan Modra  <amodra@gmail.com>
 564
 565         PR 18708
 566         * i386-dis.c (get64): Avoid signed integer overflow.
 567
 568 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 569
 570         PR binutils/18631
 571         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 572         "EXEvexHalfBcstXmmq" for the second operand.
 573         (EVEX_W_0F79_P_2): Likewise.
 574         (EVEX_W_0F7A_P_2): Likewise.
 575         (EVEX_W_0F7B_P_2): Likewise.
 576
 577 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 578
 579         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 580         float bitfield format.
 581         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 582         quarter float bitfield format.
 583
 584 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 585
 586         * configure: Regenerated.
 587
 588 2015-07-03  Alan Modra  <amodra@gmail.com>
 589
 590         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 591         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 592         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 593
 594 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 595             Cesar Philippidis  <cesar@codesourcery.com>
 596
 597         * nios2-dis.c (nios2_extract_opcode): New.
 598         (nios2_disassembler_state): New.
 599         (nios2_find_opcode_hash): Use mach parameter to select correct
 600         disassembler state.
 601         (nios2_print_insn_arg): Extend to support new R2 argument letters
 602         and formats.
 603         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 604         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 605         (NIOS2_NUM_OPCODES): Rename to...
 606         (NIOS2_NUM_R1_OPCODES): This.
 607         (nios2_r2_opcodes): New.
 608         (NIOS2_NUM_R2_OPCODES): New.
 609         (nios2_num_r2_opcodes): New.
 610         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 611         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 612         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 613         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 614         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 615
 616 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 617
 618         * i386-dis.c (OP_Mwaitx): New.
 619         (rm_table): Add monitorx/mwaitx.
 620         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 621         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 622         (operand_type_init): Add CpuMWAITX.
 623         * i386-opc.h (CpuMWAITX): New.
 624         (i386_cpu_flags): Add cpumwaitx.
 625         * i386-opc.tbl: Add monitorx and mwaitx.
 626         * i386-init.h: Regenerated.
 627         * i386-tbl.h: Likewise.
 628
 629 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 630
 631         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 632         (insert_esync): New function.
 633         (LS, WC): Use insert_ls.
 634         (ESYNC): Use insert_esync.
 635
 636 2015-06-22  Nick Clifton  <nickc@redhat.com>
 637
 638         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 639         requested region lies beyond it.
 640         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 641         looking for 32-bit insns.
 642         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 643         data.
 644         * sh-dis.c (print_insn_sh): Likewise.
 645         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 646         blocks of instructions.
 647         * vax-dis.c (print_insn_vax): Check that the requested address
 648         does not clash with the stop_vma.
 649
 650 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 651
 652         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 653         * ppc-opc.c (FXM4): Add non-zero optional value.
 654         (TBR): Likewise.
 655         (SXL): Likewise.
 656         (insert_fxm): Handle new default operand value.
 657         (extract_fxm): Likewise.
 658         (insert_tbr): Likewise.
 659         (extract_tbr): Likewise.
 660
 661 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 662
 663         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 664
 665 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 666
 667         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 668
 669 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 670
 671         * ppc-opc.c: Add comment accidentally removed by old commit.
 672         (MTMSRD_L): Delete.
 673
 674 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 675
 676         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 677
 678 2015-06-04  Nick Clifton  <nickc@redhat.com>
 679
 680         PR 18474
 681         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 682
 683 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 684
 685         * arm-dis.c (arm_opcodes): Add "setpan".
 686         (thumb_opcodes): Add "setpan".
 687
 688 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 689
 690         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 691         macros.
 692
 693 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 694
 695         * aarch64-tbl.h (aarch64_feature_rdma): New.
 696         (RDMA): New.
 697         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 698         * aarch64-asm-2.c: Regenerate.
 699         * aarch64-dis-2.c: Regenerate.
 700         * aarch64-opc-2.c: Regenerate.
 701
 702 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 703
 704         * aarch64-tbl.h (aarch64_feature_lor): New.
 705         (LOR): New.
 706         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 707         "stllrb", "stllrh".
 708         * aarch64-asm-2.c: Regenerate.
 709         * aarch64-dis-2.c: Regenerate.
 710         * aarch64-opc-2.c: Regenerate.
 711
 712 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 713
 714         * aarch64-opc.c (F_ARCHEXT): New.
 715         (aarch64_sys_regs): Add "pan".
 716         (aarch64_sys_reg_supported_p): New.
 717         (aarch64_pstatefields): Add "pan".
 718         (aarch64_pstatefield_supported_p): New.
 719
 720 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 721
 722         * i386-tbl.h: Regenerate.
 723
 724 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 725
 726         * i386-dis.c (print_insn): Swap rounding mode specifier and
 727         general purpose register in Intel mode.
 728
 729 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 730
 731         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 732         * i386-tbl.h: Regenerate.
 733
 734 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 735
 736         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 737         * i386-init.h: Regenerated.
 738
 739 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 740
 741         PR binutis/18386
 742         * i386-dis.c: Add comments for '@'.
 743         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 744         (enum x86_64_isa): New.
 745         (isa64): Likewise.
 746         (print_i386_disassembler_options): Add amd64 and intel64.
 747         (print_insn): Handle amd64 and intel64.
 748         (putop): Handle '@'.
 749         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 750         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 751         * i386-opc.h (AMD64): New.
 752         (CpuIntel64): Likewise.
 753         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 754         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 755         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 756         * i386-init.h: Regenerated.
 757         * i386-tbl.h: Likewise.
 758
 759 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 760
 761         * ppc-opc.c (IH) New define.
 762         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 763         <tlbie>: Add RS operand for POWER7.
 764         <slbia>: Add IH operand for POWER6.
 765
 766 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 767
 768         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 769         direct branch.
 770         (jmp): Likewise.
 771         * i386-tbl.h: Regenerated.
 772
 773 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 774
 775         * configure.ac: Support bfd_iamcu_arch.
 776         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 777         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 778         CPU_IAMCU_COMPAT_FLAGS.
 779         (cpu_flags): Add CpuIAMCU.
 780         * i386-opc.h (CpuIAMCU): New.
 781         (i386_cpu_flags): Add cpuiamcu.
 782         * configure: Regenerated.
 783         * i386-init.h: Likewise.
 784         * i386-tbl.h: Likewise.
 785
 786 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 787
 788         PR binutis/18386
 789         * i386-dis.c (X86_64_E8): New.
 790         (X86_64_E9): Likewise.
 791         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 792         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 793         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 794         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 795         (putop): Handle '^'.
 796         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 797         REX_W.
 798
 799 2015-04-30  DJ Delorie  <dj@redhat.com>
 800
 801         * disassemble.c (disassembler): Choose suitable disassembler based
 802         on E_ABI.
 803         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 804         it to decode mul/div insns.
 805         * rl78-decode.c: Regenerate.
 806         * rl78-dis.c (print_insn_rl78): Rename to...
 807         (print_insn_rl78_common): ...this, take ISA parameter.
 808         (print_insn_rl78): New.
 809         (print_insn_rl78_g10): New.
 810         (print_insn_rl78_g13): New.
 811         (print_insn_rl78_g14): New.
 812         (rl78_get_disassembler): New.
 813
 814 2015-04-29  Nick Clifton  <nickc@redhat.com>
 815
 816         * po/fr.po: Updated French translation.
 817
 818 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 819
 820         * ppc-opc.c (DCBT_EO): New define.
 821         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 822         <lharx>: Likewise.
 823         <stbcx.>: Likewise.
 824         <sthcx.>: Likewise.
 825         <waitrsv>: Do not enable for POWER7 and later.
 826         <waitimpl>: Likewise.
 827         <dcbt>: Default to the two operand form of the instruction for all
 828         "old" cpus.  For "new" cpus, use the operand ordering that matches
 829         whether the cpu is server or embedded.
 830         <dcbtst>: Likewise.
 831
 832 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 833
 834         * s390-opc.c: New instruction type VV0UU2.
 835         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 836         and WFC.
 837
 838 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 839
 840         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 841         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 842         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 843         (vfpclasspd, vfpclassps): Add %XZ.
 844
 845 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 846
 847         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 848         (PREFIX_UD_REPZ): Likewise.
 849         (PREFIX_UD_REPNZ): Likewise.
 850         (PREFIX_UD_DATA): Likewise.
 851         (PREFIX_UD_ADDR): Likewise.
 852         (PREFIX_UD_LOCK): Likewise.
 853
 854 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 855
 856         * i386-dis.c (prefix_requirement): Removed.
 857         (print_insn): Don't set prefix_requirement.  Check
 858         dp->prefix_requirement instead of prefix_requirement.
 859
 860 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 861
 862         PR binutils/17898
 863         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 864         (PREFIX_MOD_0_0FC7_REG_6): This.
 865         (PREFIX_MOD_3_0FC7_REG_6): New.
 866         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 867         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 868         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 869         PREFIX_MOD_3_0FC7_REG_7.
 870         (mod_table): Replace PREFIX_0FC7_REG_6 with
 871         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 872         PREFIX_MOD_3_0FC7_REG_7.
 873
 874 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 875
 876         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 877         (PREFIX_MANDATORY_REPNZ): Likewise.
 878         (PREFIX_MANDATORY_DATA): Likewise.
 879         (PREFIX_MANDATORY_ADDR): Likewise.
 880         (PREFIX_MANDATORY_LOCK): Likewise.
 881         (PREFIX_MANDATORY): Likewise.
 882         (PREFIX_UD_SHIFT): Set to 8
 883         (PREFIX_UD_REPZ): Updated.
 884         (PREFIX_UD_REPNZ): Likewise.
 885         (PREFIX_UD_DATA): Likewise.
 886         (PREFIX_UD_ADDR): Likewise.
 887         (PREFIX_UD_LOCK): Likewise.
 888         (PREFIX_IGNORED_SHIFT): New.
 889         (PREFIX_IGNORED_REPZ): Likewise.
 890         (PREFIX_IGNORED_REPNZ): Likewise.
 891         (PREFIX_IGNORED_DATA): Likewise.
 892         (PREFIX_IGNORED_ADDR): Likewise.
 893         (PREFIX_IGNORED_LOCK): Likewise.
 894         (PREFIX_OPCODE): Likewise.
 895         (PREFIX_IGNORED): Likewise.
 896         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 897         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 898         (three_byte_table): Likewise.
 899         (mod_table): Likewise.
 900         (mandatory_prefix): Renamed to ...
 901         (prefix_requirement): This.
 902         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 903         Update PREFIX_90 entry.
 904         (get_valid_dis386): Check prefix_requirement to see if a prefix
 905         should be ignored.
 906         (print_insn): Replace mandatory_prefix with prefix_requirement.
 907
 908 2015-04-15  Renlin Li  <renlin.li@arm.com>
 909
 910         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 911         use it for ssat and ssat16.
 912         (print_insn_thumb32): Add handle case for 'D' control code.
 913
 914 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 915             H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 918         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 919         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 920         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 921         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 922         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 923         Fill prefix_requirement field.
 924         (struct dis386): Add prefix_requirement field.
 925         (dis386): Fill prefix_requirement field.
 926         (dis386_twobyte): Ditto.
 927         (twobyte_has_mandatory_prefix_: Remove.
 928         (reg_table): Fill prefix_requirement field.
 929         (prefix_table): Ditto.
 930         (x86_64_table): Ditto.
 931         (three_byte_table): Ditto.
 932         (xop_table): Ditto.
 933         (vex_table): Ditto.
 934         (vex_len_table): Ditto.
 935         (vex_w_table): Ditto.
 936         (mod_table): Ditto.
 937         (bad_opcode): Ditto.
 938         (print_insn): Use prefix_requirement.
 939         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 940         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 941         (float_reg): Ditto.
 942
 943 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 944
 945         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 946
 947 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         * Makefile.in: Regenerated.
 950
 951 2015-03-25  Anton Blanchard  <anton@samba.org>
 952
 953         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 954         powerpc_opcd_indices and vle_opcd_indices once.
 955
 956 2015-03-25  Anton Blanchard  <anton@samba.org>
 957
 958         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 959
 960 2015-03-24  Terry Guo  <terry.guo@arm.com>
 961
 962         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 963         (opcode16): Likewise.
 964         (coprocessor_opcodes): Replace bit with feature struct.
 965         (neon_opcodes): Likewise.
 966         (arm_opcodes): Likewise.
 967         (thumb_opcodes): Likewise.
 968         (thumb32_opcodes): Likewise.
 969         (print_insn_coprocessor): Likewise.
 970         (print_insn_arm): Likewise.
 971         (select_arm_features): Follow new feature struct.
 972
 973 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 974
 975         * i386-dis.c (rm_table): Add clzero.
 976         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 977         Add CPU_CLZERO_FLAGS.
 978         (cpu_flags): Add CpuCLZERO.
 979         * i386-opc.h: Add CpuCLZERO.
 980         * i386-opc.tbl: Add clzero.
 981         * i386-init.h: Re-generated.
 982         * i386-tbl.h: Re-generated.
 983
 984 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 985
 986         * mips-opc.c (decode_mips_operand): Fix constraint issues
 987         with u and y operands.
 988
 989 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 990
 991         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 992
 993 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 994
 995         * s390-opc.c: Add new IBM z13 instructions.
 996         * s390-opc.txt: Likewise.
 997
 998 2015-03-10  Renlin Li  <renlin.li@arm.com>
 999
1000         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1001         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1002         related alias.
1003         * aarch64-asm-2.c: Regenerate.
1004         * aarch64-dis-2.c: Likewise.
1005         * aarch64-opc-2.c: Likewise.
1006
1007 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
1008
1009         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1010
1011 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
1012
1013         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1014         arch_sh_up.
1015         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1016         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1017
1018 2015-02-23  Vinay  <Vinay.G@kpit.com>
1019
1020         * rl78-decode.opc (MOV): Added space between two operands for
1021         'mov' instruction in index addressing mode.
1022         * rl78-decode.c: Regenerate.
1023
1024 2015-02-19  Pedro Alves  <palves@redhat.com>
1025
1026         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1027
1028 2015-02-10  Pedro Alves  <palves@redhat.com>
1029             Tom Tromey  <tromey@redhat.com>
1030
1031         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1032         microblaze_and, microblaze_xor.
1033         * microblaze-opc.h (opcodes): Adjust.
1034
1035 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
1036
1037         * Makefile.am: Add FT32 files.
1038         * configure.ac: Handle FT32.
1039         * disassemble.c (disassembler): Call print_insn_ft32.
1040         * ft32-dis.c: New file.
1041         * ft32-opc.c: New file.
1042         * Makefile.in: Regenerate.
1043         * configure: Regenerate.
1044         * po/POTFILES.in: Regenerate.
1045
1046 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1047
1048         * nds32-asm.c (keyword_sr): Add new system registers.
1049
1050 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1051
1052         * s390-dis.c (s390_extract_operand): Support vector register
1053         operands.
1054         (s390_print_insn_with_opcode): Support new operands types and add
1055         new handling of optional operands.
1056         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1057         and include opcode/s390.h instead.
1058         (struct op_struct): New field `flags'.
1059         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1060         (dumpTable): Dump flags.
1061         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
1062         string.
1063         * s390-opc.c: Add new operands types, instruction formats, and
1064         instruction masks.
1065         (s390_opformats): Add new formats for .insn.
1066         * s390-opc.txt: Add new instructions.
1067
1068 2015-01-01  Alan Modra  <amodra@gmail.com>
1069
1070         Update year range in copyright notice of all files.
1071
1072 For older changes see ChangeLog-2014
1073 \f
1074 Copyright (C) 2015 Free Software Foundation, Inc.
1075
1076 Copying and distribution of this file, with or without modification,
1077 are permitted in any medium without royalty provided the copyright
1078 notice and this notice are preserved.
1079
1080 Local Variables:
1081 mode: change-log
1082 left-margin: 8
1083 fill-column: 74
1084 version-control: never
1085 End: