opcodes/ChangeLog

   1 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
   2
   3         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
   4         reflect the change to the short immediate syntax.
   5
   6 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
   7
   8         * or32-opc.c (debug): Warning fix.
   9         * po/POTFILES.in: Regenerate.
  10
  11         * maxq-dis.c: Formatting.
  12         (print_insn): Warning fix.
  13
  14 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
  15
  16         * arm-dis.c (WORD_ADDRESS): Define.
  17         (print_insn): Use it.  Correct big-endian end-of-section handling.
  18
  19 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  20             Vineet Sharma      <vineets@noida.hcltech.com>
  21
  22         * maxq-dis.c: New file.
  23         * disassemble.c (ARCH_maxq): Define.
  24         (disassembler): Add 'print_insn_maxq_little' for handling maxq
  25         instructions..
  26         * configure.in: Add case for bfd_maxq_arch.
  27         * configure: Regenerate.
  28         * Makefile.am: Add support for maxq-dis.c
  29         * Makefile.in: Regenerate.
  30         * aclocal.m4: Regenerate.
  31
  32 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  33
  34         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
  35         mode.
  36         * crx-dis.c: Likewise.
  37
  38 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  39
  40         Generally, handle CRISv32.
  41         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
  42         (struct cris_disasm_data): New type.
  43         (format_reg, format_hex, cris_constraint, print_flags)
  44         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
  45         callers changed.
  46         (format_sup_reg, print_insn_crisv32_with_register_prefix)
  47         (print_insn_crisv32_without_register_prefix)
  48         (print_insn_crisv10_v32_with_register_prefix)
  49         (print_insn_crisv10_v32_without_register_prefix)
  50         (cris_parse_disassembler_options): New functions.
  51         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
  52         parameter.  All callers changed.
  53         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
  54         failure.
  55         (cris_constraint) <case 'Y', 'U'>: New cases.
  56         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
  57         for constraint 'n'.
  58         (print_with_operands) <case 'Y'>: New case.
  59         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
  60         <case 'N', 'Y', 'Q'>: New cases.
  61         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
  62         (print_insn_cris_with_register_prefix)
  63         (print_insn_cris_without_register_prefix): Call
  64         cris_parse_disassembler_options.
  65         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
  66         for CRISv32 and the size of immediate operands.  New v32-only
  67         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
  68         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
  69         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
  70         Change brp to be v3..v10.
  71         (cris_support_regs): New vector.
  72         (cris_opcodes): Update head comment.  New format characters '[',
  73         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
  74         Add new opcodes for v32 and adjust existing opcodes to accommodate
  75         differences to earlier variants.
  76         (cris_cond15s): New vector.
  77
  78 2004-11-04 Jan Beulich <jbeulich@novell.com>
  79
  80         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
  81         (indirEb): Remove.
  82         (Mp): Use f_mode rather than none at all.
  83         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
  84         replaces what previously was x_mode; x_mode now means 128-bit SSE
  85         operands.
  86         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
  87         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
  88         pinsrw's second operand is Edqw.
  89         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
  90         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
  91         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
  92         mode when an operand size override is present or always suffixing.
  93         More instructions will need to be added to this group.
  94         (putop): Handle new macro chars 'C' (short/long suffix selector),
  95         'I' (Intel mode override for following macro char), and 'J' (for
  96         adding the 'l' prefix to far branches in AT&T mode). When an
  97         alternative was specified in the template, honor macro character when
  98         specified for Intel mode.
  99         (OP_E): Handle new *_mode values. Correct pointer specifications for
 100         memory operands. Consolidate output of index register.
 101         (OP_G): Handle new *_mode values.
 102         (OP_I): Handle const_1_mode.
 103         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 104         respective opcode prefix bits have been consumed.
 105         (OP_EM, OP_EX): Provide some default handling for generating pointer
 106         specifications.
 107
 108 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 109
 110         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 111         COP_INST macro.
 112
 113 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 114
 115         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 116         (getregliststring): Support HI/LO and user registers.
 117         * crx-opc.c (crx_instruction): Update data structure according to the
 118         rearrangement done in CRX opcode header file.
 119         (crx_regtab):  Likewise.
 120         (crx_optab):  Likewise.
 121         (crx_instruction): Reorder load/stor instructions, remove unsupported
 122         formats.
 123         support new Co-Processor instruction 'cpi'.
 124
 125 2004-10-27  Nick Clifton  <nickc@redhat.com>
 126
 127         * opcodes/iq2000-asm.c: Regenerate.
 128         * opcodes/iq2000-desc.c: Regenerate.
 129         * opcodes/iq2000-desc.h: Regenerate.
 130         * opcodes/iq2000-dis.c: Regenerate.
 131         * opcodes/iq2000-ibld.c: Regenerate.
 132         * opcodes/iq2000-opc.c: Regenerate.
 133         * opcodes/iq2000-opc.h: Regenerate.
 134
 135 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 136
 137         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 138         us4, us5 (respectively).
 139         Remove unsupported 'popa' instruction.
 140         Reverse operands order in store co-processor instructions.
 141
 142 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 143
 144         * Makefile.am: Run "make dep-am"
 145         * Makefile.in: Regenerate.
 146
 147 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 148
 149         * xtensa-dis.c: Use ISO C90 formatting.
 150
 151 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 152
 153         * ppc-opc.c: Revert 2004-09-09 change.
 154
 155 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 156
 157         * xtensa-dis.c (state_names): Delete.
 158         (fetch_data): Use xtensa_isa_maxlength.
 159         (print_xtensa_operand): Replace operand parameter with opcode/operand
 160         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 161         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 162         instruction bundles.  Use xmalloc instead of malloc.
 163
 164 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 165
 166         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 167         initializers.
 168
 169 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 170
 171         * crx-opc.c (crx_instruction): Support Co-processor insns.
 172         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 173         (getregliststring): Change function to use the above enum.
 174         (print_arg): Handle CO-Processor insns.
 175         (crx_cinvs): Add 'b' option to invalidate the branch-target
 176         cache.
 177
 178 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 179
 180         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 181         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 182         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 183         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 184         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 185
 186 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 187
 188         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 189         rather than add it.
 190
 191 2004-09-30  Paul Brook  <paul@codesourcery.com>
 192
 193         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 194         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 195
 196 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 199         (CONFIG_STATUS_DEPENDENCIES): New.
 200         (Makefile): Removed.
 201         (config.status): Likewise.
 202         * Makefile.in: Regenerated.
 203
 204 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 205
 206         * Makefile.am: Run "make dep-am".
 207         * Makefile.in: Regenerate.
 208         * aclocal.m4: Regenerate.
 209         * configure: Regenerate.
 210         * po/POTFILES.in: Regenerate.
 211         * po/opcodes.pot: Regenerate.
 212
 213 2004-09-11  Andreas Schwab  <schwab@suse.de>
 214
 215         * configure: Rebuild.
 216
 217 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 218
 219         * ppc-opc.c (L): Make this field not optional.
 220
 221 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 222
 223         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 224         Fix parameter to 'm[t|f]csr' insns.
 225
 226 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 227
 228         * configure.in: Autoupdate to autoconf 2.59.
 229         * aclocal.m4: Rebuild with aclocal 1.4p6.
 230         * configure: Rebuild with autoconf 2.59.
 231         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 232         bfd changes for autoconf 2.59 on the way).
 233         * config.in: Rebuild with autoheader 2.59.
 234
 235 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 236
 237         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 238
 239 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 240
 241         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 242         (GRPPADLCK2): New define.
 243         (twobyte_has_modrm): True for 0xA6.
 244         (grps): GRPPADLCK2 for opcode 0xA6.
 245
 246 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 247
 248         Introduce SH2a support.
 249         * sh-opc.h (arch_sh2a_base): Renumber.
 250         (arch_sh2a_nofpu_base): Remove.
 251         (arch_sh_base_mask): Adjust.
 252         (arch_opann_mask): New.
 253         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 254         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 255         (sh_table): Adjust whitespace.
 256         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 257         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 258         instruction list throughout.
 259         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 260         of arch_sh2a in instruction list throughout.
 261         (arch_sh2e_up): Accomodate above changes.
 262         (arch_sh2_up): Ditto.
 263         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 264         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 265         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 266         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 267         * sh-opc.h (arch_sh2a_nofpu): New.
 268         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 269         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 270         instruction.
 271         2004-01-20  DJ Delorie  <dj@redhat.com>
 272         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 273         2003-12-29  DJ Delorie  <dj@redhat.com>
 274         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 275         sh_opcode_info, sh_table): Add sh2a support.
 276         (arch_op32): New, to tag 32-bit opcodes.
 277         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 278         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 279         * sh-opc.h (arch_sh2a): Add.
 280         * sh-dis.c (arch_sh2a): Handle.
 281         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 282
 283 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 284
 285         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 286
 287 2004-07-22  Nick Clifton  <nickc@redhat.com>
 288
 289         PR/280
 290         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 291         insns - this is done by objdump itself.
 292         * h8500-dis.c (print_insn_h8500): Likewise.
 293
 294 2004-07-21  Jan Beulich <jbeulich@novell.com>
 295
 296         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 297         regardless of address size prefix in effect.
 298         (ptr_reg): Size or address registers does not depend on rex64, but
 299         on the presence of an address size override.
 300         (OP_MMX): Use rex.x only for xmm registers.
 301         (OP_EM): Use rex.z only for xmm registers.
 302
 303 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 304
 305         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 306         move/branch operations to the bottom so that VR5400 multimedia
 307         instructions take precedence in disassembly.
 308
 309 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 310
 311         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 312         ISA-specific "break" encoding.
 313
 314 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 315
 316         * arm-opc.h: Fix typo in comment.
 317
 318 2004-07-11  Andreas Schwab  <schwab@suse.de>
 319
 320         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 321
 322 2004-07-09  Andreas Schwab  <schwab@suse.de>
 323
 324         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 325
 326 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 327
 328         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 329         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 330         (crx-dis.lo): New target.
 331         (crx-opc.lo): Likewise.
 332         * Makefile.in: Regenerate.
 333         * configure.in: Handle bfd_crx_arch.
 334         * configure: Regenerate.
 335         * crx-dis.c: New file.
 336         * crx-opc.c: New file.
 337         * disassemble.c (ARCH_crx): Define.
 338         (disassembler): Handle ARCH_crx.
 339
 340 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 341
 342         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 343         * ia64-asmtab.c: Regnerate.
 344
 345 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 346
 347         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 348         (extract_fxm): Don't test dialect.
 349         (XFXFXM_MASK): Include the power4 bit.
 350         (XFXM): Add p4 param.
 351         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 352
 353 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 354
 355         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 356         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 357
 358 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 359
 360         * ppc-opc.c (BH, XLBH_MASK): Define.
 361         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 362
 363 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 364
 365         * i386-dis.c (x_mode): Comment.
 366         (two_source_ops): File scope.
 367         (float_mem): Correct fisttpll and fistpll.
 368         (float_mem_mode): New table.
 369         (dofloat): Use it.
 370         (OP_E): Correct intel mode PTR output.
 371         (ptr_reg): Use open_char and close_char.
 372         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 373         operands.  Set two_source_ops.
 374
 375 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 376
 377         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 378         instead of _raw_size.
 379
 380 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 381
 382         * ia64-gen.c (in_iclass): Handle more postinc st
 383         and ld variants.
 384         * ia64-asmtab.c: Rebuilt.
 385
 386 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 387
 388         * s390-opc.txt: Correct architecture mask for some opcodes.
 389         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 390         in the esa mode as well.
 391
 392 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 393
 394         * sh-dis.c (target_arch): Make unsigned.
 395         (print_insn_sh): Replace (most of) switch with a call to
 396         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 397         * sh-opc.h: Redefine architecture flags values.
 398         Add sh3-nommu architecture.
 399         Reorganise <arch>_up macros so they make more visual sense.
 400         (SH_MERGE_ARCH_SET): Define new macro.
 401         (SH_VALID_BASE_ARCH_SET): Likewise.
 402         (SH_VALID_MMU_ARCH_SET): Likewise.
 403         (SH_VALID_CO_ARCH_SET): Likewise.
 404         (SH_VALID_ARCH_SET): Likewise.
 405         (SH_MERGE_ARCH_SET_VALID): Likewise.
 406         (SH_ARCH_SET_HAS_FPU): Likewise.
 407         (SH_ARCH_SET_HAS_DSP): Likewise.
 408         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 409         (sh_get_arch_from_bfd_mach): Add prototype.
 410         (sh_get_arch_up_from_bfd_mach): Likewise.
 411         (sh_get_bfd_mach_from_arch_set): Likewise.
 412         (sh_merge_bfd_arc): Likewise.
 413
 414 2004-05-24  Peter Barada  <peter@the-baradas.com>
 415
 416         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 417         into new match_insn_m68k function.  Loop over canidate
 418         matches and select first that completely matches.
 419         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 420         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 421         to verify addressing for MAC/EMAC.
 422         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 423         reigster halves since 'fpu' and 'spl' look misleading.
 424         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 425         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 426         first, tighten up match masks.
 427         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 428         'size' from special case code in print_insn_m68k to
 429         determine decode size of insns.
 430
 431 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 432
 433         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 434         well as when -mpower4.
 435
 436 2004-05-13  Nick Clifton  <nickc@redhat.com>
 437
 438         * po/fr.po: Updated French translation.
 439
 440 2004-05-05  Peter Barada  <peter@the-baradas.com>
 441
 442         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 443         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 444         * m68k-op.c: Switch from ColdFire chips to core variants.
 445
 446 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 447
 448         PR 147.
 449         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 450
 451 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 452
 453         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 454         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 455
 456 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 457
 458         * sh-dis.c (print_insn_sh): Print the value in constant pool
 459         as a symbol if it looks like a symbol.
 460
 461 2004-04-22  Peter Barada <peter@the-baradas.com>
 462
 463         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 464         appropriate ColdFire architectures.
 465         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 466         mask addressing.
 467         Add EMAC instructions, fix MAC instructions. Remove
 468         macmw/macml/msacmw/msacml instructions since mask addressing now
 469         supported.
 470
 471 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 472
 473         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 474         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 475         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 476         macro.  Adjust all users.
 477
 478 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 479
 480         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 481         separately.
 482
 483 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 484
 485         * m32r-asm.c: Regenerate.
 486
 487 2004-03-29  Stan Shebs  <shebs@apple.com>
 488
 489         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 490         used.
 491
 492 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 493
 494         * aclocal.m4: Regenerate.
 495         * config.in: Regenerate.
 496         * configure: Regenerate.
 497         * po/POTFILES.in: Regenerate.
 498         * po/opcodes.pot: Regenerate.
 499
 500 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 501
 502         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 503         PPC_OPERANDS_GPR_0.
 504         * ppc-opc.c (RA0): Define.
 505         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 506         (RAOPT): Rename from RAO.  Update all uses.
 507         (powerpc_opcodes): Use RA0 as appropriate.
 508
 509 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 510
 511         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 512
 513 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 514
 515         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 516
 517 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 518
 519         * i386-dis.c (GRPPLOCK): Delete.
 520         (grps): Delete GRPPLOCK entry.
 521
 522 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 523
 524         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 525         (M, Mp): Use OP_M.
 526         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 527         (GRPPADLCK): Define.
 528         (dis386): Use NOP_Fixup on "nop".
 529         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 530         (twobyte_has_modrm): Set for 0xa7.
 531         (padlock_table): Delete.  Move to..
 532         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 533         and clflush.
 534         (print_insn): Revert PADLOCK_SPECIAL code.
 535         (OP_E): Delete sfence, lfence, mfence checks.
 536
 537 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 538
 539         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 540         (INVLPG_Fixup): New function.
 541         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 542
 543 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 544
 545         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 546         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 547         (padlock_table): New struct with PadLock instructions.
 548         (print_insn): Handle PADLOCK_SPECIAL.
 549
 550 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 551
 552         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 553         (OP_E): Twiddle clflush to sfence here.
 554
 555 2004-03-08  Nick Clifton  <nickc@redhat.com>
 556
 557         * po/de.po: Updated German translation.
 558
 559 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 560
 561         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 562         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 563         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 564         accordingly.
 565
 566 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 567
 568         * frv-asm.c: Regenerate.
 569         * frv-desc.c: Regenerate.
 570         * frv-desc.h: Regenerate.
 571         * frv-dis.c: Regenerate.
 572         * frv-ibld.c: Regenerate.
 573         * frv-opc.c: Regenerate.
 574         * frv-opc.h: Regenerate.
 575
 576 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 577
 578         * frv-desc.c, frv-opc.c: Regenerate.
 579
 580 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 581
 582         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 583
 584 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 585
 586         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 587         Also correct mistake in the comment.
 588
 589 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 590
 591         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 592         ensure that double registers have even numbers.
 593         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 594         that reserved instruction 0xfffd does not decode the same
 595         as 0xfdfd (ftrv).
 596         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 597         REG_N refers to a double register.
 598         Add REG_N_B01 nibble type and use it instead of REG_NM
 599         in ftrv.
 600         Adjust the bit patterns in a few comments.
 601
 602 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 603
 604         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 605
 606 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 607
 608         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 609
 610 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 611
 612         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 613
 614 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 615
 616         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 617         mtivor32, mtivor33, mtivor34.
 618
 619 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 620
 621         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 622
 623 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 624
 625         * arm-opc.h Maverick accumulator register opcode fixes.
 626
 627 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 628
 629         * m32r-dis.c: Regenerate.
 630
 631 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 632
 633         * sh-opc.h (sh_table): "fsrra", not "fssra".
 634
 635 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 636
 637         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 638         contraints.
 639
 640 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 641
 642         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 643
 644 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 645
 646         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 647         1.  Don't print scale factor on AT&T mode when index missing.
 648
 649 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 650
 651         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 652         when loaded into XR registers.
 653
 654 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 655
 656         * frv-desc.h: Regenerate.
 657         * frv-desc.c: Regenerate.
 658         * frv-opc.c: Regenerate.
 659
 660 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 661
 662         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 663
 664 2004-01-09  Paul Brook  <paul@codesourcery.com>
 665
 666         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 667         specific opcodes.
 668
 669 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 670
 671         * Makefile.am (libopcodes_la_DEPENDENCIES)
 672         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 673         comment about the problem.
 674         * Makefile.in: Regenerate.
 675
 676 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 677
 678         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 679         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 680         cut&paste errors in shifting/truncating numerical operands.
 681         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 682         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 683         (parse_uslo16): Likewise.
 684         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 685         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 686         (parse_s12): Likewise.
 687         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 688         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 689         (parse_uslo16): Likewise.
 690         (parse_uhi16): Parse gothi and gotfuncdeschi.
 691         (parse_d12): Parse got12 and gotfuncdesc12.
 692         (parse_s12): Likewise.
 693
 694 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 695
 696         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 697         instruction which looks similar to an 'rla' instruction.
 698
 699 For older changes see ChangeLog-0203
 700 \f
 701 Local Variables:
 702 mode: change-log
 703 left-margin: 8
 704 fill-column: 74
 705 version-control: never
 706 End: