1 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
3 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
4 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
7 2016-07-27 Graham Markall <graham.markall@embecosm.com>
9 * arc-nps400-tbl.h: Change block comments to GNU format.
10 * arc-dis.c: Add new globals addrtypenames,
11 addrtypenames_max, and addtypeunknown.
12 (get_addrtype): New function.
13 (print_insn_arc): Print colons and address types when
15 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
16 define insert and extract functions for all address types.
17 (arc_operands): Add operands for colon and all address
19 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
20 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
21 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
22 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
23 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
24 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
26 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
28 * configure: Regenerated.
30 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
32 * arc-dis.c (skipclass): New structure.
33 (decodelist): New variable.
34 (is_compatible_p): New function.
35 (new_element): Likewise.
36 (skip_class_p): Likewise.
37 (find_format_from_table): Use skip_class_p function.
38 (find_format): Decode first the extension instructions.
39 (print_insn_arc): Select either ARCEM or ARCHS based on elf
41 (parse_option): New function.
42 (parse_disassembler_options): Likewise.
43 (print_arc_disassembler_options): Likewise.
44 (print_insn_arc): Use parse_disassembler_options function. Proper
45 select ARCv2 cpu variant.
46 * disassemble.c (disassembler_usage): Add ARC disassembler
49 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
51 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
52 annotation from the "nal" entry and reorder it beyond "bltzal".
54 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
56 * sparc-opc.c (ldtxa): New macro.
57 (sparc_opcodes): Use the macro defined above to add entries for
58 the LDTXA instructions.
59 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
62 2016-07-07 James Bowman <james.bowman@ftdichip.com>
64 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
67 2016-07-01 Jan Beulich <jbeulich@suse.com>
69 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
70 (movzb): Adjust to cover all permitted suffixes.
72 * i386-tbl.h: Re-generate.
74 2016-07-01 Jan Beulich <jbeulich@suse.com>
76 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
77 (lgdt): Remove Tbyte from non-64-bit variant.
78 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
79 xsaves64, xsavec64): Remove Disp16.
80 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
81 Remove Disp32S from non-64-bit variants. Remove Disp16 from
83 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
84 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
85 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
87 * i386-tbl.h: Re-generate.
89 2016-07-01 Jan Beulich <jbeulich@suse.com>
91 * i386-opc.tbl (xlat): Remove RepPrefixOk.
92 * i386-tbl.h: Re-generate.
94 2016-06-30 Yao Qi <yao.qi@linaro.org>
96 * arm-dis.c (print_insn): Fix typo in comment.
98 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
100 * aarch64-opc.c (operand_general_constraint_met_p): Check the
101 range of ldst_elemlist operands.
102 (print_register_list): Use PRIi64 to print the index.
103 (aarch64_print_operand): Likewise.
105 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
107 * mcore-opc.h: Remove sentinal.
108 * mcore-dis.c (print_insn_mcore): Adjust.
110 2016-06-23 Graham Markall <graham.markall@embecosm.com>
112 * arc-opc.c: Correct description of availability of NPS400
115 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
117 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
118 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
119 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
120 xor3>: New mnemonics.
121 <setb>: Change to a VX form instruction.
122 (insert_sh6): Add support for rldixor.
123 (extract_sh6): Likewise.
125 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
127 * arc-ext.h: Wrap in extern C.
129 2016-06-21 Graham Markall <graham.markall@embecosm.com>
131 * arc-dis.c (arc_insn_length): Add comment on instruction length.
132 Use same method for determining instruction length on ARC700 and
134 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
135 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
136 with the NPS400 subclass.
137 * arc-opc.c: Likewise.
139 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
141 * sparc-opc.c (rdasr): New macro.
147 (sparc_opcodes): Use the macros above to fix and expand the
148 definition of read/write instructions from/to
149 asr/privileged/hyperprivileged instructions.
150 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
151 %hva_mask_nz. Prefer softint_set and softint_clear over
152 set_softint and clear_softint.
153 (print_insn_sparc): Support %ver in Rd.
155 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
157 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
158 architecture according to the hardware capabilities they require.
160 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
162 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
163 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
164 bfd_mach_sparc_v9{c,d,e,v,m}.
165 * sparc-opc.c (MASK_V9C): Define.
166 (MASK_V9D): Likewise.
167 (MASK_V9E): Likewise.
168 (MASK_V9V): Likewise.
169 (MASK_V9M): Likewise.
170 (v6): Add MASK_V9{C,D,E,V,M}.
171 (v6notlet): Likewise.
175 (v9andleon): Likewise.
183 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
185 2016-06-15 Nick Clifton <nickc@redhat.com>
187 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
188 constants to match expected behaviour.
189 (nds32_parse_opcode): Likewise. Also for whitespace.
191 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
193 * arc-opc.c (extract_rhv1): Extract value from insn.
195 2016-06-14 Graham Markall <graham.markall@embecosm.com>
197 * arc-nps400-tbl.h: Add ldbit instruction.
198 * arc-opc.c: Add flag classes required for ldbit.
200 2016-06-14 Graham Markall <graham.markall@embecosm.com>
202 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
203 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
204 support the above instructions.
206 2016-06-14 Graham Markall <graham.markall@embecosm.com>
208 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
209 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
210 csma, cbba, zncv, and hofs.
211 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
212 support the above instructions.
214 2016-06-06 Graham Markall <graham.markall@embecosm.com>
216 * arc-nps400-tbl.h: Add andab and orab instructions.
218 2016-06-06 Graham Markall <graham.markall@embecosm.com>
220 * arc-nps400-tbl.h: Add addl-like instructions.
222 2016-06-06 Graham Markall <graham.markall@embecosm.com>
224 * arc-nps400-tbl.h: Add mxb and imxb instructions.
226 2016-06-06 Graham Markall <graham.markall@embecosm.com>
228 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
231 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
233 * s390-dis.c (option_use_insn_len_bits_p): New file scope
235 (init_disasm): Handle new command line option "insnlength".
236 (print_s390_disassembler_options): Mention new option in help
238 (print_insn_s390): Use the encoded insn length when dumping
239 unknown instructions.
241 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
243 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
244 to the address and set as symbol address for LDS/ STS immediate operands.
246 2016-06-07 Alan Modra <amodra@gmail.com>
248 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
249 cpu for "vle" to e500.
250 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
251 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
252 (PPCNONE): Delete, substitute throughout.
253 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
254 except for major opcode 4 and 31.
255 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
257 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
259 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
260 ARM_EXT_RAS in relevant entries.
262 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
265 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
268 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
271 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
273 Add comments for '&'.
274 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
276 (intel_operand_size): Handle indir_v_mode.
277 (OP_E_register): Likewise.
278 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
279 64-bit indirect call/jmp for AMD64.
280 * i386-tbl.h: Regenerated
282 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
284 * arc-dis.c (struct arc_operand_iterator): New structure.
285 (find_format_from_table): All the old content from find_format,
286 with some minor adjustments, and parameter renaming.
287 (find_format_long_instructions): New function.
288 (find_format): Rewritten.
289 (arc_insn_length): Add LSB parameter.
290 (extract_operand_value): New function.
291 (operand_iterator_next): New function.
292 (print_insn_arc): Use new functions to find opcode, and iterator
294 * arc-opc.c (insert_nps_3bit_dst_short): New function.
295 (extract_nps_3bit_dst_short): New function.
296 (insert_nps_3bit_src2_short): New function.
297 (extract_nps_3bit_src2_short): New function.
298 (insert_nps_bitop1_size): New function.
299 (extract_nps_bitop1_size): New function.
300 (insert_nps_bitop2_size): New function.
301 (extract_nps_bitop2_size): New function.
302 (insert_nps_bitop_mod4_msb): New function.
303 (extract_nps_bitop_mod4_msb): New function.
304 (insert_nps_bitop_mod4_lsb): New function.
305 (extract_nps_bitop_mod4_lsb): New function.
306 (insert_nps_bitop_dst_pos3_pos4): New function.
307 (extract_nps_bitop_dst_pos3_pos4): New function.
308 (insert_nps_bitop_ins_ext): New function.
309 (extract_nps_bitop_ins_ext): New function.
310 (arc_operands): Add new operands.
311 (arc_long_opcodes): New global array.
312 (arc_num_long_opcodes): New global.
313 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
315 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
317 * nds32-asm.h: Add extern "C".
318 * sh-opc.h: Likewise.
320 2016-06-01 Graham Markall <graham.markall@embecosm.com>
322 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
323 0,b,limm to the rflt instruction.
325 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
327 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
330 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
333 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
334 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
335 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
336 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
337 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
338 * i386-init.h: Regenerated.
340 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
343 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
344 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
345 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
346 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
347 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
348 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
349 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
350 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
351 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
352 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
353 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
354 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
355 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
356 CpuRegMask for AVX512.
357 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
359 (set_bitfield_from_cpu_flag_init): New function.
360 (set_bitfield): Remove const on f. Call
361 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
362 * i386-opc.h (CpuRegMMX): New.
363 (CpuRegXMM): Likewise.
364 (CpuRegYMM): Likewise.
365 (CpuRegZMM): Likewise.
366 (CpuRegMask): Likewise.
367 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
369 * i386-init.h: Regenerated.
370 * i386-tbl.h: Likewise.
372 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
375 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
376 (opcode_modifiers): Add AMD64 and Intel64.
377 (main): Properly verify CpuMax.
378 * i386-opc.h (CpuAMD64): Removed.
379 (CpuIntel64): Likewise.
380 (CpuMax): Set to CpuNo64.
381 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
384 (i386_opcode_modifier): Add amd64 and intel64.
385 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
387 * i386-init.h: Regenerated.
388 * i386-tbl.h: Likewise.
390 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
393 * i386-gen.c (main): Fail if CpuMax is incorrect.
394 * i386-opc.h (CpuMax): Set to CpuIntel64.
395 * i386-tbl.h: Regenerated.
397 2016-05-27 Nick Clifton <nickc@redhat.com>
400 * msp430-dis.c (msp430dis_read_two_bytes): New function.
401 (msp430dis_opcode_unsigned): New function.
402 (msp430dis_opcode_signed): New function.
403 (msp430_singleoperand): Use the new opcode reading functions.
404 Only disassenmble bytes if they were successfully read.
405 (msp430_doubleoperand): Likewise.
406 (msp430_branchinstr): Likewise.
407 (msp430x_callx_instr): Likewise.
408 (print_insn_msp430): Check that it is safe to read bytes before
409 attempting disassembly. Use the new opcode reading functions.
411 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
413 * ppc-opc.c (CY): New define. Document it.
414 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
416 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
418 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
419 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
420 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
421 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
423 * i386-init.h: Regenerated.
425 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
428 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
429 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
430 * i386-init.h: Regenerated.
432 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
434 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
435 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
436 * i386-init.h: Regenerated.
438 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
440 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
442 (print_insn_arc): Set insn_type information.
443 * arc-opc.c (C_CC): Add F_CLASS_COND.
444 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
445 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
446 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
447 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
448 (brne, brne_s, jeq_s, jne_s): Likewise.
450 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
452 * arc-tbl.h (neg): New instruction variant.
454 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
456 * arc-dis.c (find_format, find_format, get_auxreg)
457 (print_insn_arc): Changed.
458 * arc-ext.h (INSERT_XOP): Likewise.
460 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
462 * tic54x-dis.c (sprint_mmr): Adjust.
463 * tic54x-opc.c: Likewise.
465 2016-05-19 Alan Modra <amodra@gmail.com>
467 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
469 2016-05-19 Alan Modra <amodra@gmail.com>
471 * ppc-opc.c: Formatting.
472 (NSISIGNOPT): Define.
473 (powerpc_opcodes <subis>): Use NSISIGNOPT.
475 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
477 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
478 replacing references to `micromips_ase' throughout.
479 (_print_insn_mips): Don't use file-level microMIPS annotation to
480 determine the disassembly mode with the symbol table.
482 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
484 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
486 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
488 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
490 * mips-opc.c (D34): New macro.
491 (mips_builtin_opcodes): Define bposge32c for DSPr3.
493 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
495 * i386-dis.c (prefix_table): Add RDPID instruction.
496 * i386-gen.c (cpu_flag_init): Add RDPID flag.
497 (cpu_flags): Add RDPID bitfield.
498 * i386-opc.h (enum): Add RDPID element.
499 (i386_cpu_flags): Add RDPID field.
500 * i386-opc.tbl: Add RDPID instruction.
501 * i386-init.h: Regenerate.
502 * i386-tbl.h: Regenerate.
504 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
506 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
507 branch type of a symbol.
508 (print_insn): Likewise.
510 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
512 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
513 Mainline Security Extensions instructions.
514 (thumb_opcodes): Add entries for narrow ARMv8-M Security
515 Extensions instructions.
516 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
518 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
521 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
523 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
525 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
527 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
528 (arcExtMap_genOpcode): Likewise.
529 * arc-opc.c (arg_32bit_rc): Define new variable.
530 (arg_32bit_u6): Likewise.
531 (arg_32bit_limm): Likewise.
533 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
535 * aarch64-gen.c (VERIFIER): Define.
536 * aarch64-opc.c (VERIFIER): Define.
537 (verify_ldpsw): Use static linkage.
538 * aarch64-opc.h (verify_ldpsw): Remove.
539 * aarch64-tbl.h: Use VERIFIER for verifiers.
541 2016-04-28 Nick Clifton <nickc@redhat.com>
544 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
545 * aarch64-opc.c (verify_ldpsw): New function.
546 * aarch64-opc.h (verify_ldpsw): New prototype.
547 * aarch64-tbl.h: Add initialiser for verifier field.
548 (LDPSW): Set verifier to verify_ldpsw.
550 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
554 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
555 smaller than address size.
557 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
559 * alpha-dis.c: Regenerate.
560 * crx-dis.c: Likewise.
561 * disassemble.c: Likewise.
562 * epiphany-opc.c: Likewise.
563 * fr30-opc.c: Likewise.
564 * frv-opc.c: Likewise.
565 * ip2k-opc.c: Likewise.
566 * iq2000-opc.c: Likewise.
567 * lm32-opc.c: Likewise.
568 * lm32-opinst.c: Likewise.
569 * m32c-opc.c: Likewise.
570 * m32r-opc.c: Likewise.
571 * m32r-opinst.c: Likewise.
572 * mep-opc.c: Likewise.
573 * mt-opc.c: Likewise.
574 * or1k-opc.c: Likewise.
575 * or1k-opinst.c: Likewise.
576 * tic80-opc.c: Likewise.
577 * xc16x-opc.c: Likewise.
578 * xstormy16-opc.c: Likewise.
580 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
582 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
583 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
584 calcsd, and calcxd instructions.
585 * arc-opc.c (insert_nps_bitop_size): Delete.
586 (extract_nps_bitop_size): Delete.
587 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
588 (extract_nps_qcmp_m3): Define.
589 (extract_nps_qcmp_m2): Define.
590 (extract_nps_qcmp_m1): Define.
591 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
592 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
593 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
594 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
595 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
598 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
600 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
602 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
604 * Makefile.in: Regenerated with automake 1.11.6.
605 * aclocal.m4: Likewise.
607 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
609 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
611 * arc-opc.c (insert_nps_cmem_uimm16): New function.
612 (extract_nps_cmem_uimm16): New function.
613 (arc_operands): Add NPS_XLDST_UIMM16 operand.
615 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
617 * arc-dis.c (arc_insn_length): New function.
618 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
619 (find_format): Change insnLen parameter to unsigned.
621 2016-04-13 Nick Clifton <nickc@redhat.com>
624 * v850-opc.c (v850_opcodes): Correct masks for long versions of
625 the LD.B and LD.BU instructions.
627 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
629 * arc-dis.c (find_format): Check for extension flags.
630 (print_flags): New function.
631 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
633 * arc-ext.c (arcExtMap_coreRegName): Use
634 LAST_EXTENSION_CORE_REGISTER.
635 (arcExtMap_coreReadWrite): Likewise.
636 (dump_ARC_extmap): Update printing.
637 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
638 (arc_aux_regs): Add cpu field.
639 * arc-regs.h: Add cpu field, lower case name aux registers.
641 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
643 * arc-tbl.h: Add rtsc, sleep with no arguments.
645 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
647 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
649 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
650 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
651 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
652 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
653 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
654 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
655 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
656 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
657 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
658 (arc_opcode arc_opcodes): Null terminate the array.
659 (arc_num_opcodes): Remove.
660 * arc-ext.h (INSERT_XOP): Define.
661 (extInstruction_t): Likewise.
662 (arcExtMap_instName): Delete.
663 (arcExtMap_insn): New function.
664 (arcExtMap_genOpcode): Likewise.
665 * arc-ext.c (ExtInstruction): Remove.
666 (create_map): Zero initialize instruction fields.
667 (arcExtMap_instName): Remove.
668 (arcExtMap_insn): New function.
669 (dump_ARC_extmap): More info while debuging.
670 (arcExtMap_genOpcode): New function.
671 * arc-dis.c (find_format): New function.
672 (print_insn_arc): Use find_format.
673 (arc_get_disassembler): Enable dump_ARC_extmap only when
676 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
678 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
679 instruction bits out.
681 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
683 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
684 * arc-opc.c (arc_flag_operands): Add new flags.
685 (arc_flag_classes): Add new classes.
687 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
689 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
691 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
693 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
694 encode1, rflt, crc16, and crc32 instructions.
695 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
696 (arc_flag_classes): Add C_NPS_R.
697 (insert_nps_bitop_size_2b): New function.
698 (extract_nps_bitop_size_2b): Likewise.
699 (insert_nps_bitop_uimm8): Likewise.
700 (extract_nps_bitop_uimm8): Likewise.
701 (arc_operands): Add new operand entries.
703 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
705 * arc-regs.h: Add a new subclass field. Add double assist
706 accumulator register values.
707 * arc-tbl.h: Use DPA subclass to mark the double assist
708 instructions. Use DPX/SPX subclas to mark the FPX instructions.
709 * arc-opc.c (RSP): Define instead of SP.
710 (arc_aux_regs): Add the subclass field.
712 2016-04-05 Jiong Wang <jiong.wang@arm.com>
714 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
716 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
718 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
721 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
723 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
724 issues. No functional changes.
726 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
728 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
729 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
730 (RTT): Remove duplicate.
731 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
732 (PCT_CONFIG*): Remove.
733 (D1L, D1H, D2H, D2L): Define.
735 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
737 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
739 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
741 * arc-tbl.h (invld07): Remove.
742 * arc-ext-tbl.h: New file.
743 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
744 * arc-opc.c (arc_opcodes): Add ext-tbl include.
746 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
748 Fix -Wstack-usage warnings.
749 * aarch64-dis.c (print_operands): Substitute size.
750 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
752 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
754 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
755 to get a proper diagnostic when an invalid ASR register is used.
757 2016-03-22 Nick Clifton <nickc@redhat.com>
759 * configure: Regenerate.
761 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
763 * arc-nps400-tbl.h: New file.
764 * arc-opc.c: Add top level comment.
765 (insert_nps_3bit_dst): New function.
766 (extract_nps_3bit_dst): New function.
767 (insert_nps_3bit_src2): New function.
768 (extract_nps_3bit_src2): New function.
769 (insert_nps_bitop_size): New function.
770 (extract_nps_bitop_size): New function.
771 (arc_flag_operands): Add nps400 entries.
772 (arc_flag_classes): Add nps400 entries.
773 (arc_operands): Add nps400 entries.
774 (arc_opcodes): Add nps400 include.
776 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
778 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
779 the new class enum values.
781 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
783 * arc-dis.c (print_insn_arc): Handle nps400.
785 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
787 * arc-opc.c (BASE): Delete.
789 2016-03-18 Nick Clifton <nickc@redhat.com>
792 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
793 of MOV insn that aliases an ORR insn.
795 2016-03-16 Jiong Wang <jiong.wang@arm.com>
797 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
799 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
801 * mcore-opc.h: Add const qualifiers.
802 * microblaze-opc.h (struct op_code_struct): Likewise.
803 * sh-opc.h: Likewise.
804 * tic4x-dis.c (tic4x_print_indirect): Likewise.
805 (tic4x_print_op): Likewise.
807 2016-03-02 Alan Modra <amodra@gmail.com>
809 * or1k-desc.h: Regenerate.
810 * fr30-ibld.c: Regenerate.
811 * rl78-decode.c: Regenerate.
813 2016-03-01 Nick Clifton <nickc@redhat.com>
816 * rl78-dis.c (print_insn_rl78_common): Fix typo.
818 2016-02-24 Renlin Li <renlin.li@arm.com>
820 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
821 (print_insn_coprocessor): Support fp16 instructions.
823 2016-02-24 Renlin Li <renlin.li@arm.com>
825 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
828 2016-02-24 Renlin Li <renlin.li@arm.com>
830 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
831 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
833 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
835 * i386-dis.c (print_insn): Parenthesize expression to prevent
839 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
840 Janek van Oirschot <jvanoirs@synopsys.com>
842 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
845 2016-02-04 Nick Clifton <nickc@redhat.com>
848 * msp430-dis.c (print_insn_msp430): Add a special case for
849 decoding an RRC instruction with the ZC bit set in the extension
852 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
854 * cgen-ibld.in (insert_normal): Rework calculation of shift.
855 * epiphany-ibld.c: Regenerate.
856 * fr30-ibld.c: Regenerate.
857 * frv-ibld.c: Regenerate.
858 * ip2k-ibld.c: Regenerate.
859 * iq2000-ibld.c: Regenerate.
860 * lm32-ibld.c: Regenerate.
861 * m32c-ibld.c: Regenerate.
862 * m32r-ibld.c: Regenerate.
863 * mep-ibld.c: Regenerate.
864 * mt-ibld.c: Regenerate.
865 * or1k-ibld.c: Regenerate.
866 * xc16x-ibld.c: Regenerate.
867 * xstormy16-ibld.c: Regenerate.
869 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
871 * epiphany-dis.c: Regenerated from latest cpu files.
873 2016-02-01 Michael McConville <mmcco@mykolab.com>
875 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
878 2016-01-25 Renlin Li <renlin.li@arm.com>
880 * arm-dis.c (mapping_symbol_for_insn): New function.
881 (find_ifthen_state): Call mapping_symbol_for_insn().
883 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
885 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
886 of MSR UAO immediate operand.
888 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
890 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
893 2016-01-17 Alan Modra <amodra@gmail.com>
895 * configure: Regenerate.
897 2016-01-14 Nick Clifton <nickc@redhat.com>
899 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
900 instructions that can support stack pointer operations.
901 * rl78-decode.c: Regenerate.
902 * rl78-dis.c: Fix display of stack pointer in MOVW based
905 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
907 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
908 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
909 erxtatus_el1 and erxaddr_el1.
911 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
913 * arm-dis.c (arm_opcodes): Add "esb".
914 (thumb_opcodes): Likewise.
916 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
918 * ppc-opc.c <xscmpnedp>: Delete.
919 <xvcmpnedp>: Likewise.
920 <xvcmpnedp.>: Likewise.
921 <xvcmpnesp>: Likewise.
922 <xvcmpnesp.>: Likewise.
924 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
927 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
930 2016-01-01 Alan Modra <amodra@gmail.com>
932 Update year range in copyright notice of all files.
934 For older changes see ChangeLog-2015
936 Copyright (C) 2016 Free Software Foundation, Inc.
938 Copying and distribution of this file, with or without modification,
939 are permitted in any medium without royalty provided the copyright
940 notice and this notice are preserved.
946 version-control: never