1 2016-11-03 Graham Markall <graham.markall@embecosm.com>
3 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
5 (find_format_long_instructions): Likewise.
6 * arc-opc.c (arc_opcode_len): New function.
8 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
10 * arc-nps400-tbl.h: Fix some instruction masks.
12 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
14 * i386-dis.c (REG_82): Removed.
15 (X86_64_82_REG_0): Likewise.
16 (X86_64_82_REG_1): Likewise.
17 (X86_64_82_REG_2): Likewise.
18 (X86_64_82_REG_3): Likewise.
19 (X86_64_82_REG_4): Likewise.
20 (X86_64_82_REG_5): Likewise.
21 (X86_64_82_REG_6): Likewise.
22 (X86_64_82_REG_7): Likewise.
24 (dis386): Use X86_64_82 instead of REG_82.
25 (reg_table): Remove REG_82.
26 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
27 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
28 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
31 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
34 * i386-dis.c (REG_82): New.
35 (X86_64_82_REG_0): Likewise.
36 (X86_64_82_REG_1): Likewise.
37 (X86_64_82_REG_2): Likewise.
38 (X86_64_82_REG_3): Likewise.
39 (X86_64_82_REG_4): Likewise.
40 (X86_64_82_REG_5): Likewise.
41 (X86_64_82_REG_6): Likewise.
42 (X86_64_82_REG_7): Likewise.
44 (reg_table): Add REG_82.
45 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
46 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
47 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
49 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
51 * i386-dis.c (REG_82): Renamed to ...
54 (reg_table): Likewise.
56 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
58 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
59 * i386-dis-evex.h (evex_table): Updated.
60 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
61 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
62 (cpu_flags): Add CpuAVX512_4VNNIW.
63 * i386-opc.h (enum): (AVX512_4VNNIW): New.
64 (i386_cpu_flags): Add cpuavx512_4vnniw.
65 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
66 * i386-init.h: Regenerate.
69 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
71 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
72 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
73 * i386-dis-evex.h (evex_table): Updated.
74 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
75 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
76 (cpu_flags): Add CpuAVX512_4FMAPS.
77 (opcode_modifiers): Add ImplicitQuadGroup modifier.
78 * i386-opc.h (AVX512_4FMAP): New.
79 (i386_cpu_flags): Add cpuavx512_4fmaps.
80 (ImplicitQuadGroup): New.
81 (i386_opcode_modifier): Add implicitquadgroup.
82 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
83 * i386-init.h: Regenerate.
86 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
87 Andrew Waterman <andrew@sifive.com>
89 Add support for RISC-V architecture.
90 * configure.ac: Add entry for bfd_riscv_arch.
91 * configure: Regenerate.
92 * disassemble.c (disassembler): Add support for riscv.
93 (disassembler_usage): Likewise.
94 * riscv-dis.c: New file.
95 * riscv-opc.c: New file.
97 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
99 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
100 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
101 (rm_table): Update the RM_0FAE_REG_7 entry.
102 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
103 (cpu_flags): Remove CpuPCOMMIT.
104 * i386-opc.h (CpuPCOMMIT): Removed.
105 (i386_cpu_flags): Remove cpupcommit.
106 * i386-opc.tbl: Remove pcommit.
107 * i386-init.h: Regenerated.
108 * i386-tbl.h: Likewise.
110 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
113 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
114 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
115 32-bit mode. Don't check vex.register_specifier in 32-bit
117 (OP_VEX): Check for invalid mask registers.
119 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
122 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
125 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
128 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
130 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
132 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
133 local variable to `index_regno'.
135 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
137 * arc-tbl.h: Removed any "inv.+" instructions from the table.
139 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
141 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
144 2016-10-11 Jiong Wang <jiong.wang@arm.com>
147 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
149 2016-10-07 Jiong Wang <jiong.wang@arm.com>
152 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
155 2016-10-07 Alan Modra <amodra@gmail.com>
157 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
159 2016-10-06 Alan Modra <amodra@gmail.com>
161 * aarch64-opc.c: Spell fall through comments consistently.
162 * i386-dis.c: Likewise.
163 * aarch64-dis.c: Add missing fall through comments.
164 * aarch64-opc.c: Likewise.
165 * arc-dis.c: Likewise.
166 * arm-dis.c: Likewise.
167 * i386-dis.c: Likewise.
168 * m68k-dis.c: Likewise.
169 * mep-asm.c: Likewise.
170 * ns32k-dis.c: Likewise.
171 * sh-dis.c: Likewise.
172 * tic4x-dis.c: Likewise.
173 * tic6x-dis.c: Likewise.
174 * vax-dis.c: Likewise.
176 2016-10-06 Alan Modra <amodra@gmail.com>
178 * arc-ext.c (create_map): Add missing break.
179 * msp430-decode.opc (encode_as): Likewise.
180 * msp430-decode.c: Regenerate.
182 2016-10-06 Alan Modra <amodra@gmail.com>
184 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
185 * crx-dis.c (print_insn_crx): Likewise.
187 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
190 * i386-dis.c (putop): Don't assign alt twice.
192 2016-09-29 Jiong Wang <jiong.wang@arm.com>
195 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
197 2016-09-29 Alan Modra <amodra@gmail.com>
199 * ppc-opc.c (L): Make compulsory.
200 (LOPT): New, optional form of L.
201 (HTM_R): Define as LOPT.
203 (L32OPT): New, optional for 32-bit L.
204 (L2OPT): New, 2-bit L for dcbf.
207 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
208 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
210 <tlbiel, tlbie>: Use LOPT.
211 <wclr, wclrall>: Use L2.
213 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
215 * Makefile.in: Regenerate.
216 * configure: Likewise.
218 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
220 * arc-ext-tbl.h (EXTINSN2OPF): Define.
221 (EXTINSN2OP): Use EXTINSN2OPF.
222 (bspeekm, bspop, modapp): New extension instructions.
223 * arc-opc.c (F_DNZ_ND): Define.
228 * arc-tbl.h (dbnz): New instruction.
229 (prealloc): Allow it for ARC EM.
232 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
234 * aarch64-opc.c (print_immediate_offset_address): Print spaces
235 after commas in addresses.
236 (aarch64_print_operand): Likewise.
238 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
240 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
241 rather than "should be" or "expected to be" in error messages.
243 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
245 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
246 (print_mnemonic_name): ...here.
247 (print_comment): New function.
248 (print_aarch64_insn): Call it.
249 * aarch64-opc.c (aarch64_conds): Add SVE names.
250 (aarch64_print_operand): Print alternative condition names in
253 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
255 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
256 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
257 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
258 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
259 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
260 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
261 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
262 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
263 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
264 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
265 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
266 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
267 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
268 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
269 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
270 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
271 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
272 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
273 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
274 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
275 (OP_SVE_XWU, OP_SVE_XXU): New macros.
276 (aarch64_feature_sve): New variable.
278 (_SVE_INSN): Likewise.
279 (aarch64_opcode_table): Add SVE instructions.
280 * aarch64-opc.h (extract_fields): Declare.
281 * aarch64-opc-2.c: Regenerate.
282 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
283 * aarch64-asm-2.c: Regenerate.
284 * aarch64-dis.c (extract_fields): Make global.
285 (do_misc_decoding): Handle the new SVE aarch64_ops.
286 * aarch64-dis-2.c: Regenerate.
288 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
290 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
291 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
293 * aarch64-opc.c (fields): Add corresponding entries.
294 * aarch64-asm.c (aarch64_get_variant): New function.
295 (aarch64_encode_variant_using_iclass): Likewise.
296 (aarch64_opcode_encode): Call it.
297 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
298 (aarch64_opcode_decode): Call it.
300 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
302 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
303 and FP register operands.
304 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
305 (FLD_SVE_Vn): New aarch64_field_kinds.
306 * aarch64-opc.c (fields): Add corresponding entries.
307 (aarch64_print_operand): Handle the new SVE core and FP register
309 * aarch64-opc-2.c: Regenerate.
310 * aarch64-asm-2.c: Likewise.
311 * aarch64-dis-2.c: Likewise.
313 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
315 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
317 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
318 * aarch64-opc.c (fields): Add corresponding entry.
319 (operand_general_constraint_met_p): Handle the new SVE FP immediate
321 (aarch64_print_operand): Likewise.
322 * aarch64-opc-2.c: Regenerate.
323 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
324 (ins_sve_float_zero_one): New inserters.
325 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
326 (aarch64_ins_sve_float_half_two): Likewise.
327 (aarch64_ins_sve_float_zero_one): Likewise.
328 * aarch64-asm-2.c: Regenerate.
329 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
330 (ext_sve_float_zero_one): New extractors.
331 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
332 (aarch64_ext_sve_float_half_two): Likewise.
333 (aarch64_ext_sve_float_zero_one): Likewise.
334 * aarch64-dis-2.c: Regenerate.
336 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
338 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
339 integer immediate operands.
340 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
341 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
342 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
343 * aarch64-opc.c (fields): Add corresponding entries.
344 (operand_general_constraint_met_p): Handle the new SVE integer
346 (aarch64_print_operand): Likewise.
347 (aarch64_sve_dupm_mov_immediate_p): New function.
348 * aarch64-opc-2.c: Regenerate.
349 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
350 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
351 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
352 (aarch64_ins_limm): ...here.
353 (aarch64_ins_inv_limm): New function.
354 (aarch64_ins_sve_aimm): Likewise.
355 (aarch64_ins_sve_asimm): Likewise.
356 (aarch64_ins_sve_limm_mov): Likewise.
357 (aarch64_ins_sve_shlimm): Likewise.
358 (aarch64_ins_sve_shrimm): Likewise.
359 * aarch64-asm-2.c: Regenerate.
360 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
361 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
362 * aarch64-dis.c (decode_limm): New function, split out from...
363 (aarch64_ext_limm): ...here.
364 (aarch64_ext_inv_limm): New function.
365 (decode_sve_aimm): Likewise.
366 (aarch64_ext_sve_aimm): Likewise.
367 (aarch64_ext_sve_asimm): Likewise.
368 (aarch64_ext_sve_limm_mov): Likewise.
369 (aarch64_top_bit): Likewise.
370 (aarch64_ext_sve_shlimm): Likewise.
371 (aarch64_ext_sve_shrimm): Likewise.
372 * aarch64-dis-2.c: Regenerate.
374 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
376 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
378 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
379 the AARCH64_MOD_MUL_VL entry.
380 (value_aligned_p): Cope with non-power-of-two alignments.
381 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
382 (print_immediate_offset_address): Likewise.
383 (aarch64_print_operand): Likewise.
384 * aarch64-opc-2.c: Regenerate.
385 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
386 (ins_sve_addr_ri_s9xvl): New inserters.
387 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
388 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
389 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
390 * aarch64-asm-2.c: Regenerate.
391 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
392 (ext_sve_addr_ri_s9xvl): New extractors.
393 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
394 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
395 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
396 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
397 * aarch64-dis-2.c: Regenerate.
399 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
401 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
403 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
404 (FLD_SVE_xs_22): New aarch64_field_kinds.
405 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
406 (get_operand_specific_data): New function.
407 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
408 FLD_SVE_xs_14 and FLD_SVE_xs_22.
409 (operand_general_constraint_met_p): Handle the new SVE address
411 (sve_reg): New array.
412 (get_addr_sve_reg_name): New function.
413 (aarch64_print_operand): Handle the new SVE address operands.
414 * aarch64-opc-2.c: Regenerate.
415 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
416 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
417 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
418 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
419 (aarch64_ins_sve_addr_rr_lsl): Likewise.
420 (aarch64_ins_sve_addr_rz_xtw): Likewise.
421 (aarch64_ins_sve_addr_zi_u5): Likewise.
422 (aarch64_ins_sve_addr_zz): Likewise.
423 (aarch64_ins_sve_addr_zz_lsl): Likewise.
424 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
425 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
426 * aarch64-asm-2.c: Regenerate.
427 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
428 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
429 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
430 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
431 (aarch64_ext_sve_addr_ri_u6): Likewise.
432 (aarch64_ext_sve_addr_rr_lsl): Likewise.
433 (aarch64_ext_sve_addr_rz_xtw): Likewise.
434 (aarch64_ext_sve_addr_zi_u5): Likewise.
435 (aarch64_ext_sve_addr_zz): Likewise.
436 (aarch64_ext_sve_addr_zz_lsl): Likewise.
437 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
438 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
439 * aarch64-dis-2.c: Regenerate.
441 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
443 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
444 AARCH64_OPND_SVE_PATTERN_SCALED.
445 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
446 * aarch64-opc.c (fields): Add a corresponding entry.
447 (set_multiplier_out_of_range_error): New function.
448 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
449 (operand_general_constraint_met_p): Handle
450 AARCH64_OPND_SVE_PATTERN_SCALED.
451 (print_register_offset_address): Use PRIi64 to print the
453 (aarch64_print_operand): Likewise. Handle
454 AARCH64_OPND_SVE_PATTERN_SCALED.
455 * aarch64-opc-2.c: Regenerate.
456 * aarch64-asm.h (ins_sve_scale): New inserter.
457 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
458 * aarch64-asm-2.c: Regenerate.
459 * aarch64-dis.h (ext_sve_scale): New inserter.
460 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
461 * aarch64-dis-2.c: Regenerate.
463 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
465 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
466 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
467 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
468 (FLD_SVE_prfop): Likewise.
469 * aarch64-opc.c: Include libiberty.h.
470 (aarch64_sve_pattern_array): New variable.
471 (aarch64_sve_prfop_array): Likewise.
472 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
473 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
474 AARCH64_OPND_SVE_PRFOP.
475 * aarch64-asm-2.c: Regenerate.
476 * aarch64-dis-2.c: Likewise.
477 * aarch64-opc-2.c: Likewise.
479 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
481 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
482 AARCH64_OPND_QLF_P_[ZM].
483 (aarch64_print_operand): Print /z and /m where appropriate.
485 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
487 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
488 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
489 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
490 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
491 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
492 * aarch64-opc.c (fields): Add corresponding entries here.
493 (operand_general_constraint_met_p): Check that SVE register lists
494 have the correct length. Check the ranges of SVE index registers.
495 Check for cases where p8-p15 are used in 3-bit predicate fields.
496 (aarch64_print_operand): Handle the new SVE operands.
497 * aarch64-opc-2.c: Regenerate.
498 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
499 * aarch64-asm.c (aarch64_ins_sve_index): New function.
500 (aarch64_ins_sve_reglist): Likewise.
501 * aarch64-asm-2.c: Regenerate.
502 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
503 * aarch64-dis.c (aarch64_ext_sve_index): New function.
504 (aarch64_ext_sve_reglist): Likewise.
505 * aarch64-dis-2.c: Regenerate.
507 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
509 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
510 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
511 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
512 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
515 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
517 * aarch64-opc.c (get_offset_int_reg_name): New function.
518 (print_immediate_offset_address): Likewise.
519 (print_register_offset_address): Take the base and offset
520 registers as parameters.
521 (aarch64_print_operand): Update caller accordingly. Use
522 print_immediate_offset_address.
524 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
526 * aarch64-opc.c (BANK): New macro.
527 (R32, R64): Take a register number as argument
530 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
532 * aarch64-opc.c (print_register_list): Add a prefix parameter.
533 (aarch64_print_operand): Update accordingly.
535 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
537 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
539 * aarch64-asm.h (ins_fpimm): New inserter.
540 * aarch64-asm.c (aarch64_ins_fpimm): New function.
541 * aarch64-asm-2.c: Regenerate.
542 * aarch64-dis.h (ext_fpimm): New extractor.
543 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
544 (aarch64_ext_fpimm): New function.
545 * aarch64-dis-2.c: Regenerate.
547 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
549 * aarch64-asm.c: Include libiberty.h.
550 (insert_fields): New function.
551 (aarch64_ins_imm): Use it.
552 * aarch64-dis.c (extract_fields): New function.
553 (aarch64_ext_imm): Use it.
555 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
557 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
558 with an esize parameter.
559 (operand_general_constraint_met_p): Update accordingly.
560 Fix misindented code.
561 * aarch64-asm.c (aarch64_ins_limm): Update call to
562 aarch64_logical_immediate_p.
564 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
566 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
568 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
570 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
572 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
574 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
576 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
578 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
579 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
580 xor3>: Delete mnemonics.
581 <cp_abort>: Rename mnemonic from ...
582 <cpabort>: ...to this.
583 <setb>: Change to a X form instruction.
584 <sync>: Change to 1 operand form.
585 <copy>: Delete mnemonic.
586 <copy_first>: Rename mnemonic from ...
588 <paste, paste.>: Delete mnemonics.
589 <paste_last>: Rename mnemonic from ...
590 <paste.>: ...to this.
592 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
594 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
596 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
598 * s390-mkopc.c (main): Support alternate arch strings.
600 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
602 * s390-opc.txt: Fix kmctr instruction type.
604 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
606 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
607 * i386-init.h: Regenerated.
609 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
611 * opcodes/arc-dis.c (print_insn_arc): Changed.
613 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
615 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
618 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
620 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
621 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
622 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
624 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
626 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
627 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
628 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
629 PREFIX_MOD_3_0FAE_REG_4.
630 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
631 PREFIX_MOD_3_0FAE_REG_4.
632 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
633 (cpu_flags): Add CpuPTWRITE.
634 * i386-opc.h (CpuPTWRITE): New.
635 (i386_cpu_flags): Add cpuptwrite.
636 * i386-opc.tbl: Add ptwrite instruction.
637 * i386-init.h: Regenerated.
638 * i386-tbl.h: Likewise.
640 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
642 * arc-dis.h: Wrap around in extern "C".
644 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
646 * aarch64-tbl.h (V8_2_INSN): New macro.
647 (aarch64_opcode_table): Use it.
649 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
651 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
652 CORE_INSN, __FP_INSN and SIMD_INSN.
654 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
656 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
657 (aarch64_opcode_table): Update uses accordingly.
659 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
660 Kwok Cheung Yeung <kcy@codesourcery.com>
663 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
664 'e_cmplwi' to 'e_cmpli' instead.
665 (OPVUPRT, OPVUPRT_MASK): Define.
666 (powerpc_opcodes): Add E200Z4 insns.
667 (vle_opcodes): Add context save/restore insns.
669 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
671 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
672 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
675 2016-07-27 Graham Markall <graham.markall@embecosm.com>
677 * arc-nps400-tbl.h: Change block comments to GNU format.
678 * arc-dis.c: Add new globals addrtypenames,
679 addrtypenames_max, and addtypeunknown.
680 (get_addrtype): New function.
681 (print_insn_arc): Print colons and address types when
683 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
684 define insert and extract functions for all address types.
685 (arc_operands): Add operands for colon and all address
687 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
688 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
689 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
690 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
691 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
692 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
694 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
696 * configure: Regenerated.
698 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
700 * arc-dis.c (skipclass): New structure.
701 (decodelist): New variable.
702 (is_compatible_p): New function.
703 (new_element): Likewise.
704 (skip_class_p): Likewise.
705 (find_format_from_table): Use skip_class_p function.
706 (find_format): Decode first the extension instructions.
707 (print_insn_arc): Select either ARCEM or ARCHS based on elf
709 (parse_option): New function.
710 (parse_disassembler_options): Likewise.
711 (print_arc_disassembler_options): Likewise.
712 (print_insn_arc): Use parse_disassembler_options function. Proper
713 select ARCv2 cpu variant.
714 * disassemble.c (disassembler_usage): Add ARC disassembler
717 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
719 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
720 annotation from the "nal" entry and reorder it beyond "bltzal".
722 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
724 * sparc-opc.c (ldtxa): New macro.
725 (sparc_opcodes): Use the macro defined above to add entries for
726 the LDTXA instructions.
727 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
730 2016-07-07 James Bowman <james.bowman@ftdichip.com>
732 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
735 2016-07-01 Jan Beulich <jbeulich@suse.com>
737 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
738 (movzb): Adjust to cover all permitted suffixes.
740 * i386-tbl.h: Re-generate.
742 2016-07-01 Jan Beulich <jbeulich@suse.com>
744 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
745 (lgdt): Remove Tbyte from non-64-bit variant.
746 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
747 xsaves64, xsavec64): Remove Disp16.
748 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
749 Remove Disp32S from non-64-bit variants. Remove Disp16 from
751 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
752 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
753 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
755 * i386-tbl.h: Re-generate.
757 2016-07-01 Jan Beulich <jbeulich@suse.com>
759 * i386-opc.tbl (xlat): Remove RepPrefixOk.
760 * i386-tbl.h: Re-generate.
762 2016-06-30 Yao Qi <yao.qi@linaro.org>
764 * arm-dis.c (print_insn): Fix typo in comment.
766 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
768 * aarch64-opc.c (operand_general_constraint_met_p): Check the
769 range of ldst_elemlist operands.
770 (print_register_list): Use PRIi64 to print the index.
771 (aarch64_print_operand): Likewise.
773 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
775 * mcore-opc.h: Remove sentinal.
776 * mcore-dis.c (print_insn_mcore): Adjust.
778 2016-06-23 Graham Markall <graham.markall@embecosm.com>
780 * arc-opc.c: Correct description of availability of NPS400
783 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
785 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
786 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
787 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
788 xor3>: New mnemonics.
789 <setb>: Change to a VX form instruction.
790 (insert_sh6): Add support for rldixor.
791 (extract_sh6): Likewise.
793 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
795 * arc-ext.h: Wrap in extern C.
797 2016-06-21 Graham Markall <graham.markall@embecosm.com>
799 * arc-dis.c (arc_insn_length): Add comment on instruction length.
800 Use same method for determining instruction length on ARC700 and
802 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
803 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
804 with the NPS400 subclass.
805 * arc-opc.c: Likewise.
807 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
809 * sparc-opc.c (rdasr): New macro.
815 (sparc_opcodes): Use the macros above to fix and expand the
816 definition of read/write instructions from/to
817 asr/privileged/hyperprivileged instructions.
818 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
819 %hva_mask_nz. Prefer softint_set and softint_clear over
820 set_softint and clear_softint.
821 (print_insn_sparc): Support %ver in Rd.
823 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
825 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
826 architecture according to the hardware capabilities they require.
828 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
830 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
831 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
832 bfd_mach_sparc_v9{c,d,e,v,m}.
833 * sparc-opc.c (MASK_V9C): Define.
834 (MASK_V9D): Likewise.
835 (MASK_V9E): Likewise.
836 (MASK_V9V): Likewise.
837 (MASK_V9M): Likewise.
838 (v6): Add MASK_V9{C,D,E,V,M}.
839 (v6notlet): Likewise.
843 (v9andleon): Likewise.
851 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
853 2016-06-15 Nick Clifton <nickc@redhat.com>
855 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
856 constants to match expected behaviour.
857 (nds32_parse_opcode): Likewise. Also for whitespace.
859 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
861 * arc-opc.c (extract_rhv1): Extract value from insn.
863 2016-06-14 Graham Markall <graham.markall@embecosm.com>
865 * arc-nps400-tbl.h: Add ldbit instruction.
866 * arc-opc.c: Add flag classes required for ldbit.
868 2016-06-14 Graham Markall <graham.markall@embecosm.com>
870 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
871 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
872 support the above instructions.
874 2016-06-14 Graham Markall <graham.markall@embecosm.com>
876 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
877 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
878 csma, cbba, zncv, and hofs.
879 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
880 support the above instructions.
882 2016-06-06 Graham Markall <graham.markall@embecosm.com>
884 * arc-nps400-tbl.h: Add andab and orab instructions.
886 2016-06-06 Graham Markall <graham.markall@embecosm.com>
888 * arc-nps400-tbl.h: Add addl-like instructions.
890 2016-06-06 Graham Markall <graham.markall@embecosm.com>
892 * arc-nps400-tbl.h: Add mxb and imxb instructions.
894 2016-06-06 Graham Markall <graham.markall@embecosm.com>
896 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
899 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
901 * s390-dis.c (option_use_insn_len_bits_p): New file scope
903 (init_disasm): Handle new command line option "insnlength".
904 (print_s390_disassembler_options): Mention new option in help
906 (print_insn_s390): Use the encoded insn length when dumping
907 unknown instructions.
909 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
911 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
912 to the address and set as symbol address for LDS/ STS immediate operands.
914 2016-06-07 Alan Modra <amodra@gmail.com>
916 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
917 cpu for "vle" to e500.
918 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
919 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
920 (PPCNONE): Delete, substitute throughout.
921 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
922 except for major opcode 4 and 31.
923 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
925 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
927 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
928 ARM_EXT_RAS in relevant entries.
930 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
933 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
936 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
939 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
941 Add comments for '&'.
942 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
944 (intel_operand_size): Handle indir_v_mode.
945 (OP_E_register): Likewise.
946 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
947 64-bit indirect call/jmp for AMD64.
948 * i386-tbl.h: Regenerated
950 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
952 * arc-dis.c (struct arc_operand_iterator): New structure.
953 (find_format_from_table): All the old content from find_format,
954 with some minor adjustments, and parameter renaming.
955 (find_format_long_instructions): New function.
956 (find_format): Rewritten.
957 (arc_insn_length): Add LSB parameter.
958 (extract_operand_value): New function.
959 (operand_iterator_next): New function.
960 (print_insn_arc): Use new functions to find opcode, and iterator
962 * arc-opc.c (insert_nps_3bit_dst_short): New function.
963 (extract_nps_3bit_dst_short): New function.
964 (insert_nps_3bit_src2_short): New function.
965 (extract_nps_3bit_src2_short): New function.
966 (insert_nps_bitop1_size): New function.
967 (extract_nps_bitop1_size): New function.
968 (insert_nps_bitop2_size): New function.
969 (extract_nps_bitop2_size): New function.
970 (insert_nps_bitop_mod4_msb): New function.
971 (extract_nps_bitop_mod4_msb): New function.
972 (insert_nps_bitop_mod4_lsb): New function.
973 (extract_nps_bitop_mod4_lsb): New function.
974 (insert_nps_bitop_dst_pos3_pos4): New function.
975 (extract_nps_bitop_dst_pos3_pos4): New function.
976 (insert_nps_bitop_ins_ext): New function.
977 (extract_nps_bitop_ins_ext): New function.
978 (arc_operands): Add new operands.
979 (arc_long_opcodes): New global array.
980 (arc_num_long_opcodes): New global.
981 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
983 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
985 * nds32-asm.h: Add extern "C".
986 * sh-opc.h: Likewise.
988 2016-06-01 Graham Markall <graham.markall@embecosm.com>
990 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
991 0,b,limm to the rflt instruction.
993 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
995 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
998 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1001 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1002 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1003 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1004 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1005 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1006 * i386-init.h: Regenerated.
1008 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1011 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1012 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1013 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1014 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1015 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1016 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1017 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1018 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1019 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1020 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1021 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1022 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1023 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1024 CpuRegMask for AVX512.
1025 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1027 (set_bitfield_from_cpu_flag_init): New function.
1028 (set_bitfield): Remove const on f. Call
1029 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1030 * i386-opc.h (CpuRegMMX): New.
1031 (CpuRegXMM): Likewise.
1032 (CpuRegYMM): Likewise.
1033 (CpuRegZMM): Likewise.
1034 (CpuRegMask): Likewise.
1035 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1037 * i386-init.h: Regenerated.
1038 * i386-tbl.h: Likewise.
1040 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1043 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1044 (opcode_modifiers): Add AMD64 and Intel64.
1045 (main): Properly verify CpuMax.
1046 * i386-opc.h (CpuAMD64): Removed.
1047 (CpuIntel64): Likewise.
1048 (CpuMax): Set to CpuNo64.
1049 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1051 (Intel64): Likewise.
1052 (i386_opcode_modifier): Add amd64 and intel64.
1053 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1055 * i386-init.h: Regenerated.
1056 * i386-tbl.h: Likewise.
1058 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1061 * i386-gen.c (main): Fail if CpuMax is incorrect.
1062 * i386-opc.h (CpuMax): Set to CpuIntel64.
1063 * i386-tbl.h: Regenerated.
1065 2016-05-27 Nick Clifton <nickc@redhat.com>
1068 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1069 (msp430dis_opcode_unsigned): New function.
1070 (msp430dis_opcode_signed): New function.
1071 (msp430_singleoperand): Use the new opcode reading functions.
1072 Only disassenmble bytes if they were successfully read.
1073 (msp430_doubleoperand): Likewise.
1074 (msp430_branchinstr): Likewise.
1075 (msp430x_callx_instr): Likewise.
1076 (print_insn_msp430): Check that it is safe to read bytes before
1077 attempting disassembly. Use the new opcode reading functions.
1079 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1081 * ppc-opc.c (CY): New define. Document it.
1082 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1084 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1086 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1087 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1088 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1089 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1091 * i386-init.h: Regenerated.
1093 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1096 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1097 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1098 * i386-init.h: Regenerated.
1100 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1102 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1103 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1104 * i386-init.h: Regenerated.
1106 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1108 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1110 (print_insn_arc): Set insn_type information.
1111 * arc-opc.c (C_CC): Add F_CLASS_COND.
1112 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1113 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1114 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1115 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1116 (brne, brne_s, jeq_s, jne_s): Likewise.
1118 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1120 * arc-tbl.h (neg): New instruction variant.
1122 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1124 * arc-dis.c (find_format, find_format, get_auxreg)
1125 (print_insn_arc): Changed.
1126 * arc-ext.h (INSERT_XOP): Likewise.
1128 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1130 * tic54x-dis.c (sprint_mmr): Adjust.
1131 * tic54x-opc.c: Likewise.
1133 2016-05-19 Alan Modra <amodra@gmail.com>
1135 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1137 2016-05-19 Alan Modra <amodra@gmail.com>
1139 * ppc-opc.c: Formatting.
1140 (NSISIGNOPT): Define.
1141 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1143 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1145 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1146 replacing references to `micromips_ase' throughout.
1147 (_print_insn_mips): Don't use file-level microMIPS annotation to
1148 determine the disassembly mode with the symbol table.
1150 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1152 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1154 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1156 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1158 * mips-opc.c (D34): New macro.
1159 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1161 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1163 * i386-dis.c (prefix_table): Add RDPID instruction.
1164 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1165 (cpu_flags): Add RDPID bitfield.
1166 * i386-opc.h (enum): Add RDPID element.
1167 (i386_cpu_flags): Add RDPID field.
1168 * i386-opc.tbl: Add RDPID instruction.
1169 * i386-init.h: Regenerate.
1170 * i386-tbl.h: Regenerate.
1172 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1174 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1175 branch type of a symbol.
1176 (print_insn): Likewise.
1178 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1180 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1181 Mainline Security Extensions instructions.
1182 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1183 Extensions instructions.
1184 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1186 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1189 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1191 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1193 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1195 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1196 (arcExtMap_genOpcode): Likewise.
1197 * arc-opc.c (arg_32bit_rc): Define new variable.
1198 (arg_32bit_u6): Likewise.
1199 (arg_32bit_limm): Likewise.
1201 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1203 * aarch64-gen.c (VERIFIER): Define.
1204 * aarch64-opc.c (VERIFIER): Define.
1205 (verify_ldpsw): Use static linkage.
1206 * aarch64-opc.h (verify_ldpsw): Remove.
1207 * aarch64-tbl.h: Use VERIFIER for verifiers.
1209 2016-04-28 Nick Clifton <nickc@redhat.com>
1212 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1213 * aarch64-opc.c (verify_ldpsw): New function.
1214 * aarch64-opc.h (verify_ldpsw): New prototype.
1215 * aarch64-tbl.h: Add initialiser for verifier field.
1216 (LDPSW): Set verifier to verify_ldpsw.
1218 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1222 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1223 smaller than address size.
1225 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1227 * alpha-dis.c: Regenerate.
1228 * crx-dis.c: Likewise.
1229 * disassemble.c: Likewise.
1230 * epiphany-opc.c: Likewise.
1231 * fr30-opc.c: Likewise.
1232 * frv-opc.c: Likewise.
1233 * ip2k-opc.c: Likewise.
1234 * iq2000-opc.c: Likewise.
1235 * lm32-opc.c: Likewise.
1236 * lm32-opinst.c: Likewise.
1237 * m32c-opc.c: Likewise.
1238 * m32r-opc.c: Likewise.
1239 * m32r-opinst.c: Likewise.
1240 * mep-opc.c: Likewise.
1241 * mt-opc.c: Likewise.
1242 * or1k-opc.c: Likewise.
1243 * or1k-opinst.c: Likewise.
1244 * tic80-opc.c: Likewise.
1245 * xc16x-opc.c: Likewise.
1246 * xstormy16-opc.c: Likewise.
1248 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1250 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1251 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1252 calcsd, and calcxd instructions.
1253 * arc-opc.c (insert_nps_bitop_size): Delete.
1254 (extract_nps_bitop_size): Delete.
1255 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1256 (extract_nps_qcmp_m3): Define.
1257 (extract_nps_qcmp_m2): Define.
1258 (extract_nps_qcmp_m1): Define.
1259 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1260 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1261 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1262 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1263 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1266 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1268 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1270 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1272 * Makefile.in: Regenerated with automake 1.11.6.
1273 * aclocal.m4: Likewise.
1275 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1277 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1279 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1280 (extract_nps_cmem_uimm16): New function.
1281 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1283 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1285 * arc-dis.c (arc_insn_length): New function.
1286 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1287 (find_format): Change insnLen parameter to unsigned.
1289 2016-04-13 Nick Clifton <nickc@redhat.com>
1292 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1293 the LD.B and LD.BU instructions.
1295 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1297 * arc-dis.c (find_format): Check for extension flags.
1298 (print_flags): New function.
1299 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1301 * arc-ext.c (arcExtMap_coreRegName): Use
1302 LAST_EXTENSION_CORE_REGISTER.
1303 (arcExtMap_coreReadWrite): Likewise.
1304 (dump_ARC_extmap): Update printing.
1305 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1306 (arc_aux_regs): Add cpu field.
1307 * arc-regs.h: Add cpu field, lower case name aux registers.
1309 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1311 * arc-tbl.h: Add rtsc, sleep with no arguments.
1313 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1315 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1317 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1318 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1319 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1320 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1321 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1322 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1323 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1324 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1325 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1326 (arc_opcode arc_opcodes): Null terminate the array.
1327 (arc_num_opcodes): Remove.
1328 * arc-ext.h (INSERT_XOP): Define.
1329 (extInstruction_t): Likewise.
1330 (arcExtMap_instName): Delete.
1331 (arcExtMap_insn): New function.
1332 (arcExtMap_genOpcode): Likewise.
1333 * arc-ext.c (ExtInstruction): Remove.
1334 (create_map): Zero initialize instruction fields.
1335 (arcExtMap_instName): Remove.
1336 (arcExtMap_insn): New function.
1337 (dump_ARC_extmap): More info while debuging.
1338 (arcExtMap_genOpcode): New function.
1339 * arc-dis.c (find_format): New function.
1340 (print_insn_arc): Use find_format.
1341 (arc_get_disassembler): Enable dump_ARC_extmap only when
1344 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1346 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1347 instruction bits out.
1349 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1351 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1352 * arc-opc.c (arc_flag_operands): Add new flags.
1353 (arc_flag_classes): Add new classes.
1355 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1357 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1359 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1361 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1362 encode1, rflt, crc16, and crc32 instructions.
1363 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1364 (arc_flag_classes): Add C_NPS_R.
1365 (insert_nps_bitop_size_2b): New function.
1366 (extract_nps_bitop_size_2b): Likewise.
1367 (insert_nps_bitop_uimm8): Likewise.
1368 (extract_nps_bitop_uimm8): Likewise.
1369 (arc_operands): Add new operand entries.
1371 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1373 * arc-regs.h: Add a new subclass field. Add double assist
1374 accumulator register values.
1375 * arc-tbl.h: Use DPA subclass to mark the double assist
1376 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1377 * arc-opc.c (RSP): Define instead of SP.
1378 (arc_aux_regs): Add the subclass field.
1380 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1382 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1384 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1386 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1389 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1391 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1392 issues. No functional changes.
1394 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1396 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1397 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1398 (RTT): Remove duplicate.
1399 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1400 (PCT_CONFIG*): Remove.
1401 (D1L, D1H, D2H, D2L): Define.
1403 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1405 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1407 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1409 * arc-tbl.h (invld07): Remove.
1410 * arc-ext-tbl.h: New file.
1411 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1412 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1414 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1416 Fix -Wstack-usage warnings.
1417 * aarch64-dis.c (print_operands): Substitute size.
1418 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1420 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1422 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1423 to get a proper diagnostic when an invalid ASR register is used.
1425 2016-03-22 Nick Clifton <nickc@redhat.com>
1427 * configure: Regenerate.
1429 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1431 * arc-nps400-tbl.h: New file.
1432 * arc-opc.c: Add top level comment.
1433 (insert_nps_3bit_dst): New function.
1434 (extract_nps_3bit_dst): New function.
1435 (insert_nps_3bit_src2): New function.
1436 (extract_nps_3bit_src2): New function.
1437 (insert_nps_bitop_size): New function.
1438 (extract_nps_bitop_size): New function.
1439 (arc_flag_operands): Add nps400 entries.
1440 (arc_flag_classes): Add nps400 entries.
1441 (arc_operands): Add nps400 entries.
1442 (arc_opcodes): Add nps400 include.
1444 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1446 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1447 the new class enum values.
1449 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1451 * arc-dis.c (print_insn_arc): Handle nps400.
1453 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1455 * arc-opc.c (BASE): Delete.
1457 2016-03-18 Nick Clifton <nickc@redhat.com>
1460 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1461 of MOV insn that aliases an ORR insn.
1463 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1465 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1467 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1469 * mcore-opc.h: Add const qualifiers.
1470 * microblaze-opc.h (struct op_code_struct): Likewise.
1471 * sh-opc.h: Likewise.
1472 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1473 (tic4x_print_op): Likewise.
1475 2016-03-02 Alan Modra <amodra@gmail.com>
1477 * or1k-desc.h: Regenerate.
1478 * fr30-ibld.c: Regenerate.
1479 * rl78-decode.c: Regenerate.
1481 2016-03-01 Nick Clifton <nickc@redhat.com>
1484 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1486 2016-02-24 Renlin Li <renlin.li@arm.com>
1488 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1489 (print_insn_coprocessor): Support fp16 instructions.
1491 2016-02-24 Renlin Li <renlin.li@arm.com>
1493 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1494 vminnm, vrint(mpna).
1496 2016-02-24 Renlin Li <renlin.li@arm.com>
1498 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1499 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1501 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1503 * i386-dis.c (print_insn): Parenthesize expression to prevent
1504 truncated addresses.
1507 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1508 Janek van Oirschot <jvanoirs@synopsys.com>
1510 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1513 2016-02-04 Nick Clifton <nickc@redhat.com>
1516 * msp430-dis.c (print_insn_msp430): Add a special case for
1517 decoding an RRC instruction with the ZC bit set in the extension
1520 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1522 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1523 * epiphany-ibld.c: Regenerate.
1524 * fr30-ibld.c: Regenerate.
1525 * frv-ibld.c: Regenerate.
1526 * ip2k-ibld.c: Regenerate.
1527 * iq2000-ibld.c: Regenerate.
1528 * lm32-ibld.c: Regenerate.
1529 * m32c-ibld.c: Regenerate.
1530 * m32r-ibld.c: Regenerate.
1531 * mep-ibld.c: Regenerate.
1532 * mt-ibld.c: Regenerate.
1533 * or1k-ibld.c: Regenerate.
1534 * xc16x-ibld.c: Regenerate.
1535 * xstormy16-ibld.c: Regenerate.
1537 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1539 * epiphany-dis.c: Regenerated from latest cpu files.
1541 2016-02-01 Michael McConville <mmcco@mykolab.com>
1543 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1546 2016-01-25 Renlin Li <renlin.li@arm.com>
1548 * arm-dis.c (mapping_symbol_for_insn): New function.
1549 (find_ifthen_state): Call mapping_symbol_for_insn().
1551 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1553 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1554 of MSR UAO immediate operand.
1556 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1558 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1559 instruction support.
1561 2016-01-17 Alan Modra <amodra@gmail.com>
1563 * configure: Regenerate.
1565 2016-01-14 Nick Clifton <nickc@redhat.com>
1567 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1568 instructions that can support stack pointer operations.
1569 * rl78-decode.c: Regenerate.
1570 * rl78-dis.c: Fix display of stack pointer in MOVW based
1573 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1575 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1576 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1577 erxtatus_el1 and erxaddr_el1.
1579 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1581 * arm-dis.c (arm_opcodes): Add "esb".
1582 (thumb_opcodes): Likewise.
1584 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1586 * ppc-opc.c <xscmpnedp>: Delete.
1587 <xvcmpnedp>: Likewise.
1588 <xvcmpnedp.>: Likewise.
1589 <xvcmpnesp>: Likewise.
1590 <xvcmpnesp.>: Likewise.
1592 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1595 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1598 2016-01-01 Alan Modra <amodra@gmail.com>
1600 Update year range in copyright notice of all files.
1602 For older changes see ChangeLog-2015
1604 Copyright (C) 2016 Free Software Foundation, Inc.
1606 Copying and distribution of this file, with or without modification,
1607 are permitted in any medium without royalty provided the copyright
1608 notice and this notice are preserved.
1614 version-control: never