opcodes/ChangeLog

   1 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * disassemble.c (disassemble_init_for_target): Set endian_code for
   4         bpf targets.
   5         * bpf-desc.c: Regenerate.
   6         * bpf-opc.c: Likewise.
   7         * bpf-dis.c: Likewise.
   8
   9 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
  10
  11         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
  12         (cgen_put_insn_value): Likewise.
  13         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
  14         * cgen-dis.in (print_insn): Likewise.
  15         * cgen-ibld.in (insert_1): Likewise.
  16         (insert_1): Likewise.
  17         (insert_insn_normal): Likewise.
  18         (extract_1): Likewise.
  19         * bpf-dis.c: Regenerate.
  20         * bpf-ibld.c: Likewise.
  21         * bpf-ibld.c: Likewise.
  22         * cgen-dis.in: Likewise.
  23         * cgen-ibld.in: Likewise.
  24         * cgen-opc.c: Likewise.
  25         * epiphany-dis.c: Likewise.
  26         * epiphany-ibld.c: Likewise.
  27         * fr30-dis.c: Likewise.
  28         * fr30-ibld.c: Likewise.
  29         * frv-dis.c: Likewise.
  30         * frv-ibld.c: Likewise.
  31         * ip2k-dis.c: Likewise.
  32         * ip2k-ibld.c: Likewise.
  33         * iq2000-dis.c: Likewise.
  34         * iq2000-ibld.c: Likewise.
  35         * lm32-dis.c: Likewise.
  36         * lm32-ibld.c: Likewise.
  37         * m32c-dis.c: Likewise.
  38         * m32c-ibld.c: Likewise.
  39         * m32r-dis.c: Likewise.
  40         * m32r-ibld.c: Likewise.
  41         * mep-dis.c: Likewise.
  42         * mep-ibld.c: Likewise.
  43         * mt-dis.c: Likewise.
  44         * mt-ibld.c: Likewise.
  45         * or1k-dis.c: Likewise.
  46         * or1k-ibld.c: Likewise.
  47         * xc16x-dis.c: Likewise.
  48         * xc16x-ibld.c: Likewise.
  49         * xstormy16-dis.c: Likewise.
  50         * xstormy16-ibld.c: Likewise.
  51
  52 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
  53
  54         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
  55         (print_insn_): Handle instruction endian.
  56         * bpf-dis.c: Regenerate.
  57         * bpf-desc.c: Regenerate.
  58         * epiphany-dis.c: Likewise.
  59         * epiphany-desc.c: Likewise.
  60         * fr30-dis.c: Likewise.
  61         * fr30-desc.c: Likewise.
  62         * frv-dis.c: Likewise.
  63         * frv-desc.c: Likewise.
  64         * ip2k-dis.c: Likewise.
  65         * ip2k-desc.c: Likewise.
  66         * iq2000-dis.c: Likewise.
  67         * iq2000-desc.c: Likewise.
  68         * lm32-dis.c: Likewise.
  69         * lm32-desc.c: Likewise.
  70         * m32c-dis.c: Likewise.
  71         * m32c-desc.c: Likewise.
  72         * m32r-dis.c: Likewise.
  73         * m32r-desc.c: Likewise.
  74         * mep-dis.c: Likewise.
  75         * mep-desc.c: Likewise.
  76         * mt-dis.c: Likewise.
  77         * mt-desc.c: Likewise.
  78         * or1k-dis.c: Likewise.
  79         * or1k-desc.c: Likewise.
  80         * xc16x-dis.c: Likewise.
  81         * xc16x-desc.c: Likewise.
  82         * xstormy16-dis.c: Likewise.
  83         * xstormy16-desc.c: Likewise.
  84
  85 2020-06-03  Nick Clifton  <nickc@redhat.com>
  86
  87         * po/sr.po: Updated Serbian translation.
  88
  89 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
  90
  91         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
  92         (riscv_get_priv_spec_class): Likewise.
  93
  94 2020-06-01  Alan Modra  <amodra@gmail.com>
  95
  96         * bpf-desc.c: Regenerate.
  97
  98 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
  99             David Faust <david.faust@oracle.com>
 100
 101         * bpf-desc.c: Regenerate.
 102         * bpf-opc.h: Likewise.
 103         * bpf-opc.c: Likewise.
 104         * bpf-dis.c: Likewise.
 105
 106 2020-05-28  Alan Modra  <amodra@gmail.com>
 107
 108         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 109         values.
 110
 111 2020-05-28  Alan Modra  <amodra@gmail.com>
 112
 113         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 114         immediates.
 115         (print_insn_ns32k): Revert last change.
 116
 117 2020-05-28  Nick Clifton  <nickc@redhat.com>
 118
 119         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 120         static.
 121
 122 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 123
 124         Fix extraction of signed constants in nios2 disassembler (again).
 125
 126         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 127         extractions of signed fields.
 128
 129 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 130
 131         * s390-opc.txt: Relocate vector load/store instructions with
 132         additional alignment parameter and change architecture level
 133         constraint from z14 to z13.
 134
 135 2020-05-21  Alan Modra  <amodra@gmail.com>
 136
 137         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 138         * sparc-dis.c: Likewise.
 139         * tic4x-dis.c: Likewise.
 140         * xtensa-dis.c: Likewise.
 141         * bpf-desc.c: Regenerate.
 142         * epiphany-desc.c: Regenerate.
 143         * fr30-desc.c: Regenerate.
 144         * frv-desc.c: Regenerate.
 145         * ip2k-desc.c: Regenerate.
 146         * iq2000-desc.c: Regenerate.
 147         * lm32-desc.c: Regenerate.
 148         * m32c-desc.c: Regenerate.
 149         * m32r-desc.c: Regenerate.
 150         * mep-asm.c: Regenerate.
 151         * mep-desc.c: Regenerate.
 152         * mt-desc.c: Regenerate.
 153         * or1k-desc.c: Regenerate.
 154         * xc16x-desc.c: Regenerate.
 155         * xstormy16-desc.c: Regenerate.
 156
 157 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 158
 159         * riscv-opc.c (riscv_ext_version_table): The table used to store
 160         all information about the supported spec and the corresponding ISA
 161         versions.  Currently, only Zicsr is supported to verify the
 162         correctness of Z sub extension settings.  Others will be supported
 163         in the future patches.
 164         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 165         classes and the corresponding strings.
 166         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 167         spec class by giving a ISA spec string.
 168         * riscv-opc.c (struct priv_spec_t): New structure.
 169         (struct priv_spec_t priv_specs): List for all supported privilege spec
 170         classes and the corresponding strings.
 171         (riscv_get_priv_spec_class): New function.  Get the corresponding
 172         privilege spec class by giving a spec string.
 173         (riscv_get_priv_spec_name): New function.  Get the corresponding
 174         privilege spec string by giving a CSR version class.
 175         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 176         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 177         according to the chosen version.  Build a hash table riscv_csr_hash to
 178         store the valid CSR for the chosen pirv verison.  Dump the direct
 179         CSR address rather than it's name if it is invalid.
 180         (parse_riscv_dis_option_without_args): New function.  Parse the options
 181         without arguments.
 182         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 183         parse the options without arguments first, and then handle the options
 184         with arguments.  Add the new option -Mpriv-spec, which has argument.
 185         * riscv-dis.c (print_riscv_disassembler_options): Add description
 186         about the new OBJDUMP option.
 187
 188 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 189
 190         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 191         WC values on POWER10 sync, dcbf  and wait instructions.
 192         (insert_pl, extract_pl): New functions.
 193         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 194         (LS3): New , 3-bit L for sync.
 195         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 196         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 197         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 198         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 199         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 200         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 201         <wait>: Enable PL operand on POWER10.
 202         <dcbf>: Enable L3OPT operand on POWER10.
 203         <sync>: Enable SC2 operand on POWER10.
 204
 205 2020-05-19  Stafford Horne  <shorne@gmail.com>
 206
 207         PR 25184
 208         * or1k-asm.c: Regenerate.
 209         * or1k-desc.c: Regenerate.
 210         * or1k-desc.h: Regenerate.
 211         * or1k-dis.c: Regenerate.
 212         * or1k-ibld.c: Regenerate.
 213         * or1k-opc.c: Regenerate.
 214         * or1k-opc.h: Regenerate.
 215         * or1k-opinst.c: Regenerate.
 216
 217 2020-05-11  Alan Modra  <amodra@gmail.com>
 218
 219         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 220         xsmaxcqp, xsmincqp.
 221
 222 2020-05-11  Alan Modra  <amodra@gmail.com>
 223
 224         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 225         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 226
 227 2020-05-11  Alan Modra  <amodra@gmail.com>
 228
 229         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 230
 231 2020-05-11  Alan Modra  <amodra@gmail.com>
 232
 233         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 234         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 235
 236 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 237
 238         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 239         mnemonics.
 240
 241 2020-05-11  Alan Modra  <amodra@gmail.com>
 242
 243         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 244         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 245         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 246         (prefix_opcodes): Add xxeval.
 247
 248 2020-05-11  Alan Modra  <amodra@gmail.com>
 249
 250         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 251         xxgenpcvwm, xxgenpcvdm.
 252
 253 2020-05-11  Alan Modra  <amodra@gmail.com>
 254
 255         * ppc-opc.c (MP, VXVAM_MASK): Define.
 256         (VXVAPS_MASK): Use VXVA_MASK.
 257         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 258         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 259         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 260         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 261
 262 2020-05-11  Alan Modra  <amodra@gmail.com>
 263             Peter Bergner  <bergner@linux.ibm.com>
 264
 265         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 266         New functions.
 267         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 268         YMSK2, XA6a, XA6ap, XB6a entries.
 269         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 270         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 271         (PPCVSX4): Define.
 272         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 273         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 274         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 275         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 276         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 277         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 278         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 279         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 280         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 281         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 282         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 283         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 284         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 285         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 286
 287 2020-05-11  Alan Modra  <amodra@gmail.com>
 288
 289         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 290         (insert_xts, extract_xts): New functions.
 291         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 292         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 293         (VXRC_MASK, VXSH_MASK): Define.
 294         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 295         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 296         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 297         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 298         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 299         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 300         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 301
 302 2020-05-11  Alan Modra  <amodra@gmail.com>
 303
 304         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 305         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 306         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 307         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 308         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 309
 310 2020-05-11  Alan Modra  <amodra@gmail.com>
 311
 312         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 313         (XTP, DQXP, DQXP_MASK): Define.
 314         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 315         (prefix_opcodes): Add plxvp and pstxvp.
 316
 317 2020-05-11  Alan Modra  <amodra@gmail.com>
 318
 319         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 320         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 321         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 322
 323 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 324
 325         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 326
 327 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 328
 329         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 330         (L1OPT): Define.
 331         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 332
 333 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 334
 335         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 336
 337 2020-05-11  Alan Modra  <amodra@gmail.com>
 338
 339         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 340
 341 2020-05-11  Alan Modra  <amodra@gmail.com>
 342
 343         * ppc-dis.c (ppc_opts): Add "power10" entry.
 344         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 345         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 346
 347 2020-05-11  Nick Clifton  <nickc@redhat.com>
 348
 349         * po/fr.po: Updated French translation.
 350
 351 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 352
 353         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 354         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 355         (operand_general_constraint_met_p): validate
 356         AARCH64_OPND_UNDEFINED.
 357         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 358         for FLD_imm16_2.
 359         * aarch64-asm-2.c: Regenerated.
 360         * aarch64-dis-2.c: Regenerated.
 361         * aarch64-opc-2.c: Regenerated.
 362
 363 2020-04-29  Nick Clifton  <nickc@redhat.com>
 364
 365         PR 22699
 366         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 367         and SETRC insns.
 368
 369 2020-04-29  Nick Clifton  <nickc@redhat.com>
 370
 371         * po/sv.po: Updated Swedish translation.
 372
 373 2020-04-29  Nick Clifton  <nickc@redhat.com>
 374
 375         PR 22699
 376         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 377         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 378         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 379         IMM0_8U case.
 380
 381 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 382
 383         PR 25848
 384         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 385         cmpi only on m68020up and cpu32.
 386
 387 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 388
 389         * aarch64-asm.c (aarch64_ins_none): New.
 390         * aarch64-asm.h (ins_none): New declaration.
 391         * aarch64-dis.c (aarch64_ext_none): New.
 392         * aarch64-dis.h (ext_none): New declaration.
 393         * aarch64-opc.c (aarch64_print_operand): Update case for
 394         AARCH64_OPND_BARRIER_PSB.
 395         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 396         (AARCH64_OPERANDS): Update inserter/extracter for
 397         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 398         * aarch64-asm-2.c: Regenerated.
 399         * aarch64-dis-2.c: Regenerated.
 400         * aarch64-opc-2.c: Regenerated.
 401
 402 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 403
 404         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 405         (aarch64_feature_ras, RAS): Likewise.
 406         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 407         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 408         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 409         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 410         * aarch64-asm-2.c: Regenerated.
 411         * aarch64-dis-2.c: Regenerated.
 412         * aarch64-opc-2.c: Regenerated.
 413
 414 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 415
 416         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 417         (print_insn_neon): Support disassembly of conditional
 418         instructions.
 419
 420 2020-02-16  David Faust  <david.faust@oracle.com>
 421
 422         * bpf-desc.c: Regenerate.
 423         * bpf-desc.h: Likewise.
 424         * bpf-opc.c: Regenerate.
 425         * bpf-opc.h: Likewise.
 426
 427 2020-04-07  Lili Cui  <lili.cui@intel.com>
 428
 429         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 430         (prefix_table): New instructions (see prefixes above).
 431         (rm_table): Likewise
 432         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 433         CPU_ANY_TSXLDTRK_FLAGS.
 434         (cpu_flags): Add CpuTSXLDTRK.
 435         * i386-opc.h (enum): Add CpuTSXLDTRK.
 436         (i386_cpu_flags): Add cputsxldtrk.
 437         * i386-opc.tbl: Add XSUSPLDTRK insns.
 438         * i386-init.h: Regenerate.
 439         * i386-tbl.h: Likewise.
 440
 441 2020-04-02  Lili Cui  <lili.cui@intel.com>
 442
 443         * i386-dis.c (prefix_table): New instructions serialize.
 444         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 445         CPU_ANY_SERIALIZE_FLAGS.
 446         (cpu_flags): Add CpuSERIALIZE.
 447         * i386-opc.h (enum): Add CpuSERIALIZE.
 448         (i386_cpu_flags): Add cpuserialize.
 449         * i386-opc.tbl: Add SERIALIZE insns.
 450         * i386-init.h: Regenerate.
 451         * i386-tbl.h: Likewise.
 452
 453 2020-03-26  Alan Modra  <amodra@gmail.com>
 454
 455         * disassemble.h (opcodes_assert): Declare.
 456         (OPCODES_ASSERT): Define.
 457         * disassemble.c: Don't include assert.h.  Include opintl.h.
 458         (opcodes_assert): New function.
 459         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 460         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 461         calculate maxlen.  Omit insn decoding when insn length exceeds
 462         maxlen.  Exit from nibble loop when looking for E, before
 463         accessing next data byte.  Move processing of E outside loop.
 464         Replace tests of maxlen in loop with assertions.
 465
 466 2020-03-26  Alan Modra  <amodra@gmail.com>
 467
 468         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 469
 470 2020-03-25  Alan Modra  <amodra@gmail.com>
 471
 472         * z80-dis.c (suffix): Init mybuf.
 473
 474 2020-03-22  Alan Modra  <amodra@gmail.com>
 475
 476         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 477         successflly read from section.
 478
 479 2020-03-22  Alan Modra  <amodra@gmail.com>
 480
 481         * arc-dis.c (find_format): Use ISO C string concatenation rather
 482         than line continuation within a string.  Don't access needs_limm
 483         before testing opcode != NULL.
 484
 485 2020-03-22  Alan Modra  <amodra@gmail.com>
 486
 487         * ns32k-dis.c (print_insn_arg): Update comment.
 488         (print_insn_ns32k): Reduce size of index_offset array, and
 489         initialize, passing -1 to print_insn_arg for args that are not
 490         an index.  Don't exit arg loop early.  Abort on bad arg number.
 491
 492 2020-03-22  Alan Modra  <amodra@gmail.com>
 493
 494         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 495         * s12z-opc.c: Formatting.
 496         (operands_f): Return an int.
 497         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 498         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 499         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 500         (exg_sex_discrim): Likewise.
 501         (create_immediate_operand, create_bitfield_operand),
 502         (create_register_operand_with_size, create_register_all_operand),
 503         (create_register_all16_operand, create_simple_memory_operand),
 504         (create_memory_operand, create_memory_auto_operand): Don't
 505         segfault on malloc failure.
 506         (z_ext24_decode): Return an int status, negative on fail, zero
 507         on success.
 508         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 509         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 510         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 511         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 512         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 513         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 514         (loop_primitive_decode, shift_decode, psh_pul_decode),
 515         (bit_field_decode): Similarly.
 516         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 517         to return value, update callers.
 518         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 519         Don't segfault on NULL operand.
 520         (decode_operation): Return OP_INVALID on first fail.
 521         (decode_s12z): Check all reads, returning -1 on fail.
 522
 523 2020-03-20  Alan Modra  <amodra@gmail.com>
 524
 525         * metag-dis.c (print_insn_metag): Don't ignore status from
 526         read_memory_func.
 527
 528 2020-03-20  Alan Modra  <amodra@gmail.com>
 529
 530         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 531         Initialize parts of buffer not written when handling a possible
 532         2-byte insn at end of section.  Don't attempt decoding of such
 533         an insn by the 4-byte machinery.
 534
 535 2020-03-20  Alan Modra  <amodra@gmail.com>
 536
 537         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 538         partially filled buffer.  Prevent lookup of 4-byte insns when
 539         only VLE 2-byte insns are possible due to section size.  Print
 540         ".word" rather than ".long" for 2-byte leftovers.
 541
 542 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 543
 544         PR 25641
 545         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 546
 547 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 548
 549         * i386-dis.c (X86_64_0D): Rename to ...
 550         (X86_64_0E): ... this.
 551
 552 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 555         * Makefile.in: Regenerated.
 556
 557 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 560         3-operand pseudos.
 561         * i386-tbl.h: Re-generate.
 562
 563 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 566         vprot*, vpsha*, and vpshl*.
 567         * i386-tbl.h: Re-generate.
 568
 569 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 570
 571         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 572         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 573         * i386-tbl.h: Re-generate.
 574
 575 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 576
 577         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 578         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 579         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 580         * i386-tbl.h: Re-generate.
 581
 582 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-gen.c (struct template_arg, struct template_instance,
 585         struct template_param, struct template, templates,
 586         parse_template, expand_templates): New.
 587         (process_i386_opcodes): Various local variables moved to
 588         expand_templates. Call parse_template and expand_templates.
 589         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 590         * i386-tbl.h: Re-generate.
 591
 592 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 595         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 596         register and memory source templates. Replace VexW= by VexW*
 597         where applicable.
 598         * i386-tbl.h: Re-generate.
 599
 600 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 603         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 604         * i386-tbl.h: Re-generate.
 605
 606 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 609         * i386-tbl.h: Re-generate.
 610
 611 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 614         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 615         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 616         VexW0 on SSE2AVX variants.
 617         (vmovq): Drop NoRex64 from XMM/XMM variants.
 618         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 619         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 620         applicable use VexW0.
 621         * i386-tbl.h: Re-generate.
 622
 623 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 624
 625         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 626         * i386-opc.h (Rex64): Delete.
 627         (struct i386_opcode_modifier): Remove rex64 field.
 628         * i386-opc.tbl (crc32): Drop Rex64.
 629         Replace Rex64 with Size64 everywhere else.
 630         * i386-tbl.h: Re-generate.
 631
 632 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-dis.c (OP_E_memory): Exclude recording of used address
 635         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 636         addressed memory operands for MPX insns.
 637
 638 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 641         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 642         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 643         (ptwrite): Split into non-64-bit and 64-bit forms.
 644         * i386-tbl.h: Re-generate.
 645
 646 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 649         template.
 650         * i386-tbl.h: Re-generate.
 651
 652 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 655         (prefix_table): Move vmmcall here. Add vmgexit.
 656         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 657         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 658         (cpu_flags): Add CpuSEV_ES entry.
 659         * i386-opc.h (CpuSEV_ES): New.
 660         (union i386_cpu_flags): Add cpusev_es field.
 661         * i386-opc.tbl (vmgexit): New.
 662         * i386-init.h, i386-tbl.h: Re-generate.
 663
 664 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 667         with MnemonicSize.
 668         * i386-opc.h (IGNORESIZE): New.
 669         (DEFAULTSIZE): Likewise.
 670         (IgnoreSize): Removed.
 671         (DefaultSize): Likewise.
 672         (MnemonicSize): New.
 673         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 674         mnemonicsize.
 675         * i386-opc.tbl (IgnoreSize): New.
 676         (DefaultSize): Likewise.
 677         * i386-tbl.h: Regenerated.
 678
 679 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 680
 681         PR 25627
 682         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 683         instructions.
 684
 685 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 686
 687         PR gas/25622
 688         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 689         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 690         * i386-tbl.h: Regenerated.
 691
 692 2020-02-26  Alan Modra  <amodra@gmail.com>
 693
 694         * aarch64-asm.c: Indent labels correctly.
 695         * aarch64-dis.c: Likewise.
 696         * aarch64-gen.c: Likewise.
 697         * aarch64-opc.c: Likewise.
 698         * alpha-dis.c: Likewise.
 699         * i386-dis.c: Likewise.
 700         * nds32-asm.c: Likewise.
 701         * nfp-dis.c: Likewise.
 702         * visium-dis.c: Likewise.
 703
 704 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 705
 706         * arc-regs.h (int_vector_base): Make it available for all ARC
 707         CPUs.
 708
 709 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 710
 711         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 712         changed.
 713
 714 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 715
 716         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 717         c.mv/c.li if rs1 is zero.
 718
 719 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 720
 721         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 722         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 723         CPU_POPCNT_FLAGS.
 724         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 725         * i386-opc.h (CpuABM): Removed.
 726         (CpuPOPCNT): New.
 727         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 728         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 729         popcnt.  Remove CpuABM from lzcnt.
 730         * i386-init.h: Regenerated.
 731         * i386-tbl.h: Likewise.
 732
 733 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 734
 735         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 736         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 737         VexW1 instead of open-coding them.
 738         * i386-tbl.h: Re-generate.
 739
 740 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 741
 742         * i386-opc.tbl (AddrPrefixOpReg): Define.
 743         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 744         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 745         templates. Drop NoRex64.
 746         * i386-tbl.h: Re-generate.
 747
 748 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 749
 750         PR gas/6518
 751         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 752         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 753         into Intel syntax instance (with Unpsecified) and AT&T one
 754         (without).
 755         (vcvtneps2bf16): Likewise, along with folding the two so far
 756         separate ones.
 757         * i386-tbl.h: Re-generate.
 758
 759 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 760
 761         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 762         CPU_ANY_SSE4A_FLAGS.
 763
 764 2020-02-17  Alan Modra  <amodra@gmail.com>
 765
 766         * i386-gen.c (cpu_flag_init): Correct last change.
 767
 768 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 771         CPU_ANY_SSE4_FLAGS.
 772
 773 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 774
 775         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 776         (movzx): Likewise.
 777
 778 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 779
 780         PR gas/25438
 781         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 782         destination for Cpu64-only variant.
 783         (movzx): Fold patterns.
 784         * i386-tbl.h: Re-generate.
 785
 786 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 789         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 790         CPU_ANY_SSE4_FLAGS entry.
 791         * i386-init.h: Re-generate.
 792
 793 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 796         with Unspecified, making the present one AT&T syntax only.
 797         * i386-tbl.h: Re-generate.
 798
 799 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 802         * i386-tbl.h: Re-generate.
 803
 804 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 805
 806         PR gas/24546
 807         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 808         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 809         Amd64 and Intel64 templates.
 810         (call, jmp): Likewise for far indirect variants. Dro
 811         Unspecified.
 812         * i386-tbl.h: Re-generate.
 813
 814 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 817         * i386-opc.h (ShortForm): Delete.
 818         (struct i386_opcode_modifier): Remove shortform field.
 819         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 820         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 821         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 822         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 823         Drop ShortForm.
 824         * i386-tbl.h: Re-generate.
 825
 826 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 829         fucompi): Drop ShortForm from operand-less templates.
 830         * i386-tbl.h: Re-generate.
 831
 832 2020-02-11  Alan Modra  <amodra@gmail.com>
 833
 834         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 835         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 836         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 837         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 838         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 839
 840 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 841
 842         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 843         (cde_opcodes): Add VCX* instructions.
 844
 845 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 846             Matthew Malcomson  <matthew.malcomson@arm.com>
 847
 848         * arm-dis.c (struct cdeopcode32): New.
 849         (CDE_OPCODE): New macro.
 850         (cde_opcodes): New disassembly table.
 851         (regnames): New option to table.
 852         (cde_coprocs): New global variable.
 853         (print_insn_cde): New
 854         (print_insn_thumb32): Use print_insn_cde.
 855         (parse_arm_disassembler_options): Parse coprocN args.
 856
 857 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 858
 859         PR gas/25516
 860         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 861         with ISA64.
 862         * i386-opc.h (AMD64): Removed.
 863         (Intel64): Likewose.
 864         (AMD64): New.
 865         (INTEL64): Likewise.
 866         (INTEL64ONLY): Likewise.
 867         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 868         * i386-opc.tbl (Amd64): New.
 869         (Intel64): Likewise.
 870         (Intel64Only): Likewise.
 871         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 872         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 873         * i386-tbl.h: Regenerated.
 874
 875 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 876
 877         PR 25469
 878         * z80-dis.c: Add support for GBZ80 opcodes.
 879
 880 2020-02-04  Alan Modra  <amodra@gmail.com>
 881
 882         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 883
 884 2020-02-03  Alan Modra  <amodra@gmail.com>
 885
 886         * m32c-ibld.c: Regenerate.
 887
 888 2020-02-01  Alan Modra  <amodra@gmail.com>
 889
 890         * frv-ibld.c: Regenerate.
 891
 892 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 893
 894         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 895         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 896         (OP_E_memory): Replace xmm_mdq_mode case label by
 897         vex_scalar_w_dq_mode one.
 898         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 899
 900 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 901
 902         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 903         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 904         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 905         (intel_operand_size): Drop vex_w_dq_mode case label.
 906
 907 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 908
 909         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 910         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 911
 912 2020-01-30  Alan Modra  <amodra@gmail.com>
 913
 914         * m32c-ibld.c: Regenerate.
 915
 916 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 917
 918         * bpf-opc.c: Regenerate.
 919
 920 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 921
 922         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 923         (dis386): Use them to replace C2/C3 table entries.
 924         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 925         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 926         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 927         * i386-tbl.h: Re-generate.
 928
 929 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 930
 931         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 932         forms.
 933         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 934         DefaultSize.
 935         * i386-tbl.h: Re-generate.
 936
 937 2020-01-30  Alan Modra  <amodra@gmail.com>
 938
 939         * tic4x-dis.c (tic4x_dp): Make unsigned.
 940
 941 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 942             Jan Beulich  <jbeulich@suse.com>
 943
 944         PR binutils/25445
 945         * i386-dis.c (MOVSXD_Fixup): New function.
 946         (movsxd_mode): New enum.
 947         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 948         (intel_operand_size): Handle movsxd_mode.
 949         (OP_E_register): Likewise.
 950         (OP_G): Likewise.
 951         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 952         register on movsxd.  Add movsxd with 16-bit destination register
 953         for AMD64 and Intel64 ISAs.
 954         * i386-tbl.h: Regenerated.
 955
 956 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 957
 958         PR 25403
 959         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 960         * aarch64-asm-2.c: Regenerate
 961         * aarch64-dis-2.c: Likewise.
 962         * aarch64-opc-2.c: Likewise.
 963
 964 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 965
 966         * i386-opc.tbl (sysret): Drop DefaultSize.
 967         * i386-tbl.h: Re-generate.
 968
 969 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 972         Dword.
 973         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 974         * i386-tbl.h: Re-generate.
 975
 976 2020-01-20  Nick Clifton  <nickc@redhat.com>
 977
 978         * po/de.po: Updated German translation.
 979         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 980         * po/uk.po: Updated Ukranian translation.
 981
 982 2020-01-20  Alan Modra  <amodra@gmail.com>
 983
 984         * hppa-dis.c (fput_const): Remove useless cast.
 985
 986 2020-01-20  Alan Modra  <amodra@gmail.com>
 987
 988         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 989
 990 2020-01-18  Nick Clifton  <nickc@redhat.com>
 991
 992         * configure: Regenerate.
 993         * po/opcodes.pot: Regenerate.
 994
 995 2020-01-18  Nick Clifton  <nickc@redhat.com>
 996
 997         Binutils 2.34 branch created.
 998
 999 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1000
1001         * opintl.h: Fix spelling error (seperate).
1002
1003 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1004
1005         * i386-opc.tbl: Add {vex} pseudo prefix.
1006         * i386-tbl.h: Regenerated.
1007
1008 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1009
1010         PR 25376
1011         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1012         (neon_opcodes): Likewise.
1013         (select_arm_features): Make sure we enable MVE bits when selecting
1014         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1015         any architecture.
1016
1017 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-opc.tbl: Drop stale comment from XOP section.
1020
1021 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1024         (extractps): Add VexWIG to SSE2AVX forms.
1025         * i386-tbl.h: Re-generate.
1026
1027 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1030         Size64 from and use VexW1 on SSE2AVX forms.
1031         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1032         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1033         * i386-tbl.h: Re-generate.
1034
1035 2020-01-15  Alan Modra  <amodra@gmail.com>
1036
1037         * tic4x-dis.c (tic4x_version): Make unsigned long.
1038         (optab, optab_special, registernames): New file scope vars.
1039         (tic4x_print_register): Set up registernames rather than
1040         malloc'd registertable.
1041         (tic4x_disassemble): Delete optable and optable_special.  Use
1042         optab and optab_special instead.  Throw away old optab,
1043         optab_special and registernames when info->mach changes.
1044
1045 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1046
1047         PR 25377
1048         * z80-dis.c (suffix): Use .db instruction to generate double
1049         prefix.
1050
1051 2020-01-14  Alan Modra  <amodra@gmail.com>
1052
1053         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1054         values to unsigned before shifting.
1055
1056 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1057
1058         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1059         flow instructions.
1060         (print_insn_thumb16, print_insn_thumb32): Likewise.
1061         (print_insn): Initialize the insn info.
1062         * i386-dis.c (print_insn): Initialize the insn info fields, and
1063         detect jumps.
1064
1065 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1066
1067         * arc-opc.c (C_NE): Make it required.
1068
1069 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1070
1071         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1072         reserved register name.
1073
1074 2020-01-13  Alan Modra  <amodra@gmail.com>
1075
1076         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1077         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1078
1079 2020-01-13  Alan Modra  <amodra@gmail.com>
1080
1081         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1082         result of wasm_read_leb128 in a uint64_t and check that bits
1083         are not lost when copying to other locals.  Use uint32_t for
1084         most locals.  Use PRId64 when printing int64_t.
1085
1086 2020-01-13  Alan Modra  <amodra@gmail.com>
1087
1088         * score-dis.c: Formatting.
1089         * score7-dis.c: Formatting.
1090
1091 2020-01-13  Alan Modra  <amodra@gmail.com>
1092
1093         * score-dis.c (print_insn_score48): Use unsigned variables for
1094         unsigned values.  Don't left shift negative values.
1095         (print_insn_score32): Likewise.
1096         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1097
1098 2020-01-13  Alan Modra  <amodra@gmail.com>
1099
1100         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1101
1102 2020-01-13  Alan Modra  <amodra@gmail.com>
1103
1104         * fr30-ibld.c: Regenerate.
1105
1106 2020-01-13  Alan Modra  <amodra@gmail.com>
1107
1108         * xgate-dis.c (print_insn): Don't left shift signed value.
1109         (ripBits): Formatting, use 1u.
1110
1111 2020-01-10  Alan Modra  <amodra@gmail.com>
1112
1113         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1114         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1115
1116 2020-01-10  Alan Modra  <amodra@gmail.com>
1117
1118         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1119         and XRREG value earlier to avoid a shift with negative exponent.
1120         * m10200-dis.c (disassemble): Similarly.
1121
1122 2020-01-09  Nick Clifton  <nickc@redhat.com>
1123
1124         PR 25224
1125         * z80-dis.c (ld_ii_ii): Use correct cast.
1126
1127 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1128
1129         PR 25224
1130         * z80-dis.c (ld_ii_ii): Use character constant when checking
1131         opcode byte value.
1132
1133 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1134
1135         * i386-dis.c (SEP_Fixup): New.
1136         (SEP): Define.
1137         (dis386_twobyte): Use it for sysenter/sysexit.
1138         (enum x86_64_isa): Change amd64 enumerator to value 1.
1139         (OP_J): Compare isa64 against intel64 instead of amd64.
1140         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1141         forms.
1142         * i386-tbl.h: Re-generate.
1143
1144 2020-01-08  Alan Modra  <amodra@gmail.com>
1145
1146         * z8k-dis.c: Include libiberty.h
1147         (instr_data_s): Make max_fetched unsigned.
1148         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1149         Don't exceed byte_info bounds.
1150         (output_instr): Make num_bytes unsigned.
1151         (unpack_instr): Likewise for nibl_count and loop.
1152         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1153         idx unsigned.
1154         * z8k-opc.h: Regenerate.
1155
1156 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1157
1158         * arc-tbl.h (llock): Use 'LLOCK' as class.
1159         (llockd): Likewise.
1160         (scond): Use 'SCOND' as class.
1161         (scondd): Likewise.
1162         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1163         (scondd): Likewise.
1164
1165 2020-01-06  Alan Modra  <amodra@gmail.com>
1166
1167         * m32c-ibld.c: Regenerate.
1168
1169 2020-01-06  Alan Modra  <amodra@gmail.com>
1170
1171         PR 25344
1172         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1173         Peek at next byte to prevent recursion on repeated prefix bytes.
1174         Ensure uninitialised "mybuf" is not accessed.
1175         (print_insn_z80): Don't zero n_fetch and n_used here,..
1176         (print_insn_z80_buf): ..do it here instead.
1177
1178 2020-01-04  Alan Modra  <amodra@gmail.com>
1179
1180         * m32r-ibld.c: Regenerate.
1181
1182 2020-01-04  Alan Modra  <amodra@gmail.com>
1183
1184         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1185
1186 2020-01-04  Alan Modra  <amodra@gmail.com>
1187
1188         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1189
1190 2020-01-04  Alan Modra  <amodra@gmail.com>
1191
1192         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1193
1194 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1195
1196         * aarch64-tbl.h (aarch64_opcode_table): Use
1197         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1198
1199 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1200
1201         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1202         forms of SUDOT and USDOT.
1203
1204 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1205
1206         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1207         uzip{1,2}.
1208         * opcodes/aarch64-dis-2.c: Re-generate.
1209
1210 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1211
1212         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1213         FMMLA encoding.
1214         * opcodes/aarch64-dis-2.c: Re-generate.
1215
1216 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1217
1218         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1219
1220 2020-01-01  Alan Modra  <amodra@gmail.com>
1221
1222         Update year range in copyright notice of all files.
1223
1224 For older changes see ChangeLog-2019
1225 \f
1226 Copyright (C) 2020 Free Software Foundation, Inc.
1227
1228 Copying and distribution of this file, with or without modification,
1229 are permitted in any medium without royalty provided the copyright
1230 notice and this notice are preserved.
1231
1232 Local Variables:
1233 mode: change-log
1234 left-margin: 8
1235 fill-column: 74
1236 version-control: never
1237 End: