opcodes/ChangeLog

   1 2018-11-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
   4         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
   5         Vex=1 on AVX / AVX2 flavors.
   6         (vpmaxub): Re-order attributes on AVX512BW flavor.
   7         * i386-tbl.h: Re-generate.
   8
   9 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-opc.tbl (VexW0, VexW1): New.
  12         (vphadd*, vphsub*): Use VexW0 on XOP variants.
  13         * i386-tbl.h: Re-generate.
  14
  15 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
  16
  17         * s12z-dis.c (decode_possible_symbol): Add fallback case.
  18         (rel_15_7): Likewise.
  19
  20 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
  21
  22         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
  23         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
  24         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
  25
  26 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
  27
  28         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
  29         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
  30
  31 2018-10-10  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
  34         Size64. Add Size.
  35         * i386-opc.h (Size16, Size32, Size64): Delete.
  36         (Size): New.
  37         (SIZE16, SIZE32, SIZE64): Define.
  38         (struct i386_opcode_modifier): Drop size16, size32, and size64.
  39         Add size.
  40         * i386-opc.tbl (Size16, Size32, Size64): Define.
  41         * i386-tbl.h: Re-generate.
  42
  43 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  44
  45         * aarch64-opc.c (operand_general_constraint_met_p): Add
  46         SSBS in the check for one-bit immediate.
  47         (aarch64_sys_regs): New entry for SSBS.
  48         (aarch64_sys_reg_supported_p): New check for above.
  49         (aarch64_pstatefields): New entry for SSBS.
  50         (aarch64_pstatefield_supported_p): New check for above.
  51
  52 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  53
  54         * aarch64-opc.c (aarch64_sys_regs): New entries for
  55         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
  56         (aarch64_sys_reg_supported_p): New checks for above.
  57
  58 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  59
  60         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
  61         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
  62         with the hint immediate.
  63         * aarch64-opc.c (aarch64_hint_options): New entries for
  64         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
  65         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
  66         while checking for HINT_OPD_F_NOPRINT flag.
  67         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
  68         extract value.
  69         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
  70         (aarch64_opcode_table): Add entry for BTI.
  71         (AARCH64_OPERANDS): Add new description for BTI targets.
  72         * aarch64-asm-2.c: Regenerate.
  73         * aarch64-dis-2.c: Regenerate.
  74         * aarch64-opc-2.c: Regenerate.
  75
  76 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  77
  78         * aarch64-opc.c (aarch64_sys_regs): New entries for
  79         rndr and rndrrs.
  80         (aarch64_sys_reg_supported_p): New check for above.
  81
  82 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  83
  84         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
  85         (aarch64_sys_ins_reg_supported_p): New check for above.
  86
  87 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  88
  89         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
  90         AARCH64_OPND_SYSREG_SR.
  91         * aarch64-opc.c (aarch64_print_operand): Likewise.
  92         (aarch64_sys_regs_sr): Define table.
  93         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
  94         AARCH64_FEATURE_PREDRES.
  95         * aarch64-tbl.h (aarch64_feature_predres): New.
  96         (PREDRES, PREDRES_INSN): New.
  97         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
  98         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
  99         * aarch64-asm-2.c: Regenerate.
 100         * aarch64-dis-2.c: Regenerate.
 101         * aarch64-opc-2.c: Regenerate.
 102
 103 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 104
 105         * aarch64-tbl.h (aarch64_feature_sb): New.
 106         (SB, SB_INSN): New.
 107         (aarch64_opcode_table): Add entry for sb.
 108         * aarch64-asm-2.c: Regenerate.
 109         * aarch64-dis-2.c: Regenerate.
 110         * aarch64-opc-2.c: Regenerate.
 111
 112 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 113
 114         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 115         (aarch64_feature_frintts): New.
 116         (FLAGMANIP, FRINTTS): New.
 117         (aarch64_opcode_table): Add entries for xaflag, axflag
 118         and frint[32,64][x,z] instructions.
 119         * aarch64-asm-2.c: Regenerate.
 120         * aarch64-dis-2.c: Regenerate.
 121         * aarch64-opc-2.c: Regenerate.
 122
 123 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 124
 125         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 126         (ARMV8_5, V8_5_INSN): New.
 127
 128 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 129
 130         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 131
 132 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 133
 134         * i386-dis.c (rm_table): Add enclv.
 135         * i386-opc.tbl: Add enclv.
 136         * i386-tbl.h: Regenerated.
 137
 138 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 139
 140         * arm-dis.c (arm_opcodes): Add sb.
 141         (thumb32_opcodes): Likewise.
 142
 143 2018-10-05  Richard Henderson  <rth@twiddle.net>
 144             Stafford Horne  <shorne@gmail.com>
 145
 146         * or1k-desc.c: Regenerate.
 147         * or1k-desc.h: Regenerate.
 148         * or1k-opc.c: Regenerate.
 149         * or1k-opc.h: Regenerate.
 150         * or1k-opinst.c: Regenerate.
 151
 152 2018-10-05  Richard Henderson  <rth@twiddle.net>
 153
 154         * or1k-asm.c: Regenerated.
 155         * or1k-desc.c: Regenerated.
 156         * or1k-desc.h: Regenerated.
 157         * or1k-dis.c: Regenerated.
 158         * or1k-ibld.c: Regenerated.
 159         * or1k-opc.c: Regenerated.
 160         * or1k-opc.h: Regenerated.
 161         * or1k-opinst.c: Regenerated.
 162
 163 2018-10-05  Richard Henderson  <rth@twiddle.net>
 164
 165         * or1k-asm.c: Regenerate.
 166
 167 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 168
 169         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 170         * aarch64-dis.c (print_operands): Refactor to take notes.
 171         (print_verifier_notes): New.
 172         (print_aarch64_insn): Apply constraint verifier.
 173         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 174         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 175
 176 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 177
 178         * aarch64-opc.c (init_insn_block): New.
 179         (verify_constraints, aarch64_is_destructive_by_operands): New.
 180         * aarch64-opc.h (verify_constraints): New.
 181
 182 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 183
 184         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 185         * aarch64-opc.c (verify_ldpsw): Update arguments.
 186
 187 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 188
 189         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 190         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 191
 192 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 193
 194         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 195         * aarch64-dis.c (insn_sequence): New.
 196
 197 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 198
 199         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 200         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 201         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 202         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 203         constraints.
 204         (_SVE_INSNC): New.
 205         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 206         constraints.
 207         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 208         F_SCAN flags.
 209         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 210         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 211         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 212         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 213         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 214         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 215         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 216
 217 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 218
 219         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 220
 221 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 222
 223         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 224         are used when extracting signed fields and converting them to
 225         potentially 64-bit types.
 226
 227 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 228
 229         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 230         * Makefile.in: Re-generate.
 231         * aclocal.m4: Re-generate.
 232         * configure: Re-generate.
 233         * configure.ac: Remove check for -Wno-missing-field-initializers.
 234         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 235         (csky_v2_opcodes): Likewise.
 236
 237 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 238
 239         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 240
 241 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 242
 243         * nds32-asm.c (operand_fields): Remove the unused fields.
 244         (nds32_opcodes): Remove the unused instructions.
 245         * nds32-dis.c (nds32_ex9_info): Removed.
 246         (nds32_parse_opcode): Updated.
 247         (print_insn_nds32): Likewise.
 248         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 249         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 250         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 251         build_opcode_hash_table): New functions.
 252         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 253         nds32_opcode_table): New.
 254         (hw_ktabs): Declare it to a pointer rather than an array.
 255         (build_hash_table): Removed.
 256         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 257         SYN_ROPT and upadte HW_GPR and HW_INT.
 258         * nds32-dis.c (keywords): Remove const.
 259         (match_field): New function.
 260         (nds32_parse_opcode): Updated.
 261         * disassemble.c (disassemble_init_for_target):
 262         Add disassemble_init_nds32.
 263         * nds32-dis.c (eum map_type): New.
 264         (nds32_private_data): Likewise.
 265         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 266         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 267         (print_insn_nds32): Updated.
 268         * nds32-asm.c (parse_aext_reg): Add new parameter.
 269         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 270         are allowed to use.
 271         All callers changed.
 272         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 273         (operand_fields): Add new fields.
 274         (nds32_opcodes): Add new instructions.
 275         (keyword_aridxi_mx): New keyword.
 276         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 277         and NASM_ATTR_ZOL.
 278         (ALU2_1, ALU2_2, ALU2_3): New macros.
 279         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 280
 281 2018-09-17  Kito Cheng  <kito@andestech.com>
 282
 283         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 284
 285 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 286
 287         PR gas/23670
 288         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 289         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 290         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 291         (EVEX_LEN_0F7E_P_1): Likewise.
 292         (EVEX_LEN_0F7E_P_2): Likewise.
 293         (EVEX_LEN_0FD6_P_2): Likewise.
 294         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 295         (EVEX_LEN_TABLE): Likewise.
 296         (EVEX_LEN_0F6E_P_2): New enum.
 297         (EVEX_LEN_0F7E_P_1): Likewise.
 298         (EVEX_LEN_0F7E_P_2): Likewise.
 299         (EVEX_LEN_0FD6_P_2): Likewise.
 300         (evex_len_table): New.
 301         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 302         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 303         * i386-tbl.h: Regenerated.
 304
 305 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         PR gas/23665
 308         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 309         VEX_LEN_0F7E_P_2 entries.
 310         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 311         * i386-tbl.h: Regenerated.
 312
 313 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         * i386-dis.c (VZERO_Fixup): Removed.
 316         (VZERO): Likewise.
 317         (VEX_LEN_0F10_P_1): Likewise.
 318         (VEX_LEN_0F10_P_3): Likewise.
 319         (VEX_LEN_0F11_P_1): Likewise.
 320         (VEX_LEN_0F11_P_3): Likewise.
 321         (VEX_LEN_0F2E_P_0): Likewise.
 322         (VEX_LEN_0F2E_P_2): Likewise.
 323         (VEX_LEN_0F2F_P_0): Likewise.
 324         (VEX_LEN_0F2F_P_2): Likewise.
 325         (VEX_LEN_0F51_P_1): Likewise.
 326         (VEX_LEN_0F51_P_3): Likewise.
 327         (VEX_LEN_0F52_P_1): Likewise.
 328         (VEX_LEN_0F53_P_1): Likewise.
 329         (VEX_LEN_0F58_P_1): Likewise.
 330         (VEX_LEN_0F58_P_3): Likewise.
 331         (VEX_LEN_0F59_P_1): Likewise.
 332         (VEX_LEN_0F59_P_3): Likewise.
 333         (VEX_LEN_0F5A_P_1): Likewise.
 334         (VEX_LEN_0F5A_P_3): Likewise.
 335         (VEX_LEN_0F5C_P_1): Likewise.
 336         (VEX_LEN_0F5C_P_3): Likewise.
 337         (VEX_LEN_0F5D_P_1): Likewise.
 338         (VEX_LEN_0F5D_P_3): Likewise.
 339         (VEX_LEN_0F5E_P_1): Likewise.
 340         (VEX_LEN_0F5E_P_3): Likewise.
 341         (VEX_LEN_0F5F_P_1): Likewise.
 342         (VEX_LEN_0F5F_P_3): Likewise.
 343         (VEX_LEN_0FC2_P_1): Likewise.
 344         (VEX_LEN_0FC2_P_3): Likewise.
 345         (VEX_LEN_0F3A0A_P_2): Likewise.
 346         (VEX_LEN_0F3A0B_P_2): Likewise.
 347         (VEX_W_0F10_P_0): Likewise.
 348         (VEX_W_0F10_P_1): Likewise.
 349         (VEX_W_0F10_P_2): Likewise.
 350         (VEX_W_0F10_P_3): Likewise.
 351         (VEX_W_0F11_P_0): Likewise.
 352         (VEX_W_0F11_P_1): Likewise.
 353         (VEX_W_0F11_P_2): Likewise.
 354         (VEX_W_0F11_P_3): Likewise.
 355         (VEX_W_0F12_P_0_M_0): Likewise.
 356         (VEX_W_0F12_P_0_M_1): Likewise.
 357         (VEX_W_0F12_P_1): Likewise.
 358         (VEX_W_0F12_P_2): Likewise.
 359         (VEX_W_0F12_P_3): Likewise.
 360         (VEX_W_0F13_M_0): Likewise.
 361         (VEX_W_0F14): Likewise.
 362         (VEX_W_0F15): Likewise.
 363         (VEX_W_0F16_P_0_M_0): Likewise.
 364         (VEX_W_0F16_P_0_M_1): Likewise.
 365         (VEX_W_0F16_P_1): Likewise.
 366         (VEX_W_0F16_P_2): Likewise.
 367         (VEX_W_0F17_M_0): Likewise.
 368         (VEX_W_0F28): Likewise.
 369         (VEX_W_0F29): Likewise.
 370         (VEX_W_0F2B_M_0): Likewise.
 371         (VEX_W_0F2E_P_0): Likewise.
 372         (VEX_W_0F2E_P_2): Likewise.
 373         (VEX_W_0F2F_P_0): Likewise.
 374         (VEX_W_0F2F_P_2): Likewise.
 375         (VEX_W_0F50_M_0): Likewise.
 376         (VEX_W_0F51_P_0): Likewise.
 377         (VEX_W_0F51_P_1): Likewise.
 378         (VEX_W_0F51_P_2): Likewise.
 379         (VEX_W_0F51_P_3): Likewise.
 380         (VEX_W_0F52_P_0): Likewise.
 381         (VEX_W_0F52_P_1): Likewise.
 382         (VEX_W_0F53_P_0): Likewise.
 383         (VEX_W_0F53_P_1): Likewise.
 384         (VEX_W_0F58_P_0): Likewise.
 385         (VEX_W_0F58_P_1): Likewise.
 386         (VEX_W_0F58_P_2): Likewise.
 387         (VEX_W_0F58_P_3): Likewise.
 388         (VEX_W_0F59_P_0): Likewise.
 389         (VEX_W_0F59_P_1): Likewise.
 390         (VEX_W_0F59_P_2): Likewise.
 391         (VEX_W_0F59_P_3): Likewise.
 392         (VEX_W_0F5A_P_0): Likewise.
 393         (VEX_W_0F5A_P_1): Likewise.
 394         (VEX_W_0F5A_P_3): Likewise.
 395         (VEX_W_0F5B_P_0): Likewise.
 396         (VEX_W_0F5B_P_1): Likewise.
 397         (VEX_W_0F5B_P_2): Likewise.
 398         (VEX_W_0F5C_P_0): Likewise.
 399         (VEX_W_0F5C_P_1): Likewise.
 400         (VEX_W_0F5C_P_2): Likewise.
 401         (VEX_W_0F5C_P_3): Likewise.
 402         (VEX_W_0F5D_P_0): Likewise.
 403         (VEX_W_0F5D_P_1): Likewise.
 404         (VEX_W_0F5D_P_2): Likewise.
 405         (VEX_W_0F5D_P_3): Likewise.
 406         (VEX_W_0F5E_P_0): Likewise.
 407         (VEX_W_0F5E_P_1): Likewise.
 408         (VEX_W_0F5E_P_2): Likewise.
 409         (VEX_W_0F5E_P_3): Likewise.
 410         (VEX_W_0F5F_P_0): Likewise.
 411         (VEX_W_0F5F_P_1): Likewise.
 412         (VEX_W_0F5F_P_2): Likewise.
 413         (VEX_W_0F5F_P_3): Likewise.
 414         (VEX_W_0F60_P_2): Likewise.
 415         (VEX_W_0F61_P_2): Likewise.
 416         (VEX_W_0F62_P_2): Likewise.
 417         (VEX_W_0F63_P_2): Likewise.
 418         (VEX_W_0F64_P_2): Likewise.
 419         (VEX_W_0F65_P_2): Likewise.
 420         (VEX_W_0F66_P_2): Likewise.
 421         (VEX_W_0F67_P_2): Likewise.
 422         (VEX_W_0F68_P_2): Likewise.
 423         (VEX_W_0F69_P_2): Likewise.
 424         (VEX_W_0F6A_P_2): Likewise.
 425         (VEX_W_0F6B_P_2): Likewise.
 426         (VEX_W_0F6C_P_2): Likewise.
 427         (VEX_W_0F6D_P_2): Likewise.
 428         (VEX_W_0F6F_P_1): Likewise.
 429         (VEX_W_0F6F_P_2): Likewise.
 430         (VEX_W_0F70_P_1): Likewise.
 431         (VEX_W_0F70_P_2): Likewise.
 432         (VEX_W_0F70_P_3): Likewise.
 433         (VEX_W_0F71_R_2_P_2): Likewise.
 434         (VEX_W_0F71_R_4_P_2): Likewise.
 435         (VEX_W_0F71_R_6_P_2): Likewise.
 436         (VEX_W_0F72_R_2_P_2): Likewise.
 437         (VEX_W_0F72_R_4_P_2): Likewise.
 438         (VEX_W_0F72_R_6_P_2): Likewise.
 439         (VEX_W_0F73_R_2_P_2): Likewise.
 440         (VEX_W_0F73_R_3_P_2): Likewise.
 441         (VEX_W_0F73_R_6_P_2): Likewise.
 442         (VEX_W_0F73_R_7_P_2): Likewise.
 443         (VEX_W_0F74_P_2): Likewise.
 444         (VEX_W_0F75_P_2): Likewise.
 445         (VEX_W_0F76_P_2): Likewise.
 446         (VEX_W_0F77_P_0): Likewise.
 447         (VEX_W_0F7C_P_2): Likewise.
 448         (VEX_W_0F7C_P_3): Likewise.
 449         (VEX_W_0F7D_P_2): Likewise.
 450         (VEX_W_0F7D_P_3): Likewise.
 451         (VEX_W_0F7E_P_1): Likewise.
 452         (VEX_W_0F7F_P_1): Likewise.
 453         (VEX_W_0F7F_P_2): Likewise.
 454         (VEX_W_0FAE_R_2_M_0): Likewise.
 455         (VEX_W_0FAE_R_3_M_0): Likewise.
 456         (VEX_W_0FC2_P_0): Likewise.
 457         (VEX_W_0FC2_P_1): Likewise.
 458         (VEX_W_0FC2_P_2): Likewise.
 459         (VEX_W_0FC2_P_3): Likewise.
 460         (VEX_W_0FD0_P_2): Likewise.
 461         (VEX_W_0FD0_P_3): Likewise.
 462         (VEX_W_0FD1_P_2): Likewise.
 463         (VEX_W_0FD2_P_2): Likewise.
 464         (VEX_W_0FD3_P_2): Likewise.
 465         (VEX_W_0FD4_P_2): Likewise.
 466         (VEX_W_0FD5_P_2): Likewise.
 467         (VEX_W_0FD6_P_2): Likewise.
 468         (VEX_W_0FD7_P_2_M_1): Likewise.
 469         (VEX_W_0FD8_P_2): Likewise.
 470         (VEX_W_0FD9_P_2): Likewise.
 471         (VEX_W_0FDA_P_2): Likewise.
 472         (VEX_W_0FDB_P_2): Likewise.
 473         (VEX_W_0FDC_P_2): Likewise.
 474         (VEX_W_0FDD_P_2): Likewise.
 475         (VEX_W_0FDE_P_2): Likewise.
 476         (VEX_W_0FDF_P_2): Likewise.
 477         (VEX_W_0FE0_P_2): Likewise.
 478         (VEX_W_0FE1_P_2): Likewise.
 479         (VEX_W_0FE2_P_2): Likewise.
 480         (VEX_W_0FE3_P_2): Likewise.
 481         (VEX_W_0FE4_P_2): Likewise.
 482         (VEX_W_0FE5_P_2): Likewise.
 483         (VEX_W_0FE6_P_1): Likewise.
 484         (VEX_W_0FE6_P_2): Likewise.
 485         (VEX_W_0FE6_P_3): Likewise.
 486         (VEX_W_0FE7_P_2_M_0): Likewise.
 487         (VEX_W_0FE8_P_2): Likewise.
 488         (VEX_W_0FE9_P_2): Likewise.
 489         (VEX_W_0FEA_P_2): Likewise.
 490         (VEX_W_0FEB_P_2): Likewise.
 491         (VEX_W_0FEC_P_2): Likewise.
 492         (VEX_W_0FED_P_2): Likewise.
 493         (VEX_W_0FEE_P_2): Likewise.
 494         (VEX_W_0FEF_P_2): Likewise.
 495         (VEX_W_0FF0_P_3_M_0): Likewise.
 496         (VEX_W_0FF1_P_2): Likewise.
 497         (VEX_W_0FF2_P_2): Likewise.
 498         (VEX_W_0FF3_P_2): Likewise.
 499         (VEX_W_0FF4_P_2): Likewise.
 500         (VEX_W_0FF5_P_2): Likewise.
 501         (VEX_W_0FF6_P_2): Likewise.
 502         (VEX_W_0FF7_P_2): Likewise.
 503         (VEX_W_0FF8_P_2): Likewise.
 504         (VEX_W_0FF9_P_2): Likewise.
 505         (VEX_W_0FFA_P_2): Likewise.
 506         (VEX_W_0FFB_P_2): Likewise.
 507         (VEX_W_0FFC_P_2): Likewise.
 508         (VEX_W_0FFD_P_2): Likewise.
 509         (VEX_W_0FFE_P_2): Likewise.
 510         (VEX_W_0F3800_P_2): Likewise.
 511         (VEX_W_0F3801_P_2): Likewise.
 512         (VEX_W_0F3802_P_2): Likewise.
 513         (VEX_W_0F3803_P_2): Likewise.
 514         (VEX_W_0F3804_P_2): Likewise.
 515         (VEX_W_0F3805_P_2): Likewise.
 516         (VEX_W_0F3806_P_2): Likewise.
 517         (VEX_W_0F3807_P_2): Likewise.
 518         (VEX_W_0F3808_P_2): Likewise.
 519         (VEX_W_0F3809_P_2): Likewise.
 520         (VEX_W_0F380A_P_2): Likewise.
 521         (VEX_W_0F380B_P_2): Likewise.
 522         (VEX_W_0F3817_P_2): Likewise.
 523         (VEX_W_0F381C_P_2): Likewise.
 524         (VEX_W_0F381D_P_2): Likewise.
 525         (VEX_W_0F381E_P_2): Likewise.
 526         (VEX_W_0F3820_P_2): Likewise.
 527         (VEX_W_0F3821_P_2): Likewise.
 528         (VEX_W_0F3822_P_2): Likewise.
 529         (VEX_W_0F3823_P_2): Likewise.
 530         (VEX_W_0F3824_P_2): Likewise.
 531         (VEX_W_0F3825_P_2): Likewise.
 532         (VEX_W_0F3828_P_2): Likewise.
 533         (VEX_W_0F3829_P_2): Likewise.
 534         (VEX_W_0F382A_P_2_M_0): Likewise.
 535         (VEX_W_0F382B_P_2): Likewise.
 536         (VEX_W_0F3830_P_2): Likewise.
 537         (VEX_W_0F3831_P_2): Likewise.
 538         (VEX_W_0F3832_P_2): Likewise.
 539         (VEX_W_0F3833_P_2): Likewise.
 540         (VEX_W_0F3834_P_2): Likewise.
 541         (VEX_W_0F3835_P_2): Likewise.
 542         (VEX_W_0F3837_P_2): Likewise.
 543         (VEX_W_0F3838_P_2): Likewise.
 544         (VEX_W_0F3839_P_2): Likewise.
 545         (VEX_W_0F383A_P_2): Likewise.
 546         (VEX_W_0F383B_P_2): Likewise.
 547         (VEX_W_0F383C_P_2): Likewise.
 548         (VEX_W_0F383D_P_2): Likewise.
 549         (VEX_W_0F383E_P_2): Likewise.
 550         (VEX_W_0F383F_P_2): Likewise.
 551         (VEX_W_0F3840_P_2): Likewise.
 552         (VEX_W_0F3841_P_2): Likewise.
 553         (VEX_W_0F38DB_P_2): Likewise.
 554         (VEX_W_0F3A08_P_2): Likewise.
 555         (VEX_W_0F3A09_P_2): Likewise.
 556         (VEX_W_0F3A0A_P_2): Likewise.
 557         (VEX_W_0F3A0B_P_2): Likewise.
 558         (VEX_W_0F3A0C_P_2): Likewise.
 559         (VEX_W_0F3A0D_P_2): Likewise.
 560         (VEX_W_0F3A0E_P_2): Likewise.
 561         (VEX_W_0F3A0F_P_2): Likewise.
 562         (VEX_W_0F3A21_P_2): Likewise.
 563         (VEX_W_0F3A40_P_2): Likewise.
 564         (VEX_W_0F3A41_P_2): Likewise.
 565         (VEX_W_0F3A42_P_2): Likewise.
 566         (VEX_W_0F3A62_P_2): Likewise.
 567         (VEX_W_0F3A63_P_2): Likewise.
 568         (VEX_W_0F3ADF_P_2): Likewise.
 569         (VEX_LEN_0F77_P_0): New.
 570         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 571         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 572         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 573         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 574         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 575         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 576         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 577         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 578         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 579         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 580         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 581         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 582         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 583         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 584         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 585         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 586         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 587         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 588         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 589         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 590         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 591         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 592         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 593         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 594         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 595         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 596         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 597         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 598         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 599         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 600         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 601         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 602         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 603         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 604         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 605         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 606         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 607         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 608         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 609         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 610         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 611         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 612         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 613         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 614         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 615         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 616         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 617         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 618         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 619         (vex_table): Update VEX 0F28 and 0F29 entries.
 620         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 621         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 622         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 623         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 624         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 625         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 626         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 627         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 628         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 629         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 630         VEX_LEN_0F3A0B_P_2 entries.
 631         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 632         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 633         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 634         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 635         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 636         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 637         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 638         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 639         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 640         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 641         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 642         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 643         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 644         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 645         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 646         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 647         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 648         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 649         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 650         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 651         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 652         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 653         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 654         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 655         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 656         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 657         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 658         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 659         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 660         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 661         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 662         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 663         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 664         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 665         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 666         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 667         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 668         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 669         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 670         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 671         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 672         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 673         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 674         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 675         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 676         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 677         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 678         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 679         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 680         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 681         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 682         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 683         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 684         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 685         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 686         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 687         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 688         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 689         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 690         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 691         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 692         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 693         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 694         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 695         VEX_W_0F3ADF_P_2 entries.
 696         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 697         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 698         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 699
 700 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 701
 702         * i386-opc.tbl (VexWIG): New.
 703         Replace VexW=3 with VexWIG.
 704
 705 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 706
 707         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 708         * i386-tbl.h: Regenerated.
 709
 710 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 711
 712         PR gas/23665
 713         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 714         VEX_LEN_0FD6_P_2 entries.
 715         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 716         * i386-tbl.h: Regenerated.
 717
 718 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 719
 720         PR gas/23642
 721         * i386-opc.h (VEXWIG): New.
 722         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 723         * i386-tbl.h: Regenerated.
 724
 725 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 726
 727         PR binutils/23655
 728         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 729         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 730         * i386-dis.c (EXxEVexR64): New.
 731         (evex_rounding_64_mode): Likewise.
 732         (OP_Rounding): Handle evex_rounding_64_mode.
 733
 734 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 735
 736         PR binutils/23655
 737         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 738         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 739         * i386-dis.c (Edqa): New.
 740         (dqa_mode): Likewise.
 741         (intel_operand_size): Handle dqa_mode as m_mode.
 742         (OP_E_register): Handle dqa_mode as dq_mode.
 743         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 744
 745 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 746
 747         * i386-dis.c (OP_E_memory): Reformat.
 748
 749 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 750
 751         * i386-opc.tbl (crc32): Fold byte and word forms.
 752         * i386-tbl.h: Re-generate.
 753
 754 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 755
 756         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 757         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 758         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 759         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 760         * i386-tbl.h: Regenerated.
 761
 762 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 763
 764         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 765         meaningless.
 766         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 767         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 768         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 769         * i386-tbl.h: Re-generate.
 770
 771 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 772
 773         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 774         AVX512_4VNNIW insns.
 775         * i386-tbl.h: Re-generate.
 776
 777 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 778
 779         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 780         meaningless.
 781         * i386-tbl.h: Re-generate.
 782
 783 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 784
 785         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 786         meaningless.
 787         * i386-tbl.h: Re-generate.
 788
 789 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 790
 791         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 792         meaningless.
 793         * i386-tbl.h: Re-generate.
 794
 795 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 798         meaningless.
 799         * i386-tbl.h: Re-generate.
 800
 801 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 802
 803         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 804         meaningless.
 805         * i386-tbl.h: Re-generate.
 806
 807 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 810         * i386-tbl.h: Re-generate.
 811
 812 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 815         * i386-tbl.h: Re-generate.
 816
 817 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 818
 819         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 820         meaningless.
 821         * i386-tbl.h: Re-generate.
 822
 823 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 826         meaningless.
 827         * i386-tbl.h: Re-generate.
 828
 829 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 830
 831         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 832         * i386-tbl.h: Re-generate.
 833
 834 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 837         * i386-tbl.h: Re-generate.
 838
 839 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 840
 841         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 842         * i386-tbl.h: Re-generate.
 843
 844 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 845
 846         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 847         meaningless.
 848         * i386-tbl.h: Re-generate.
 849
 850 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 853         meaningless.
 854         * i386-tbl.h: Re-generate.
 855
 856 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 857
 858         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 859         meaningless.
 860         * i386-tbl.h: Re-generate.
 861
 862 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 863
 864         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 865         * i386-tbl.h: Re-generate.
 866
 867 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 870         * i386-tbl.h: Re-generate.
 871
 872 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 875         * i386-tbl.h: Re-generate.
 876
 877 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 880         (vpbroadcastw, rdpid): Drop NoRex64.
 881         * i386-tbl.h: Re-generate.
 882
 883 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 886         store templates, adding D.
 887         * i386-tbl.h: Re-generate.
 888
 889 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 892         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 893         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 894         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 895         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 896         Fold load and store templates where possible, adding D. Drop
 897         IgnoreSize where it was pointlessly present. Drop redundant
 898         *word.
 899         * i386-tbl.h: Re-generate.
 900
 901 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 902
 903         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 904         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 905         (intel_operand_size): Handle v_bndmk_mode.
 906         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 907
 908 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 909
 910         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 911
 912 2018-08-31  Kito Cheng  <kito@andestech.com>
 913
 914         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 915         compressed floating point instructions.
 916
 917 2018-08-30  Kito Cheng  <kito@andestech.com>
 918
 919         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 920         riscv_opcode.xlen_requirement.
 921         * riscv-opc.c (riscv_opcodes): Update for struct change.
 922
 923 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 924
 925         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 926         psr (PWRPSR) instruction.
 927
 928 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 929
 930         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 931
 932 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 933
 934         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 935
 936 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 937
 938         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 939         loongson3a as an alias of gs464 for compatibility.
 940         * mips-opc.c (mips_opcodes): Change Comments.
 941
 942 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 943
 944         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 945         option.
 946         (print_mips_disassembler_options): Document -M loongson-ext.
 947         * mips-opc.c (LEXT2): New macro.
 948         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 949
 950 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 951
 952          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 953          descriptors.
 954          (parse_mips_ase_option): Handle -M loongson-ext option.
 955          (print_mips_disassembler_options): Document -M loongson-ext.
 956          * mips-opc.c (IL3A): Delete.
 957          * mips-opc.c (LEXT): New macro.
 958          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 959          instructions.
 960
 961 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 962
 963         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 964         descriptors.
 965         (parse_mips_ase_option): Handle -M loongson-cam option.
 966         (print_mips_disassembler_options): Document -M loongson-cam.
 967         * mips-opc.c (LCAM): New macro.
 968         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 969         instructions.
 970
 971 2018-08-21  Alan Modra  <amodra@gmail.com>
 972
 973         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 974         (skip_optional_operands): Count optional operands, and update
 975         ppc_optional_operand_value call.
 976         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 977         (extract_vlensi): Likewise.
 978         (extract_fxm): Return default value for missing optional operand.
 979         (extract_ls, extract_raq, extract_tbr): Likewise.
 980         (insert_sxl, extract_sxl): New functions.
 981         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 982         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 983         flag and extra entry.
 984         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 985         extract_sxl.
 986
 987 2018-08-20  Alan Modra  <amodra@gmail.com>
 988
 989         * sh-opc.h (MASK): Simplify.
 990
 991 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 992
 993         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 994         BM_RESERVED0 or BM_RESERVED1
 995         (bm_rel_decode, bm_n_bytes): Ditto.
 996
 997 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 998
 999         * s12z.h: Delete.
1000
1001 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1002
1003         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1004         address with the addr32 prefix and without base nor index
1005         registers.
1006
1007 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1008
1009         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1010         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1011         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1012         (cpu_flags): Add CpuCMOV and CpuFXSR.
1013         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1014         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1015         * i386-init.h: Regenerated.
1016         * i386-tbl.h: Likewise.
1017
1018 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1019
1020         * arc-regs.h: Update auxiliary registers.
1021
1022 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1023
1024         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1025         (RegIP, RegIZ): Define.
1026         * i386-reg.tbl: Adjust comments.
1027         (rip): Use Qword instead of BaseIndex. Use RegIP.
1028         (eip): Use Dword instead of BaseIndex. Use RegIP.
1029         (riz): Add Qword. Use RegIZ.
1030         (eiz): Add Dword. Use RegIZ.
1031         * i386-tbl.h: Re-generate.
1032
1033 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1034
1035         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1036         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1037         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1038         * i386-tbl.h: Re-generate.
1039
1040 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1041
1042         * i386-gen.c (operand_types): Remove Mem field.
1043         * i386-opc.h (union i386_operand_type): Remove mem field.
1044         * i386-init.h, i386-tbl.h: Re-generate.
1045
1046 2018-08-01  Alan Modra  <amodra@gmail.com>
1047
1048         * po/POTFILES.in: Regenerate.
1049
1050 2018-07-31  Nick Clifton  <nickc@redhat.com>
1051
1052         * po/sv.po: Updated Swedish translation.
1053
1054 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1057         * i386-init.h, i386-tbl.h: Re-generate.
1058
1059 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1060
1061         * i386-opc.h (ZEROING_MASKING) Rename to ...
1062         (DYNAMIC_MASKING): ... this. Adjust comment.
1063         * i386-opc.tbl (MaskingMorZ): Define.
1064         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1065         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1066         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1067         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1068         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1069         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1070         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1071         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1072         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1073
1074 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1075
1076         * i386-opc.tbl: Use element rather than vector size for AVX512*
1077         scatter/gather insns.
1078         * i386-tbl.h: Re-generate.
1079
1080 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1083         (cpu_flags): Drop CpuVREX.
1084         * i386-opc.h (CpuVREX): Delete.
1085         (union i386_cpu_flags): Remove cpuvrex.
1086         * i386-init.h, i386-tbl.h: Re-generate.
1087
1088 2018-07-30  Jim Wilson  <jimw@sifive.com>
1089
1090         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1091         fields.
1092         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1093
1094 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1095
1096         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1097         * Makefile.in: Regenerated.
1098         * configure.ac: Add C-SKY.
1099         * configure: Regenerated.
1100         * csky-dis.c: New file.
1101         * csky-opc.h: New file.
1102         * disassemble.c (ARCH_csky): Define.
1103         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1104         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1105
1106 2018-07-27  Alan Modra  <amodra@gmail.com>
1107
1108         * ppc-opc.c (insert_sprbat): Correct function parameter and
1109         return type.
1110         (extract_sprbat): Likewise, variable too.
1111
1112 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1113             Alan Modra  <amodra@gmail.com>
1114
1115         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1116         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1117         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1118         support disjointed BAT.
1119         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1120         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1121         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1122
1123 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1124             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1125
1126         * i386-gen.c (adjust_broadcast_modifier): New function.
1127         (process_i386_opcode_modifier): Add an argument for operands.
1128         Adjust the Broadcast value based on operands.
1129         (output_i386_opcode): Pass operand_types to
1130         process_i386_opcode_modifier.
1131         (process_i386_opcodes): Pass NULL as operands to
1132         process_i386_opcode_modifier.
1133         * i386-opc.h (BYTE_BROADCAST): New.
1134         (WORD_BROADCAST): Likewise.
1135         (DWORD_BROADCAST): Likewise.
1136         (QWORD_BROADCAST): Likewise.
1137         (i386_opcode_modifier): Expand broadcast to 3 bits.
1138         * i386-tbl.h: Regenerated.
1139
1140 2018-07-24  Alan Modra  <amodra@gmail.com>
1141
1142         PR 23430
1143         * or1k-desc.h: Regenerate.
1144
1145 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1148         vcvtusi2ss, and vcvtusi2sd.
1149         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1150         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1151         * i386-tbl.h: Re-generate.
1152
1153 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1154
1155         * arc-opc.c (extract_w6): Fix extending the sign.
1156
1157 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1158
1159         * arc-tbl.h (vewt): Allow it for ARC EM family.
1160
1161 2018-07-23  Alan Modra  <amodra@gmail.com>
1162
1163         PR 23419
1164         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1165         opcode variants for mtspr/mfspr encodings.
1166
1167 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1168             Maciej W. Rozycki  <macro@mips.com>
1169
1170         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1171         loongson3a descriptors.
1172         (parse_mips_ase_option): Handle -M loongson-mmi option.
1173         (print_mips_disassembler_options): Document -M loongson-mmi.
1174         * mips-opc.c (LMMI): New macro.
1175         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1176         instructions.
1177
1178 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1179
1180         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1181         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1182         IgnoreSize and [XYZ]MMword where applicable.
1183         * i386-tbl.h: Re-generate.
1184
1185 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1186
1187         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1188         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1189         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1190         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1191         * i386-tbl.h: Re-generate.
1192
1193 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1194
1195         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1196         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1197         VPCLMULQDQ templates into their respective AVX512VL counterparts
1198         where possible, using Disp8ShiftVL and CheckRegSize instead of
1199         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1200         * i386-tbl.h: Re-generate.
1201
1202 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1203
1204         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1205         AVX512VL counterparts where possible, using Disp8ShiftVL and
1206         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1207         IgnoreSize) as appropriate.
1208         * i386-tbl.h: Re-generate.
1209
1210 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1211
1212         * i386-opc.tbl: Fold AVX512BW templates into their respective
1213         AVX512VL counterparts where possible, using Disp8ShiftVL and
1214         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1215         IgnoreSize) as appropriate.
1216         * i386-tbl.h: Re-generate.
1217
1218 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1219
1220         * i386-opc.tbl: Fold AVX512CD templates into their respective
1221         AVX512VL counterparts where possible, using Disp8ShiftVL and
1222         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1223         IgnoreSize) as appropriate.
1224         * i386-tbl.h: Re-generate.
1225
1226 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1227
1228         * i386-opc.h (DISP8_SHIFT_VL): New.
1229         * i386-opc.tbl (Disp8ShiftVL):  Define.
1230         (various): Fold AVX512VL templates into their respective
1231         AVX512F counterparts where possible, using Disp8ShiftVL and
1232         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1233         IgnoreSize) as appropriate.
1234         * i386-tbl.h: Re-generate.
1235
1236 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1237
1238         * Makefile.am: Change dependencies and rule for
1239         $(srcdir)/i386-init.h.
1240         * Makefile.in: Re-generate.
1241         * i386-gen.c (process_i386_opcodes): New local variable
1242         "marker". Drop opening of input file. Recognize marker and line
1243         number directives.
1244         * i386-opc.tbl (OPCODE_I386_H): Define.
1245         (i386-opc.h): Include it.
1246         (None): Undefine.
1247
1248 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1249
1250         PR gas/23418
1251         * i386-opc.h (Byte): Update comments.
1252         (Word): Likewise.
1253         (Dword): Likewise.
1254         (Fword): Likewise.
1255         (Qword): Likewise.
1256         (Tbyte): Likewise.
1257         (Xmmword): Likewise.
1258         (Ymmword): Likewise.
1259         (Zmmword): Likewise.
1260         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1261         vcvttps2uqq.
1262         * i386-tbl.h: Regenerated.
1263
1264 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1265
1266         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1267         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1268         * aarch64-asm-2.c: Regenerate.
1269         * aarch64-dis-2.c: Regenerate.
1270         * aarch64-opc-2.c: Regenerate.
1271
1272 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1273
1274         PR binutils/23192
1275         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1276         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1277         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1278         sqdmulh, sqrdmulh): Use Em16.
1279
1280 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1281
1282         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1283         csdb together with them.
1284         (thumb32_opcodes): Likewise.
1285
1286 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1287
1288         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1289         requiring 32-bit registers as operands 2 and 3. Improve
1290         comments.
1291         (mwait, mwaitx): Fold templates. Improve comments.
1292         OPERAND_TYPE_INOUTPORTREG.
1293         * i386-tbl.h: Re-generate.
1294
1295 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1296
1297         * i386-gen.c (operand_type_init): Remove
1298         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1299         OPERAND_TYPE_INOUTPORTREG.
1300         * i386-init.h: Re-generate.
1301
1302 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1303
1304         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1305         (wrssq, wrussq): Add Qword.
1306         * i386-tbl.h: Re-generate.
1307
1308 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1309
1310         * i386-opc.h: Rename OTMax to OTNum.
1311         (OTNumOfUints): Adjust calculation.
1312         (OTUnused): Directly alias to OTNum.
1313
1314 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1315
1316         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1317         `reg_xys'.
1318         (lea_reg_xys): Likewise.
1319         (print_insn_loop_primitive): Rename `reg' local variable to
1320         `reg_dxy'.
1321
1322 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1323
1324         PR binutils/23242
1325         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1326
1327 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1328
1329         PR binutils/23369
1330         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1331         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1332
1333 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1334
1335         PR tdep/8282
1336         * mips-dis.c (mips_option_arg_t): New enumeration.
1337         (mips_options): New variable.
1338         (disassembler_options_mips): New function.
1339         (print_mips_disassembler_options): Reimplement in terms of
1340         `disassembler_options_mips'.
1341         * arm-dis.c (disassembler_options_arm): Adapt to using the
1342         `disasm_options_and_args_t' structure.
1343         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1344         * s390-dis.c (disassembler_options_s390): Likewise.
1345
1346 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1347
1348         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1349         expected result.
1350         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1351         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1352         * testsuite/ld-arm/tls-longplt.d: Likewise.
1353
1354 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1355
1356         PR binutils/23192
1357         * aarch64-asm-2.c: Regenerate.
1358         * aarch64-dis-2.c: Likewise.
1359         * aarch64-opc-2.c: Likewise.
1360         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1361         * aarch64-opc.c (operand_general_constraint_met_p,
1362         aarch64_print_operand): Likewise.
1363         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1364         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1365         fmlal2, fmlsl2.
1366         (AARCH64_OPERANDS): Add Em2.
1367
1368 2018-06-26  Nick Clifton  <nickc@redhat.com>
1369
1370         * po/uk.po: Updated Ukranian translation.
1371         * po/de.po: Updated German translation.
1372         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1373
1374 2018-06-26  Nick Clifton  <nickc@redhat.com>
1375
1376         * nfp-dis.c: Fix spelling mistake.
1377
1378 2018-06-24  Nick Clifton  <nickc@redhat.com>
1379
1380         * configure: Regenerate.
1381         * po/opcodes.pot: Regenerate.
1382
1383 2018-06-24  Nick Clifton  <nickc@redhat.com>
1384
1385         2.31 branch created.
1386
1387 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1388
1389         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1390         * aarch64-asm-2.c: Regenerate.
1391         * aarch64-dis-2.c: Likewise.
1392
1393 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1394
1395         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1396         `-M ginv' option description.
1397
1398 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1399
1400         PR gas/23305
1401         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1402         la and lla.
1403
1404 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1405
1406         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1407         * configure.ac: Remove AC_PREREQ.
1408         * Makefile.in: Re-generate.
1409         * aclocal.m4: Re-generate.
1410         * configure: Re-generate.
1411
1412 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1413
1414         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1415         mips64r6 descriptors.
1416         (parse_mips_ase_option): Handle -Mginv option.
1417         (print_mips_disassembler_options): Document -Mginv.
1418         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1419         (GINV): New macro.
1420         (mips_opcodes): Define ginvi and ginvt.
1421
1422 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1423             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1424
1425         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1426         * mips-opc.c (CRC, CRC64): New macros.
1427         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1428         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1429         crc32cd for CRC64.
1430
1431 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1432
1433         PR 20319
1434         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1435         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1436
1437 2018-06-06  Alan Modra  <amodra@gmail.com>
1438
1439         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1440         setjmp.  Move init for some other vars later too.
1441
1442 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1443
1444         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1445         (dis_private): Add new fields for property section tracking.
1446         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1447         (xtensa_instruction_fits): New functions.
1448         (fetch_data): Bump minimal fetch size to 4.
1449         (print_insn_xtensa): Make struct dis_private static.
1450         Load and prepare property table on section change.
1451         Don't disassemble literals. Don't disassemble instructions that
1452         cross property table boundaries.
1453
1454 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1455
1456         * configure: Regenerated.
1457
1458 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1459
1460         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1461         * i386-tbl.h: Re-generate.
1462
1463 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1464
1465         * i386-opc.tbl (sldt, str): Add NoRex64.
1466         * i386-tbl.h: Re-generate.
1467
1468 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1469
1470         * i386-opc.tbl (invpcid): Add Oword.
1471         * i386-tbl.h: Re-generate.
1472
1473 2018-06-01  Alan Modra  <amodra@gmail.com>
1474
1475         * sysdep.h (_bfd_error_handler): Don't declare.
1476         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1477         * rl78-decode.opc: Likewise.
1478         * msp430-decode.c: Regenerate.
1479         * rl78-decode.c: Regenerate.
1480
1481 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1482
1483         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1484         * i386-init.h : Regenerated.
1485
1486 2018-05-25  Alan Modra  <amodra@gmail.com>
1487
1488         * Makefile.in: Regenerate.
1489         * po/POTFILES.in: Regenerate.
1490
1491 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1492
1493         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1494         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1495         (insert_bab, extract_bab, insert_btab, extract_btab,
1496         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1497         (BAT, BBA VBA RBS XB6S): Delete macros.
1498         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1499         (BB, BD, RBX, XC6): Update for new macros.
1500         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1501         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1502         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1503         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1504
1505 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1506
1507         * Makefile.am: Add support for s12z architecture.
1508         * configure.ac: Likewise.
1509         * disassemble.c: Likewise.
1510         * disassemble.h: Likewise.
1511         * Makefile.in: Regenerate.
1512         * configure: Regenerate.
1513         * s12z-dis.c: New file.
1514         * s12z.h: New file.
1515
1516 2018-05-18  Alan Modra  <amodra@gmail.com>
1517
1518         * nfp-dis.c: Don't #include libbfd.h.
1519         (init_nfp3200_priv): Use bfd_get_section_contents.
1520         (nit_nfp6000_mecsr_sec): Likewise.
1521
1522 2018-05-17  Nick Clifton  <nickc@redhat.com>
1523
1524         * po/zh_CN.po: Updated simplified Chinese translation.
1525
1526 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1527
1528         PR binutils/23109
1529         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1530         * aarch64-dis-2.c: Regenerate.
1531
1532 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1533
1534         PR binutils/21446
1535         * aarch64-asm.c (opintl.h): Include.
1536         (aarch64_ins_sysreg): Enforce read/write constraints.
1537         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1538         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1539         (F_REG_READ, F_REG_WRITE): New.
1540         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1541         AARCH64_OPND_SYSREG.
1542         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1543         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1544         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1545         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1546         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1547         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1548         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1549         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1550         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1551         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1552         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1553         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1554         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1555         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1556         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1557         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1558         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1559
1560 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1561
1562         PR binutils/21446
1563         * aarch64-dis.c (no_notes: New.
1564         (parse_aarch64_dis_option): Support notes.
1565         (aarch64_decode_insn, print_operands): Likewise.
1566         (print_aarch64_disassembler_options): Document notes.
1567         * aarch64-opc.c (aarch64_print_operand): Support notes.
1568
1569 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1570
1571         PR binutils/21446
1572         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1573         and take error struct.
1574         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1575         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1576         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1577         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1578         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1579         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1580         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1581         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1582         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1583         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1584         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1585         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1586         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1587         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1588         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1589         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1590         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1591         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1592         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1593         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1594         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1595         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1596         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1597         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1598         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1599         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1600         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1601         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1602         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1603         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1604         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1605         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1606         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1607         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1608         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1609         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1610         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1611         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1612         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1613         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1614         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1615         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1616         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1617         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1618         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1619         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1620         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1621         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1622         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1623         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1624         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1625         (determine_disassembling_preference, aarch64_decode_insn,
1626         print_insn_aarch64_word, print_insn_data): Take errors struct.
1627         (print_insn_aarch64): Use errors.
1628         * aarch64-asm-2.c: Regenerate.
1629         * aarch64-dis-2.c: Regenerate.
1630         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1631         boolean in aarch64_insert_operan.
1632         (print_operand_extractor): Likewise.
1633         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1634
1635 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1636
1637         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1638
1639 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1640
1641         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1642
1643 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1644
1645         * cr16-opc.c (cr16_instruction): Comment typo fix.
1646         * hppa-dis.c (print_insn_hppa): Likewise.
1647
1648 2018-05-08  Jim Wilson  <jimw@sifive.com>
1649
1650         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1651         (match_c_slli64, match_srxi_as_c_srxi): New.
1652         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1653         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1654         <c.slli, c.srli, c.srai>: Use match_s_slli.
1655         <c.slli64, c.srli64, c.srai64>: New.
1656
1657 2018-05-08  Alan Modra  <amodra@gmail.com>
1658
1659         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1660         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1661         partition opcode space for index lookup.
1662
1663 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1664
1665         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1666         <insn_length>: ...with this.  Update usage.
1667         Remove duplicate call to *info->memory_error_func.
1668
1669 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1670             H.J. Lu  <hongjiu.lu@intel.com>
1671
1672         * i386-dis.c (Gva): New.
1673         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1674         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1675         (prefix_table): New instructions (see prefix above).
1676         (mod_table): New instructions (see prefix above).
1677         (OP_G): Handle va_mode.
1678         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1679         CPU_MOVDIR64B_FLAGS.
1680         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1681         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1682         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1683         * i386-opc.tbl: Add movidir{i,64b}.
1684         * i386-init.h: Regenerated.
1685         * i386-tbl.h: Likewise.
1686
1687 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1688
1689         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1690         AddrPrefixOpReg.
1691         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1692         (AddrPrefixOpReg): This.
1693         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1694         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1695
1696 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1697
1698         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1699         (vle_num_opcodes): Likewise.
1700         (spe2_num_opcodes): Likewise.
1701         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1702         initialization loop.
1703         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1704         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1705         only once.
1706
1707 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1708
1709         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1710
1711 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1712
1713         Makefile.am: Added nfp-dis.c.
1714         configure.ac: Added bfd_nfp_arch.
1715         disassemble.h: Added print_insn_nfp prototype.
1716         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1717         nfp-dis.c: New, for NFP support.
1718         po/POTFILES.in: Added nfp-dis.c to the list.
1719         Makefile.in: Regenerate.
1720         configure: Regenerate.
1721
1722 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1723
1724         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1725         templates into their base ones.
1726         * i386-tlb.h: Re-generate.
1727
1728 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1729
1730         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1731         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1732         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1733         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1734         * i386-init.h: Re-generate.
1735
1736 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1737
1738         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1739         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1740         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1741         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1742         comment.
1743         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1744         and CpuRegMask.
1745         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1746         CpuRegMask: Delete.
1747         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1748         cpuregzmm, and cpuregmask.
1749         * i386-init.h: Re-generate.
1750         * i386-tbl.h: Re-generate.
1751
1752 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1753
1754         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1755         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1756         * i386-init.h: Re-generate.
1757
1758 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1759
1760         * i386-gen.c (VexImmExt): Delete.
1761         * i386-opc.h (VexImmExt, veximmext): Delete.
1762         * i386-opc.tbl: Drop all VexImmExt uses.
1763         * i386-tlb.h: Re-generate.
1764
1765 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1766
1767         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1768         register-only forms.
1769         * i386-tlb.h: Re-generate.
1770
1771 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1772
1773         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1774
1775 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1776
1777         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1778         PREFIX_0F1C.
1779         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1780         (cpu_flags): Add CpuCLDEMOTE.
1781         * i386-init.h: Regenerate.
1782         * i386-opc.h (enum): Add CpuCLDEMOTE,
1783         (i386_cpu_flags): Add cpucldemote.
1784         * i386-opc.tbl: Add cldemote.
1785         * i386-tbl.h: Regenerate.
1786
1787 2018-04-16  Alan Modra  <amodra@gmail.com>
1788
1789         * Makefile.am: Remove sh5 and sh64 support.
1790         * configure.ac: Likewise.
1791         * disassemble.c: Likewise.
1792         * disassemble.h: Likewise.
1793         * sh-dis.c: Likewise.
1794         * sh64-dis.c: Delete.
1795         * sh64-opc.c: Delete.
1796         * sh64-opc.h: Delete.
1797         * Makefile.in: Regenerate.
1798         * configure: Regenerate.
1799         * po/POTFILES.in: Regenerate.
1800
1801 2018-04-16  Alan Modra  <amodra@gmail.com>
1802
1803         * Makefile.am: Remove w65 support.
1804         * configure.ac: Likewise.
1805         * disassemble.c: Likewise.
1806         * disassemble.h: Likewise.
1807         * w65-dis.c: Delete.
1808         * w65-opc.h: Delete.
1809         * Makefile.in: Regenerate.
1810         * configure: Regenerate.
1811         * po/POTFILES.in: Regenerate.
1812
1813 2018-04-16  Alan Modra  <amodra@gmail.com>
1814
1815         * configure.ac: Remove we32k support.
1816         * configure: Regenerate.
1817
1818 2018-04-16  Alan Modra  <amodra@gmail.com>
1819
1820         * Makefile.am: Remove m88k support.
1821         * configure.ac: Likewise.
1822         * disassemble.c: Likewise.
1823         * disassemble.h: Likewise.
1824         * m88k-dis.c: Delete.
1825         * Makefile.in: Regenerate.
1826         * configure: Regenerate.
1827         * po/POTFILES.in: Regenerate.
1828
1829 2018-04-16  Alan Modra  <amodra@gmail.com>
1830
1831         * Makefile.am: Remove i370 support.
1832         * configure.ac: Likewise.
1833         * disassemble.c: Likewise.
1834         * disassemble.h: Likewise.
1835         * i370-dis.c: Delete.
1836         * i370-opc.c: Delete.
1837         * Makefile.in: Regenerate.
1838         * configure: Regenerate.
1839         * po/POTFILES.in: Regenerate.
1840
1841 2018-04-16  Alan Modra  <amodra@gmail.com>
1842
1843         * Makefile.am: Remove h8500 support.
1844         * configure.ac: Likewise.
1845         * disassemble.c: Likewise.
1846         * disassemble.h: Likewise.
1847         * h8500-dis.c: Delete.
1848         * h8500-opc.h: Delete.
1849         * Makefile.in: Regenerate.
1850         * configure: Regenerate.
1851         * po/POTFILES.in: Regenerate.
1852
1853 2018-04-16  Alan Modra  <amodra@gmail.com>
1854
1855         * configure.ac: Remove tahoe support.
1856         * configure: Regenerate.
1857
1858 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1859
1860         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1861         umwait.
1862         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1863         64-bit mode.
1864         * i386-tbl.h: Regenerated.
1865
1866 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1867
1868         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1869         PREFIX_MOD_1_0FAE_REG_6.
1870         (va_mode): New.
1871         (OP_E_register): Use va_mode.
1872         * i386-dis-evex.h (prefix_table):
1873         New instructions (see prefixes above).
1874         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1875         (cpu_flags): Likewise.
1876         * i386-opc.h (enum): Likewise.
1877         (i386_cpu_flags): Likewise.
1878         * i386-opc.tbl: Add umonitor, umwait, tpause.
1879         * i386-init.h: Regenerate.
1880         * i386-tbl.h: Likewise.
1881
1882 2018-04-11  Alan Modra  <amodra@gmail.com>
1883
1884         * opcodes/i860-dis.c: Delete.
1885         * opcodes/i960-dis.c: Delete.
1886         * Makefile.am: Remove i860 and i960 support.
1887         * configure.ac: Likewise.
1888         * disassemble.c: Likewise.
1889         * disassemble.h: Likewise.
1890         * Makefile.in: Regenerate.
1891         * configure: Regenerate.
1892         * po/POTFILES.in: Regenerate.
1893
1894 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1895
1896         PR binutils/23025
1897         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1898         to 0.
1899         (print_insn): Clear vex instead of vex.evex.
1900
1901 2018-04-04  Nick Clifton  <nickc@redhat.com>
1902
1903         * po/es.po: Updated Spanish translation.
1904
1905 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1906
1907         * i386-gen.c (opcode_modifiers): Delete VecESize.
1908         * i386-opc.h (VecESize): Delete.
1909         (struct i386_opcode_modifier): Delete vecesize.
1910         * i386-opc.tbl: Drop VecESize.
1911         * i386-tlb.h: Re-generate.
1912
1913 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1914
1915         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1916         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1917         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1918         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1919         * i386-tlb.h: Re-generate.
1920
1921 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1922
1923         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1924         Fold AVX512 forms
1925         * i386-tlb.h: Re-generate.
1926
1927 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1928
1929         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1930         (vex_len_table): Drop Y for vcvt*2si.
1931         (putop): Replace plain 'Y' handling by abort().
1932
1933 2018-03-28  Nick Clifton  <nickc@redhat.com>
1934
1935         PR 22988
1936         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1937         instructions with only a base address register.
1938         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1939         handle AARHC64_OPND_SVE_ADDR_R.
1940         (aarch64_print_operand): Likewise.
1941         * aarch64-asm-2.c: Regenerate.
1942         * aarch64_dis-2.c: Regenerate.
1943         * aarch64-opc-2.c: Regenerate.
1944
1945 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1946
1947         * i386-opc.tbl: Drop VecESize from register only insn forms and
1948         memory forms not allowing broadcast.
1949         * i386-tlb.h: Re-generate.
1950
1951 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1952
1953         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1954         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1955         sha256*): Drop Disp<N>.
1956
1957 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1958
1959         * i386-dis.c (EbndS, bnd_swap_mode): New.
1960         (prefix_table): Use EbndS.
1961         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1962         * i386-opc.tbl (bndmov): Move misplaced Load.
1963         * i386-tlb.h: Re-generate.
1964
1965 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1966
1967         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1968         templates allowing memory operands and folded ones for register
1969         only flavors.
1970         * i386-tlb.h: Re-generate.
1971
1972 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1973
1974         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1975         256-bit templates. Drop redundant leftover Disp<N>.
1976         * i386-tlb.h: Re-generate.
1977
1978 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1979
1980         * riscv-opc.c (riscv_insn_types): New.
1981
1982 2018-03-13  Nick Clifton  <nickc@redhat.com>
1983
1984         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1985
1986 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1987
1988         * i386-opc.tbl: Add Optimize to clr.
1989         * i386-tbl.h: Regenerated.
1990
1991 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1992
1993         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1994         * i386-opc.h (OldGcc): Removed.
1995         (i386_opcode_modifier): Remove oldgcc.
1996         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1997         instructions for old (<= 2.8.1) versions of gcc.
1998         * i386-tbl.h: Regenerated.
1999
2000 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2001
2002         * i386-opc.h (EVEXDYN): New.
2003         * i386-opc.tbl: Fold various AVX512VL templates.
2004         * i386-tlb.h: Re-generate.
2005
2006 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2007
2008         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2009         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2010         vpexpandd, vpexpandq): Fold AFX512VF templates.
2011         * i386-tlb.h: Re-generate.
2012
2013 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2014
2015         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2016         Fold 128- and 256-bit VEX-encoded templates.
2017         * i386-tlb.h: Re-generate.
2018
2019 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2020
2021         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2022         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2023         vpexpandd, vpexpandq): Fold AVX512F templates.
2024         * i386-tlb.h: Re-generate.
2025
2026 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2027
2028         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2029         64-bit templates. Drop Disp<N>.
2030         * i386-tlb.h: Re-generate.
2031
2032 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2033
2034         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2035         and 256-bit templates.
2036         * i386-tlb.h: Re-generate.
2037
2038 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2039
2040         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2041         * i386-tlb.h: Re-generate.
2042
2043 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2044
2045         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2046         Drop NoAVX.
2047         * i386-tlb.h: Re-generate.
2048
2049 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2050
2051         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2052         * i386-tlb.h: Re-generate.
2053
2054 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2055
2056         * i386-gen.c (opcode_modifiers): Delete FloatD.
2057         * i386-opc.h (FloatD): Delete.
2058         (struct i386_opcode_modifier): Delete floatd.
2059         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2060         FloatD by D.
2061         * i386-tlb.h: Re-generate.
2062
2063 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2064
2065         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2066
2067 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2068
2069         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2070         * i386-tlb.h: Re-generate.
2071
2072 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2073
2074         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2075         forms.
2076         * i386-tlb.h: Re-generate.
2077
2078 2018-03-07  Alan Modra  <amodra@gmail.com>
2079
2080         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2081         bfd_arch_rs6000.
2082         * disassemble.h (print_insn_rs6000): Delete.
2083         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2084         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2085         (print_insn_rs6000): Delete.
2086
2087 2018-03-03  Alan Modra  <amodra@gmail.com>
2088
2089         * sysdep.h (opcodes_error_handler): Define.
2090         (_bfd_error_handler): Declare.
2091         * Makefile.am: Remove stray #.
2092         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2093         EDIT" comment.
2094         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2095         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2096         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2097         opcodes_error_handler to print errors.  Standardize error messages.
2098         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2099         and include opintl.h.
2100         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2101         * i386-gen.c: Standardize error messages.
2102         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2103         * Makefile.in: Regenerate.
2104         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2105         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2106         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2107         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2108         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2109         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2110         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2111         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2112         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2113         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2114         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2115         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2116         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2117
2118 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2119
2120         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2121         vpsub[bwdq] instructions.
2122         * i386-tbl.h: Regenerated.
2123
2124 2018-03-01  Alan Modra  <amodra@gmail.com>
2125
2126         * configure.ac (ALL_LINGUAS): Sort.
2127         * configure: Regenerate.
2128
2129 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2130
2131         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2132         macro by assignements.
2133
2134 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2135
2136         PR gas/22871
2137         * i386-gen.c (opcode_modifiers): Add Optimize.
2138         * i386-opc.h (Optimize): New enum.
2139         (i386_opcode_modifier): Add optimize.
2140         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2141         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2142         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2143         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2144         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2145         vpxord and vpxorq.
2146         * i386-tbl.h: Regenerated.
2147
2148 2018-02-26  Alan Modra  <amodra@gmail.com>
2149
2150         * crx-dis.c (getregliststring): Allocate a large enough buffer
2151         to silence false positive gcc8 warning.
2152
2153 2018-02-22  Shea Levy <shea@shealevy.com>
2154
2155         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2156
2157 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2158
2159         * i386-opc.tbl: Add {rex},
2160         * i386-tbl.h: Regenerated.
2161
2162 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2163
2164         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2165         (mips16_opcodes): Replace `M' with `m' for "restore".
2166
2167 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2168
2169         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2170
2171 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2172
2173         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2174         variable to `function_index'.
2175
2176 2018-02-13  Nick Clifton  <nickc@redhat.com>
2177
2178         PR 22823
2179         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2180         about truncation of printing.
2181
2182 2018-02-12  Henry Wong <henry@stuffedcow.net>
2183
2184         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2185
2186 2018-02-05  Nick Clifton  <nickc@redhat.com>
2187
2188         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2189
2190 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2191
2192         * i386-dis.c (enum): Add pconfig.
2193         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2194         (cpu_flags): Add CpuPCONFIG.
2195         * i386-opc.h (enum): Add CpuPCONFIG.
2196         (i386_cpu_flags): Add cpupconfig.
2197         * i386-opc.tbl: Add PCONFIG instruction.
2198         * i386-init.h: Regenerate.
2199         * i386-tbl.h: Likewise.
2200
2201 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2202
2203         * i386-dis.c (enum): Add PREFIX_0F09.
2204         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2205         (cpu_flags): Add CpuWBNOINVD.
2206         * i386-opc.h (enum): Add CpuWBNOINVD.
2207         (i386_cpu_flags): Add cpuwbnoinvd.
2208         * i386-opc.tbl: Add WBNOINVD instruction.
2209         * i386-init.h: Regenerate.
2210         * i386-tbl.h: Likewise.
2211
2212 2018-01-17  Jim Wilson  <jimw@sifive.com>
2213
2214         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2215
2216 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2217
2218         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2219         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2220         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2221         (cpu_flags): Add CpuIBT, CpuSHSTK.
2222         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2223         (i386_cpu_flags): Add cpuibt, cpushstk.
2224         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2225         * i386-init.h: Regenerate.
2226         * i386-tbl.h: Likewise.
2227
2228 2018-01-16  Nick Clifton  <nickc@redhat.com>
2229
2230         * po/pt_BR.po: Updated Brazilian Portugese translation.
2231         * po/de.po: Updated German translation.
2232
2233 2018-01-15  Jim Wilson  <jimw@sifive.com>
2234
2235         * riscv-opc.c (match_c_nop): New.
2236         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2237
2238 2018-01-15  Nick Clifton  <nickc@redhat.com>
2239
2240         * po/uk.po: Updated Ukranian translation.
2241
2242 2018-01-13  Nick Clifton  <nickc@redhat.com>
2243
2244         * po/opcodes.pot: Regenerated.
2245
2246 2018-01-13  Nick Clifton  <nickc@redhat.com>
2247
2248         * configure: Regenerate.
2249
2250 2018-01-13  Nick Clifton  <nickc@redhat.com>
2251
2252         2.30 branch created.
2253
2254 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2255
2256         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2257         * i386-tbl.h: Regenerate.
2258
2259 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2260
2261         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2262         * i386-tbl.h: Re-generate.
2263
2264 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2265
2266         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2267         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2268         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2269         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2270         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2271         Disp8MemShift of AVX512VL forms.
2272         * i386-tbl.h: Re-generate.
2273
2274 2018-01-09  Jim Wilson  <jimw@sifive.com>
2275
2276         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2277         then the hi_addr value is zero.
2278
2279 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2280
2281         * arm-dis.c (arm_opcodes): Add csdb.
2282         (thumb32_opcodes): Add csdb.
2283
2284 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2285
2286         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2287         * aarch64-asm-2.c: Regenerate.
2288         * aarch64-dis-2.c: Regenerate.
2289         * aarch64-opc-2.c: Regenerate.
2290
2291 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2292
2293         PR gas/22681
2294         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2295         Remove AVX512 vmovd with 64-bit operands.
2296         * i386-tbl.h: Regenerated.
2297
2298 2018-01-05  Jim Wilson  <jimw@sifive.com>
2299
2300         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2301         jalr.
2302
2303 2018-01-03  Alan Modra  <amodra@gmail.com>
2304
2305         Update year range in copyright notice of all files.
2306
2307 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2308
2309         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2310         and OPERAND_TYPE_REGZMM entries.
2311
2312 For older changes see ChangeLog-2017
2313 \f
2314 Copyright (C) 2018 Free Software Foundation, Inc.
2315
2316 Copying and distribution of this file, with or without modification,
2317 are permitted in any medium without royalty provided the copyright
2318 notice and this notice are preserved.
2319
2320 Local Variables:
2321 mode: change-log
2322 left-margin: 8
2323 fill-column: 74
2324 version-control: never
2325 End: