opcodes/ChangeLog

   1 2005-02-21  Alan Modra  <amodra@bigpond.net.au>
   2
   3         * Makefile.am: Run "make dep-am"
   4         * Makefile.in: Regenerate.
   5
   6 2005-02-15  Nick Clifton  <nickc@redhat.com>
   7
   8         * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
   9         compile time warnings.
  10         (print_keyword): Likewise.
  11         (default_print_insn): Likewise.
  12
  13         * fr30-desc.c: Regenerated.
  14         * fr30-desc.h: Regenerated.
  15         * fr30-dis.c: Regenerated.
  16         * fr30-opc.c: Regenerated.
  17         * fr30-opc.h: Regenerated.
  18         * frv-desc.c: Regenerated.
  19         * frv-dis.c: Regenerated.
  20         * frv-opc.c: Regenerated.
  21         * ip2k-asm.c: Regenerated.
  22         * ip2k-desc.c: Regenerated.
  23         * ip2k-desc.h: Regenerated.
  24         * ip2k-dis.c: Regenerated.
  25         * ip2k-opc.c: Regenerated.
  26         * ip2k-opc.h: Regenerated.
  27         * iq2000-desc.c: Regenerated.
  28         * iq2000-dis.c: Regenerated.
  29         * iq2000-opc.c: Regenerated.
  30         * m32r-asm.c: Regenerated.
  31         * m32r-desc.c: Regenerated.
  32         * m32r-desc.h: Regenerated.
  33         * m32r-dis.c: Regenerated.
  34         * m32r-opc.c: Regenerated.
  35         * m32r-opc.h: Regenerated.
  36         * m32r-opinst.c: Regenerated.
  37         * openrisc-desc.c: Regenerated.
  38         * openrisc-desc.h: Regenerated.
  39         * openrisc-dis.c: Regenerated.
  40         * openrisc-opc.c: Regenerated.
  41         * openrisc-opc.h: Regenerated.
  42         * xstormy16-desc.c: Regenerated.
  43         * xstormy16-desc.h: Regenerated.
  44         * xstormy16-dis.c: Regenerated.
  45         * xstormy16-opc.c: Regenerated.
  46         * xstormy16-opc.h: Regenerated.
  47
  48 2005-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  49
  50         * dis-buf.c (perror_memory): Use sprintf_vma to print out
  51         address.
  52
  53 2005-02-11  Nick Clifton  <nickc@redhat.com>
  54
  55         * iq2000-asm.c: Regenerate.
  56
  57         * frv-dis.c: Regenerate.
  58
  59 2005-02-07  Jim Blandy  <jimb@redhat.com>
  60
  61         * Makefile.am (CGEN): Load guile.scm before calling the main
  62         application script.
  63         * Makefile.in: Regenerated.
  64         * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
  65         Simply pass the cgen-opc.scm path to ${cgen} as its first
  66         argument; ${cgen} itself now contains the '-s', or whatever is
  67         appropriate for the Scheme being used.
  68
  69 2005-01-31  Andrew Cagney  <cagney@gnu.org>
  70
  71         * configure: Regenerate to track ../gettext.m4.
  72
  73 2005-01-31  Jan Beulich  <jbeulich@novell.com>
  74
  75         * ia64-gen.c (NELEMS): Define.
  76         (shrink): Generate alias with missing second predicate register when
  77         opcode has two outputs and these are both predicates.
  78         * ia64-opc-i.c (FULL17): Define.
  79         (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
  80         here to generate output template.
  81         (TBITCM, TNATCM): Undefine after use.
  82         * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
  83         first input. Add ld16 aliases without ar.csd as second output. Add
  84         st16 aliases without ar.csd as second input. Add cmpxchg aliases
  85         without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
  86         ar.ccv as third/fourth inputs. Consolidate through...
  87         (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
  88         CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
  89         * ia64-asmtab.c: Regenerate.
  90
  91 2005-01-27  Andrew Cagney  <cagney@gnu.org>
  92
  93         * configure: Regenerate to track ../gettext.m4 change.
  94
  95 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  96
  97         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  98         * frv-asm.c: Rebuilt.
  99         * frv-desc.c: Rebuilt.
 100         * frv-desc.h: Rebuilt.
 101         * frv-dis.c: Rebuilt.
 102         * frv-ibld.c: Rebuilt.
 103         * frv-opc.c: Rebuilt.
 104         * frv-opc.h: Rebuilt.
 105
 106 2005-01-24  Andrew Cagney  <cagney@gnu.org>
 107
 108         * configure: Regenerate, ../gettext.m4 was updated.
 109
 110 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 111
 112         * mips-opc.c:  Change INSN_ALIAS to INSN2_ALIAS.
 113         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 114         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 115         * mips-dis.c: Ditto.
 116
 117 2005-01-20  Alan Modra  <amodra@bigpond.net.au>
 118
 119         * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
 120
 121 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 122
 123         * mips-dis.c (no_aliases): New disassembly option flag.
 124         (set_default_mips_dis_options): Init no_aliases to zero.
 125         (parse_mips_dis_option): Handle no-aliases option.
 126         (print_insn_mips): Ignore table entries that are aliases
 127         if no_aliases is set.
 128         (print_insn_mips16): Ditto.
 129         * mips-opc.c (mips_builtin_opcodes): Add initializer column for
 130         new pinfo2 member and add INSN_ALIAS initializers as needed.  Also
 131         move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
 132         * mips16-opc.c (mips16_opcodes): Ditto.
 133
 134 2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
 135
 136         * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
 137         (inheritance diagram): Add missing edge.
 138         (arch_sh1_up): Rename arch_sh_up to match external name to make life
 139         easier for the testsuite.
 140         (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
 141         (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
 142         (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
 143         arch_sh2a_or_sh4_up child.
 144         (sh_table): Do renaming as above.
 145         Correct comment for ldc.l for gas testsuite to read.
 146         Remove rogue mul.l from sh1 (duplicate of the one for sh2).
 147         Correct comments for movy.w and movy.l for gas testsuite to read.
 148         Correct comments for fmov.d and fmov.s for gas testsuite to read.
 149
 150 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 151
 152         * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
 153
 154 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
 157
 158 2005-01-10  Andreas Schwab  <schwab@suse.de>
 159
 160         * disassemble.c (disassemble_init_for_target) <case
 161         bfd_arch_ia64>: Set skip_zeroes to 16.
 162         <case bfd_arch_tic4x>: Set skip_zeroes to 32.
 163
 164 2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
 165
 166         * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
 167
 168 2004-12-14  Svein E. Seldal  <Svein.Seldal@solidas.com>
 169
 170         * avr-dis.c: Prettyprint. Added printing of symbol names in all
 171         memory references. Convert avr_operand() to C90 formatting.
 172
 173 2004-12-05  Tomer Levi  <Tomer.Levi@nsc.com>
 174
 175         * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
 176
 177 2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 178
 179         * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
 180         (no_op_insn): Initialize array with instructions that have no
 181         operands.
 182         * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
 183
 184 2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
 185
 186         * arm-dis.c: Correct top-level comment.
 187
 188 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
 189
 190         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
 191         architecuture defining the insn.
 192         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
 193         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
 194         field.
 195         Also include opcode/arm.h.
 196         * Makefile.am (arm-dis.lo): Update dependency list.
 197         * Makefile.in: Regenerate.
 198
 199 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
 200
 201         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
 202         reflect the change to the short immediate syntax.
 203
 204 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 205
 206         * or32-opc.c (debug): Warning fix.
 207         * po/POTFILES.in: Regenerate.
 208
 209         * maxq-dis.c: Formatting.
 210         (print_insn): Warning fix.
 211
 212 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
 213
 214         * arm-dis.c (WORD_ADDRESS): Define.
 215         (print_insn): Use it.  Correct big-endian end-of-section handling.
 216
 217 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 218             Vineet Sharma      <vineets@noida.hcltech.com>
 219
 220         * maxq-dis.c: New file.
 221         * disassemble.c (ARCH_maxq): Define.
 222         (disassembler): Add 'print_insn_maxq_little' for handling maxq
 223         instructions..
 224         * configure.in: Add case for bfd_maxq_arch.
 225         * configure: Regenerate.
 226         * Makefile.am: Add support for maxq-dis.c
 227         * Makefile.in: Regenerate.
 228         * aclocal.m4: Regenerate.
 229
 230 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 231
 232         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
 233         mode.
 234         * crx-dis.c: Likewise.
 235
 236 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 237
 238         Generally, handle CRISv32.
 239         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
 240         (struct cris_disasm_data): New type.
 241         (format_reg, format_hex, cris_constraint, print_flags)
 242         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
 243         callers changed.
 244         (format_sup_reg, print_insn_crisv32_with_register_prefix)
 245         (print_insn_crisv32_without_register_prefix)
 246         (print_insn_crisv10_v32_with_register_prefix)
 247         (print_insn_crisv10_v32_without_register_prefix)
 248         (cris_parse_disassembler_options): New functions.
 249         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
 250         parameter.  All callers changed.
 251         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
 252         failure.
 253         (cris_constraint) <case 'Y', 'U'>: New cases.
 254         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
 255         for constraint 'n'.
 256         (print_with_operands) <case 'Y'>: New case.
 257         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
 258         <case 'N', 'Y', 'Q'>: New cases.
 259         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
 260         (print_insn_cris_with_register_prefix)
 261         (print_insn_cris_without_register_prefix): Call
 262         cris_parse_disassembler_options.
 263         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
 264         for CRISv32 and the size of immediate operands.  New v32-only
 265         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
 266         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
 267         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
 268         Change brp to be v3..v10.
 269         (cris_support_regs): New vector.
 270         (cris_opcodes): Update head comment.  New format characters '[',
 271         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
 272         Add new opcodes for v32 and adjust existing opcodes to accommodate
 273         differences to earlier variants.
 274         (cris_cond15s): New vector.
 275
 276 2004-11-04 Jan Beulich <jbeulich@novell.com>
 277
 278         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
 279         (indirEb): Remove.
 280         (Mp): Use f_mode rather than none at all.
 281         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
 282         replaces what previously was x_mode; x_mode now means 128-bit SSE
 283         operands.
 284         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
 285         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
 286         pinsrw's second operand is Edqw.
 287         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 288         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 289         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 290         mode when an operand size override is present or always suffixing.
 291         More instructions will need to be added to this group.
 292         (putop): Handle new macro chars 'C' (short/long suffix selector),
 293         'I' (Intel mode override for following macro char), and 'J' (for
 294         adding the 'l' prefix to far branches in AT&T mode). When an
 295         alternative was specified in the template, honor macro character when
 296         specified for Intel mode.
 297         (OP_E): Handle new *_mode values. Correct pointer specifications for
 298         memory operands. Consolidate output of index register.
 299         (OP_G): Handle new *_mode values.
 300         (OP_I): Handle const_1_mode.
 301         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 302         respective opcode prefix bits have been consumed.
 303         (OP_EM, OP_EX): Provide some default handling for generating pointer
 304         specifications.
 305
 306 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 307
 308         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 309         COP_INST macro.
 310
 311 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 312
 313         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 314         (getregliststring): Support HI/LO and user registers.
 315         * crx-opc.c (crx_instruction): Update data structure according to the
 316         rearrangement done in CRX opcode header file.
 317         (crx_regtab):  Likewise.
 318         (crx_optab):  Likewise.
 319         (crx_instruction): Reorder load/stor instructions, remove unsupported
 320         formats.
 321         support new Co-Processor instruction 'cpi'.
 322
 323 2004-10-27  Nick Clifton  <nickc@redhat.com>
 324
 325         * opcodes/iq2000-asm.c: Regenerate.
 326         * opcodes/iq2000-desc.c: Regenerate.
 327         * opcodes/iq2000-desc.h: Regenerate.
 328         * opcodes/iq2000-dis.c: Regenerate.
 329         * opcodes/iq2000-ibld.c: Regenerate.
 330         * opcodes/iq2000-opc.c: Regenerate.
 331         * opcodes/iq2000-opc.h: Regenerate.
 332
 333 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 334
 335         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 336         us4, us5 (respectively).
 337         Remove unsupported 'popa' instruction.
 338         Reverse operands order in store co-processor instructions.
 339
 340 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 341
 342         * Makefile.am: Run "make dep-am"
 343         * Makefile.in: Regenerate.
 344
 345 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 346
 347         * xtensa-dis.c: Use ISO C90 formatting.
 348
 349 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 350
 351         * ppc-opc.c: Revert 2004-09-09 change.
 352
 353 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 354
 355         * xtensa-dis.c (state_names): Delete.
 356         (fetch_data): Use xtensa_isa_maxlength.
 357         (print_xtensa_operand): Replace operand parameter with opcode/operand
 358         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 359         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 360         instruction bundles.  Use xmalloc instead of malloc.
 361
 362 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 363
 364         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 365         initializers.
 366
 367 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 368
 369         * crx-opc.c (crx_instruction): Support Co-processor insns.
 370         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 371         (getregliststring): Change function to use the above enum.
 372         (print_arg): Handle CO-Processor insns.
 373         (crx_cinvs): Add 'b' option to invalidate the branch-target
 374         cache.
 375
 376 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 377
 378         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 379         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 380         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 381         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 382         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 383
 384 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 385
 386         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 387         rather than add it.
 388
 389 2004-09-30  Paul Brook  <paul@codesourcery.com>
 390
 391         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 392         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 393
 394 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 395
 396         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 397         (CONFIG_STATUS_DEPENDENCIES): New.
 398         (Makefile): Removed.
 399         (config.status): Likewise.
 400         * Makefile.in: Regenerated.
 401
 402 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 403
 404         * Makefile.am: Run "make dep-am".
 405         * Makefile.in: Regenerate.
 406         * aclocal.m4: Regenerate.
 407         * configure: Regenerate.
 408         * po/POTFILES.in: Regenerate.
 409         * po/opcodes.pot: Regenerate.
 410
 411 2004-09-11  Andreas Schwab  <schwab@suse.de>
 412
 413         * configure: Rebuild.
 414
 415 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 416
 417         * ppc-opc.c (L): Make this field not optional.
 418
 419 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 420
 421         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 422         Fix parameter to 'm[t|f]csr' insns.
 423
 424 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 425
 426         * configure.in: Autoupdate to autoconf 2.59.
 427         * aclocal.m4: Rebuild with aclocal 1.4p6.
 428         * configure: Rebuild with autoconf 2.59.
 429         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 430         bfd changes for autoconf 2.59 on the way).
 431         * config.in: Rebuild with autoheader 2.59.
 432
 433 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 434
 435         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 436
 437 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 438
 439         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 440         (GRPPADLCK2): New define.
 441         (twobyte_has_modrm): True for 0xA6.
 442         (grps): GRPPADLCK2 for opcode 0xA6.
 443
 444 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 445
 446         Introduce SH2a support.
 447         * sh-opc.h (arch_sh2a_base): Renumber.
 448         (arch_sh2a_nofpu_base): Remove.
 449         (arch_sh_base_mask): Adjust.
 450         (arch_opann_mask): New.
 451         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 452         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 453         (sh_table): Adjust whitespace.
 454         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 455         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 456         instruction list throughout.
 457         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 458         of arch_sh2a in instruction list throughout.
 459         (arch_sh2e_up): Accomodate above changes.
 460         (arch_sh2_up): Ditto.
 461         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 462         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 463         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 464         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 465         * sh-opc.h (arch_sh2a_nofpu): New.
 466         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 467         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 468         instruction.
 469         2004-01-20  DJ Delorie  <dj@redhat.com>
 470         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 471         2003-12-29  DJ Delorie  <dj@redhat.com>
 472         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 473         sh_opcode_info, sh_table): Add sh2a support.
 474         (arch_op32): New, to tag 32-bit opcodes.
 475         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 476         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 477         * sh-opc.h (arch_sh2a): Add.
 478         * sh-dis.c (arch_sh2a): Handle.
 479         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 480
 481 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 482
 483         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 484
 485 2004-07-22  Nick Clifton  <nickc@redhat.com>
 486
 487         PR/280
 488         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 489         insns - this is done by objdump itself.
 490         * h8500-dis.c (print_insn_h8500): Likewise.
 491
 492 2004-07-21  Jan Beulich <jbeulich@novell.com>
 493
 494         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 495         regardless of address size prefix in effect.
 496         (ptr_reg): Size or address registers does not depend on rex64, but
 497         on the presence of an address size override.
 498         (OP_MMX): Use rex.x only for xmm registers.
 499         (OP_EM): Use rex.z only for xmm registers.
 500
 501 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 502
 503         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 504         move/branch operations to the bottom so that VR5400 multimedia
 505         instructions take precedence in disassembly.
 506
 507 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 508
 509         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 510         ISA-specific "break" encoding.
 511
 512 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 513
 514         * arm-opc.h: Fix typo in comment.
 515
 516 2004-07-11  Andreas Schwab  <schwab@suse.de>
 517
 518         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 519
 520 2004-07-09  Andreas Schwab  <schwab@suse.de>
 521
 522         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 523
 524 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 525
 526         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 527         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 528         (crx-dis.lo): New target.
 529         (crx-opc.lo): Likewise.
 530         * Makefile.in: Regenerate.
 531         * configure.in: Handle bfd_crx_arch.
 532         * configure: Regenerate.
 533         * crx-dis.c: New file.
 534         * crx-opc.c: New file.
 535         * disassemble.c (ARCH_crx): Define.
 536         (disassembler): Handle ARCH_crx.
 537
 538 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 539
 540         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 541         * ia64-asmtab.c: Regnerate.
 542
 543 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 544
 545         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 546         (extract_fxm): Don't test dialect.
 547         (XFXFXM_MASK): Include the power4 bit.
 548         (XFXM): Add p4 param.
 549         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 550
 551 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 552
 553         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 554         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 555
 556 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 557
 558         * ppc-opc.c (BH, XLBH_MASK): Define.
 559         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 560
 561 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 562
 563         * i386-dis.c (x_mode): Comment.
 564         (two_source_ops): File scope.
 565         (float_mem): Correct fisttpll and fistpll.
 566         (float_mem_mode): New table.
 567         (dofloat): Use it.
 568         (OP_E): Correct intel mode PTR output.
 569         (ptr_reg): Use open_char and close_char.
 570         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 571         operands.  Set two_source_ops.
 572
 573 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 574
 575         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 576         instead of _raw_size.
 577
 578 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 579
 580         * ia64-gen.c (in_iclass): Handle more postinc st
 581         and ld variants.
 582         * ia64-asmtab.c: Rebuilt.
 583
 584 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 585
 586         * s390-opc.txt: Correct architecture mask for some opcodes.
 587         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 588         in the esa mode as well.
 589
 590 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 591
 592         * sh-dis.c (target_arch): Make unsigned.
 593         (print_insn_sh): Replace (most of) switch with a call to
 594         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 595         * sh-opc.h: Redefine architecture flags values.
 596         Add sh3-nommu architecture.
 597         Reorganise <arch>_up macros so they make more visual sense.
 598         (SH_MERGE_ARCH_SET): Define new macro.
 599         (SH_VALID_BASE_ARCH_SET): Likewise.
 600         (SH_VALID_MMU_ARCH_SET): Likewise.
 601         (SH_VALID_CO_ARCH_SET): Likewise.
 602         (SH_VALID_ARCH_SET): Likewise.
 603         (SH_MERGE_ARCH_SET_VALID): Likewise.
 604         (SH_ARCH_SET_HAS_FPU): Likewise.
 605         (SH_ARCH_SET_HAS_DSP): Likewise.
 606         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 607         (sh_get_arch_from_bfd_mach): Add prototype.
 608         (sh_get_arch_up_from_bfd_mach): Likewise.
 609         (sh_get_bfd_mach_from_arch_set): Likewise.
 610         (sh_merge_bfd_arc): Likewise.
 611
 612 2004-05-24  Peter Barada  <peter@the-baradas.com>
 613
 614         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 615         into new match_insn_m68k function.  Loop over canidate
 616         matches and select first that completely matches.
 617         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 618         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 619         to verify addressing for MAC/EMAC.
 620         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 621         reigster halves since 'fpu' and 'spl' look misleading.
 622         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 623         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 624         first, tighten up match masks.
 625         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 626         'size' from special case code in print_insn_m68k to
 627         determine decode size of insns.
 628
 629 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 630
 631         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 632         well as when -mpower4.
 633
 634 2004-05-13  Nick Clifton  <nickc@redhat.com>
 635
 636         * po/fr.po: Updated French translation.
 637
 638 2004-05-05  Peter Barada  <peter@the-baradas.com>
 639
 640         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 641         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 642         * m68k-op.c: Switch from ColdFire chips to core variants.
 643
 644 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 645
 646         PR 147.
 647         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 648
 649 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 650
 651         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 652         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 653
 654 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 655
 656         * sh-dis.c (print_insn_sh): Print the value in constant pool
 657         as a symbol if it looks like a symbol.
 658
 659 2004-04-22  Peter Barada <peter@the-baradas.com>
 660
 661         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 662         appropriate ColdFire architectures.
 663         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 664         mask addressing.
 665         Add EMAC instructions, fix MAC instructions. Remove
 666         macmw/macml/msacmw/msacml instructions since mask addressing now
 667         supported.
 668
 669 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 670
 671         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 672         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 673         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 674         macro.  Adjust all users.
 675
 676 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 677
 678         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 679         separately.
 680
 681 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 682
 683         * m32r-asm.c: Regenerate.
 684
 685 2004-03-29  Stan Shebs  <shebs@apple.com>
 686
 687         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 688         used.
 689
 690 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 691
 692         * aclocal.m4: Regenerate.
 693         * config.in: Regenerate.
 694         * configure: Regenerate.
 695         * po/POTFILES.in: Regenerate.
 696         * po/opcodes.pot: Regenerate.
 697
 698 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 699
 700         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 701         PPC_OPERANDS_GPR_0.
 702         * ppc-opc.c (RA0): Define.
 703         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 704         (RAOPT): Rename from RAO.  Update all uses.
 705         (powerpc_opcodes): Use RA0 as appropriate.
 706
 707 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 708
 709         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 710
 711 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 712
 713         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 714
 715 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 716
 717         * i386-dis.c (GRPPLOCK): Delete.
 718         (grps): Delete GRPPLOCK entry.
 719
 720 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 721
 722         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 723         (M, Mp): Use OP_M.
 724         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 725         (GRPPADLCK): Define.
 726         (dis386): Use NOP_Fixup on "nop".
 727         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 728         (twobyte_has_modrm): Set for 0xa7.
 729         (padlock_table): Delete.  Move to..
 730         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 731         and clflush.
 732         (print_insn): Revert PADLOCK_SPECIAL code.
 733         (OP_E): Delete sfence, lfence, mfence checks.
 734
 735 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 736
 737         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 738         (INVLPG_Fixup): New function.
 739         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 740
 741 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 742
 743         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 744         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 745         (padlock_table): New struct with PadLock instructions.
 746         (print_insn): Handle PADLOCK_SPECIAL.
 747
 748 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 749
 750         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 751         (OP_E): Twiddle clflush to sfence here.
 752
 753 2004-03-08  Nick Clifton  <nickc@redhat.com>
 754
 755         * po/de.po: Updated German translation.
 756
 757 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 758
 759         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 760         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 761         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 762         accordingly.
 763
 764 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 765
 766         * frv-asm.c: Regenerate.
 767         * frv-desc.c: Regenerate.
 768         * frv-desc.h: Regenerate.
 769         * frv-dis.c: Regenerate.
 770         * frv-ibld.c: Regenerate.
 771         * frv-opc.c: Regenerate.
 772         * frv-opc.h: Regenerate.
 773
 774 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 775
 776         * frv-desc.c, frv-opc.c: Regenerate.
 777
 778 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 779
 780         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 781
 782 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 783
 784         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 785         Also correct mistake in the comment.
 786
 787 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 788
 789         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 790         ensure that double registers have even numbers.
 791         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 792         that reserved instruction 0xfffd does not decode the same
 793         as 0xfdfd (ftrv).
 794         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 795         REG_N refers to a double register.
 796         Add REG_N_B01 nibble type and use it instead of REG_NM
 797         in ftrv.
 798         Adjust the bit patterns in a few comments.
 799
 800 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 801
 802         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 803
 804 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 805
 806         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 807
 808 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 809
 810         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 811
 812 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 813
 814         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 815         mtivor32, mtivor33, mtivor34.
 816
 817 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 818
 819         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 820
 821 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 822
 823         * arm-opc.h Maverick accumulator register opcode fixes.
 824
 825 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 826
 827         * m32r-dis.c: Regenerate.
 828
 829 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 830
 831         * sh-opc.h (sh_table): "fsrra", not "fssra".
 832
 833 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 834
 835         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 836         contraints.
 837
 838 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 839
 840         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 841
 842 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 843
 844         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 845         1.  Don't print scale factor on AT&T mode when index missing.
 846
 847 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 848
 849         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 850         when loaded into XR registers.
 851
 852 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 853
 854         * frv-desc.h: Regenerate.
 855         * frv-desc.c: Regenerate.
 856         * frv-opc.c: Regenerate.
 857
 858 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 859
 860         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 861
 862 2004-01-09  Paul Brook  <paul@codesourcery.com>
 863
 864         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 865         specific opcodes.
 866
 867 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 868
 869         * Makefile.am (libopcodes_la_DEPENDENCIES)
 870         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 871         comment about the problem.
 872         * Makefile.in: Regenerate.
 873
 874 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 875
 876         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 877         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 878         cut&paste errors in shifting/truncating numerical operands.
 879         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 880         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 881         (parse_uslo16): Likewise.
 882         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 883         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 884         (parse_s12): Likewise.
 885         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 886         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 887         (parse_uslo16): Likewise.
 888         (parse_uhi16): Parse gothi and gotfuncdeschi.
 889         (parse_d12): Parse got12 and gotfuncdesc12.
 890         (parse_s12): Likewise.
 891
 892 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 893
 894         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 895         instruction which looks similar to an 'rla' instruction.
 896
 897 For older changes see ChangeLog-0203
 898 \f
 899 Local Variables:
 900 mode: change-log
 901 left-margin: 8
 902 fill-column: 74
 903 version-control: never
 904 End: