opcodes/ChangeLog

   1 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
   2
   3         PR target/20667
   4         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
   5         available.
   6
   7 2016-10-07  Alan Modra  <amodra@gmail.com>
   8
   9         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
  10
  11 2016-10-06  Alan Modra  <amodra@gmail.com>
  12
  13         * aarch64-opc.c: Spell fall through comments consistently.
  14         * i386-dis.c: Likewise.
  15         * aarch64-dis.c: Add missing fall through comments.
  16         * aarch64-opc.c: Likewise.
  17         * arc-dis.c: Likewise.
  18         * arm-dis.c: Likewise.
  19         * i386-dis.c: Likewise.
  20         * m68k-dis.c: Likewise.
  21         * mep-asm.c: Likewise.
  22         * ns32k-dis.c: Likewise.
  23         * sh-dis.c: Likewise.
  24         * tic4x-dis.c: Likewise.
  25         * tic6x-dis.c: Likewise.
  26         * vax-dis.c: Likewise.
  27
  28 2016-10-06  Alan Modra  <amodra@gmail.com>
  29
  30         * arc-ext.c (create_map): Add missing break.
  31         * msp430-decode.opc (encode_as): Likewise.
  32         * msp430-decode.c: Regenerate.
  33
  34 2016-10-06  Alan Modra  <amodra@gmail.com>
  35
  36         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
  37         * crx-dis.c (print_insn_crx): Likewise.
  38
  39 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         PR binutils/20657
  42         * i386-dis.c (putop): Don't assign alt twice.
  43
  44 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
  45
  46         PR target/20553
  47         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
  48
  49 2016-09-29  Alan Modra  <amodra@gmail.com>
  50
  51         * ppc-opc.c (L): Make compulsory.
  52         (LOPT): New, optional form of L.
  53         (HTM_R): Define as LOPT.
  54         (L0, L1): Delete.
  55         (L32OPT): New, optional for 32-bit L.
  56         (L2OPT): New, 2-bit L for dcbf.
  57         (SVC_LEC): Update.
  58         (L2): Define.
  59         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
  60         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
  61         <dcbf>: Use L2OPT.
  62         <tlbiel, tlbie>: Use LOPT.
  63         <wclr, wclrall>: Use L2.
  64
  65 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
  66
  67         * Makefile.in: Regenerate.
  68         * configure: Likewise.
  69
  70 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
  71
  72         * arc-ext-tbl.h (EXTINSN2OPF): Define.
  73         (EXTINSN2OP): Use EXTINSN2OPF.
  74         (bspeekm, bspop, modapp): New extension instructions.
  75         * arc-opc.c (F_DNZ_ND): Define.
  76         (F_DNZ_D): Likewise.
  77         (F_SIZEB1): Changed.
  78         (C_DNZ_D): Define.
  79         (C_HARD): Changed.
  80         * arc-tbl.h (dbnz): New instruction.
  81         (prealloc): Allow it for ARC EM.
  82         (xbfu): Likewise.
  83
  84 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  85
  86         * aarch64-opc.c (print_immediate_offset_address): Print spaces
  87         after commas in addresses.
  88         (aarch64_print_operand): Likewise.
  89
  90 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  91
  92         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
  93         rather than "should be" or "expected to be" in error messages.
  94
  95 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  96
  97         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
  98         (print_mnemonic_name): ...here.
  99         (print_comment): New function.
 100         (print_aarch64_insn): Call it.
 101         * aarch64-opc.c (aarch64_conds): Add SVE names.
 102         (aarch64_print_operand): Print alternative condition names in
 103         a comment.
 104
 105 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 106
 107         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 108         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 109         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 110         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 111         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 112         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 113         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 114         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 115         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 116         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 117         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 118         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 119         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 120         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 121         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 122         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 123         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 124         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 125         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 126         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 127         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 128         (aarch64_feature_sve): New variable.
 129         (SVE): New macro.
 130         (_SVE_INSN): Likewise.
 131         (aarch64_opcode_table): Add SVE instructions.
 132         * aarch64-opc.h (extract_fields): Declare.
 133         * aarch64-opc-2.c: Regenerate.
 134         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 135         * aarch64-asm-2.c: Regenerate.
 136         * aarch64-dis.c (extract_fields): Make global.
 137         (do_misc_decoding): Handle the new SVE aarch64_ops.
 138         * aarch64-dis-2.c: Regenerate.
 139
 140 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 141
 142         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 143         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 144         aarch64_field_kinds.
 145         * aarch64-opc.c (fields): Add corresponding entries.
 146         * aarch64-asm.c (aarch64_get_variant): New function.
 147         (aarch64_encode_variant_using_iclass): Likewise.
 148         (aarch64_opcode_encode): Call it.
 149         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 150         (aarch64_opcode_decode): Call it.
 151
 152 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 153
 154         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 155         and FP register operands.
 156         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 157         (FLD_SVE_Vn): New aarch64_field_kinds.
 158         * aarch64-opc.c (fields): Add corresponding entries.
 159         (aarch64_print_operand): Handle the new SVE core and FP register
 160         operands.
 161         * aarch64-opc-2.c: Regenerate.
 162         * aarch64-asm-2.c: Likewise.
 163         * aarch64-dis-2.c: Likewise.
 164
 165 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 166
 167         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 168         immediate operands.
 169         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 170         * aarch64-opc.c (fields): Add corresponding entry.
 171         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 172         operands.
 173         (aarch64_print_operand): Likewise.
 174         * aarch64-opc-2.c: Regenerate.
 175         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 176         (ins_sve_float_zero_one): New inserters.
 177         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 178         (aarch64_ins_sve_float_half_two): Likewise.
 179         (aarch64_ins_sve_float_zero_one): Likewise.
 180         * aarch64-asm-2.c: Regenerate.
 181         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 182         (ext_sve_float_zero_one): New extractors.
 183         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 184         (aarch64_ext_sve_float_half_two): Likewise.
 185         (aarch64_ext_sve_float_zero_one): Likewise.
 186         * aarch64-dis-2.c: Regenerate.
 187
 188 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 189
 190         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 191         integer immediate operands.
 192         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 193         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 194         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 195         * aarch64-opc.c (fields): Add corresponding entries.
 196         (operand_general_constraint_met_p): Handle the new SVE integer
 197         immediate operands.
 198         (aarch64_print_operand): Likewise.
 199         (aarch64_sve_dupm_mov_immediate_p): New function.
 200         * aarch64-opc-2.c: Regenerate.
 201         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 202         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 203         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 204         (aarch64_ins_limm): ...here.
 205         (aarch64_ins_inv_limm): New function.
 206         (aarch64_ins_sve_aimm): Likewise.
 207         (aarch64_ins_sve_asimm): Likewise.
 208         (aarch64_ins_sve_limm_mov): Likewise.
 209         (aarch64_ins_sve_shlimm): Likewise.
 210         (aarch64_ins_sve_shrimm): Likewise.
 211         * aarch64-asm-2.c: Regenerate.
 212         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 213         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 214         * aarch64-dis.c (decode_limm): New function, split out from...
 215         (aarch64_ext_limm): ...here.
 216         (aarch64_ext_inv_limm): New function.
 217         (decode_sve_aimm): Likewise.
 218         (aarch64_ext_sve_aimm): Likewise.
 219         (aarch64_ext_sve_asimm): Likewise.
 220         (aarch64_ext_sve_limm_mov): Likewise.
 221         (aarch64_top_bit): Likewise.
 222         (aarch64_ext_sve_shlimm): Likewise.
 223         (aarch64_ext_sve_shrimm): Likewise.
 224         * aarch64-dis-2.c: Regenerate.
 225
 226 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 227
 228         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 229         operands.
 230         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 231         the AARCH64_MOD_MUL_VL entry.
 232         (value_aligned_p): Cope with non-power-of-two alignments.
 233         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 234         (print_immediate_offset_address): Likewise.
 235         (aarch64_print_operand): Likewise.
 236         * aarch64-opc-2.c: Regenerate.
 237         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 238         (ins_sve_addr_ri_s9xvl): New inserters.
 239         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 240         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 241         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 242         * aarch64-asm-2.c: Regenerate.
 243         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 244         (ext_sve_addr_ri_s9xvl): New extractors.
 245         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 246         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 247         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 248         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 249         * aarch64-dis-2.c: Regenerate.
 250
 251 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 252
 253         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 254         address operands.
 255         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 256         (FLD_SVE_xs_22): New aarch64_field_kinds.
 257         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 258         (get_operand_specific_data): New function.
 259         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 260         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 261         (operand_general_constraint_met_p): Handle the new SVE address
 262         operands.
 263         (sve_reg): New array.
 264         (get_addr_sve_reg_name): New function.
 265         (aarch64_print_operand): Handle the new SVE address operands.
 266         * aarch64-opc-2.c: Regenerate.
 267         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 268         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 269         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 270         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 271         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 272         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 273         (aarch64_ins_sve_addr_zi_u5): Likewise.
 274         (aarch64_ins_sve_addr_zz): Likewise.
 275         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 276         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 277         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 278         * aarch64-asm-2.c: Regenerate.
 279         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 280         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 281         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 282         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 283         (aarch64_ext_sve_addr_ri_u6): Likewise.
 284         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 285         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 286         (aarch64_ext_sve_addr_zi_u5): Likewise.
 287         (aarch64_ext_sve_addr_zz): Likewise.
 288         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 289         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 290         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 291         * aarch64-dis-2.c: Regenerate.
 292
 293 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 294
 295         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 296         AARCH64_OPND_SVE_PATTERN_SCALED.
 297         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 298         * aarch64-opc.c (fields): Add a corresponding entry.
 299         (set_multiplier_out_of_range_error): New function.
 300         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 301         (operand_general_constraint_met_p): Handle
 302         AARCH64_OPND_SVE_PATTERN_SCALED.
 303         (print_register_offset_address): Use PRIi64 to print the
 304         shift amount.
 305         (aarch64_print_operand): Likewise.  Handle
 306         AARCH64_OPND_SVE_PATTERN_SCALED.
 307         * aarch64-opc-2.c: Regenerate.
 308         * aarch64-asm.h (ins_sve_scale): New inserter.
 309         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 310         * aarch64-asm-2.c: Regenerate.
 311         * aarch64-dis.h (ext_sve_scale): New inserter.
 312         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 313         * aarch64-dis-2.c: Regenerate.
 314
 315 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 316
 317         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 318         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 319         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 320         (FLD_SVE_prfop): Likewise.
 321         * aarch64-opc.c: Include libiberty.h.
 322         (aarch64_sve_pattern_array): New variable.
 323         (aarch64_sve_prfop_array): Likewise.
 324         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 325         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 326         AARCH64_OPND_SVE_PRFOP.
 327         * aarch64-asm-2.c: Regenerate.
 328         * aarch64-dis-2.c: Likewise.
 329         * aarch64-opc-2.c: Likewise.
 330
 331 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 332
 333         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 334         AARCH64_OPND_QLF_P_[ZM].
 335         (aarch64_print_operand): Print /z and /m where appropriate.
 336
 337 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 338
 339         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 340         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 341         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 342         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 343         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 344         * aarch64-opc.c (fields): Add corresponding entries here.
 345         (operand_general_constraint_met_p): Check that SVE register lists
 346         have the correct length.  Check the ranges of SVE index registers.
 347         Check for cases where p8-p15 are used in 3-bit predicate fields.
 348         (aarch64_print_operand): Handle the new SVE operands.
 349         * aarch64-opc-2.c: Regenerate.
 350         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 351         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 352         (aarch64_ins_sve_reglist): Likewise.
 353         * aarch64-asm-2.c: Regenerate.
 354         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 355         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 356         (aarch64_ext_sve_reglist): Likewise.
 357         * aarch64-dis-2.c: Regenerate.
 358
 359 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 360
 361         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 362         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 363         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 364         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 365         tied operands.
 366
 367 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 368
 369         * aarch64-opc.c (get_offset_int_reg_name): New function.
 370         (print_immediate_offset_address): Likewise.
 371         (print_register_offset_address): Take the base and offset
 372         registers as parameters.
 373         (aarch64_print_operand): Update caller accordingly.  Use
 374         print_immediate_offset_address.
 375
 376 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 377
 378         * aarch64-opc.c (BANK): New macro.
 379         (R32, R64): Take a register number as argument
 380         (int_reg): Use BANK.
 381
 382 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 383
 384         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 385         (aarch64_print_operand): Update accordingly.
 386
 387 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 388
 389         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 390         for FPIMM.
 391         * aarch64-asm.h (ins_fpimm): New inserter.
 392         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 393         * aarch64-asm-2.c: Regenerate.
 394         * aarch64-dis.h (ext_fpimm): New extractor.
 395         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 396         (aarch64_ext_fpimm): New function.
 397         * aarch64-dis-2.c: Regenerate.
 398
 399 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 400
 401         * aarch64-asm.c: Include libiberty.h.
 402         (insert_fields): New function.
 403         (aarch64_ins_imm): Use it.
 404         * aarch64-dis.c (extract_fields): New function.
 405         (aarch64_ext_imm): Use it.
 406
 407 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 408
 409         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 410         with an esize parameter.
 411         (operand_general_constraint_met_p): Update accordingly.
 412         Fix misindented code.
 413         * aarch64-asm.c (aarch64_ins_limm): Update call to
 414         aarch64_logical_immediate_p.
 415
 416 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 417
 418         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 419
 420 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 421
 422         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 423
 424 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 425
 426         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 427
 428 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 429
 430         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 431         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 432         xor3>: Delete mnemonics.
 433         <cp_abort>: Rename mnemonic from ...
 434         <cpabort>: ...to this.
 435         <setb>: Change to a X form instruction.
 436         <sync>: Change to 1 operand form.
 437         <copy>: Delete mnemonic.
 438         <copy_first>: Rename mnemonic from ...
 439         <copy>: ...to this.
 440         <paste, paste.>: Delete mnemonics.
 441         <paste_last>: Rename mnemonic from ...
 442         <paste.>: ...to this.
 443
 444 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 445
 446         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 447
 448 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 449
 450         * s390-mkopc.c (main): Support alternate arch strings.
 451
 452 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 453
 454         * s390-opc.txt: Fix kmctr instruction type.
 455
 456 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 457
 458         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 459         * i386-init.h: Regenerated.
 460
 461 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 462
 463         * opcodes/arc-dis.c (print_insn_arc): Changed.
 464
 465 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 466
 467         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 468         camellia_fl.
 469
 470 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 471
 472         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 473         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 474         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 475
 476 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 477
 478         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 479         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 480         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 481         PREFIX_MOD_3_0FAE_REG_4.
 482         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 483         PREFIX_MOD_3_0FAE_REG_4.
 484         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 485         (cpu_flags): Add CpuPTWRITE.
 486         * i386-opc.h (CpuPTWRITE): New.
 487         (i386_cpu_flags): Add cpuptwrite.
 488         * i386-opc.tbl: Add ptwrite instruction.
 489         * i386-init.h: Regenerated.
 490         * i386-tbl.h: Likewise.
 491
 492 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 493
 494         * arc-dis.h: Wrap around in extern "C".
 495
 496 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 497
 498         * aarch64-tbl.h (V8_2_INSN): New macro.
 499         (aarch64_opcode_table): Use it.
 500
 501 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 502
 503         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 504         CORE_INSN, __FP_INSN and SIMD_INSN.
 505
 506 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 507
 508         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 509         (aarch64_opcode_table): Update uses accordingly.
 510
 511 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 512         Kwok Cheung Yeung  <kcy@codesourcery.com>
 513
 514         opcodes/
 515         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 516         'e_cmplwi' to 'e_cmpli' instead.
 517         (OPVUPRT, OPVUPRT_MASK): Define.
 518         (powerpc_opcodes): Add E200Z4 insns.
 519         (vle_opcodes): Add context save/restore insns.
 520
 521 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 522
 523         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 524         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 525         "j".
 526
 527 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 528
 529         * arc-nps400-tbl.h: Change block comments to GNU format.
 530         * arc-dis.c: Add new globals addrtypenames,
 531         addrtypenames_max, and addtypeunknown.
 532         (get_addrtype): New function.
 533         (print_insn_arc): Print colons and address types when
 534         required.
 535         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 536         define insert and extract functions for all address types.
 537         (arc_operands): Add operands for colon and all address
 538         types.
 539         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 540         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 541         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 542         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 543         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 544         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 545
 546 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 547
 548         * configure: Regenerated.
 549
 550 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 551
 552         * arc-dis.c (skipclass): New structure.
 553         (decodelist): New variable.
 554         (is_compatible_p): New function.
 555         (new_element): Likewise.
 556         (skip_class_p): Likewise.
 557         (find_format_from_table): Use skip_class_p function.
 558         (find_format): Decode first the extension instructions.
 559         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 560         e_flags.
 561         (parse_option): New function.
 562         (parse_disassembler_options): Likewise.
 563         (print_arc_disassembler_options): Likewise.
 564         (print_insn_arc): Use parse_disassembler_options function.  Proper
 565         select ARCv2 cpu variant.
 566         * disassemble.c (disassembler_usage): Add ARC disassembler
 567         options.
 568
 569 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 570
 571         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 572         annotation from the "nal" entry and reorder it beyond "bltzal".
 573
 574 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 575
 576         * sparc-opc.c (ldtxa): New macro.
 577         (sparc_opcodes): Use the macro defined above to add entries for
 578         the LDTXA instructions.
 579         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 580         instruction.
 581
 582 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 583
 584         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 585         and "jmpc".
 586
 587 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 590         (movzb): Adjust to cover all permitted suffixes.
 591         (movzw): New.
 592         * i386-tbl.h: Re-generate.
 593
 594 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 595
 596         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 597         (lgdt): Remove Tbyte from non-64-bit variant.
 598         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 599         xsaves64, xsavec64): Remove Disp16.
 600         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 601         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 602         64-bit variants.
 603         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 604         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 605         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 606         64-bit variants.
 607         * i386-tbl.h: Re-generate.
 608
 609 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 612         * i386-tbl.h: Re-generate.
 613
 614 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 615
 616         * arm-dis.c (print_insn): Fix typo in comment.
 617
 618 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 619
 620         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 621         range of ldst_elemlist operands.
 622         (print_register_list): Use PRIi64 to print the index.
 623         (aarch64_print_operand): Likewise.
 624
 625 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 626
 627         * mcore-opc.h: Remove sentinal.
 628         * mcore-dis.c (print_insn_mcore): Adjust.
 629
 630 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 631
 632         * arc-opc.c: Correct description of availability of NPS400
 633         features.
 634
 635 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 636
 637         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 638         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 639         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 640         xor3>: New mnemonics.
 641         <setb>: Change to a VX form instruction.
 642         (insert_sh6): Add support for rldixor.
 643         (extract_sh6): Likewise.
 644
 645 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 646
 647         * arc-ext.h: Wrap in extern C.
 648
 649 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 650
 651         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 652         Use same method for determining instruction length on ARC700 and
 653         NPS-400.
 654         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 655         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 656         with the NPS400 subclass.
 657         * arc-opc.c: Likewise.
 658
 659 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 660
 661         * sparc-opc.c (rdasr): New macro.
 662         (wrasr): Likewise.
 663         (rdpr): Likewise.
 664         (wrpr): Likewise.
 665         (rdhpr): Likewise.
 666         (wrhpr): Likewise.
 667         (sparc_opcodes): Use the macros above to fix and expand the
 668         definition of read/write instructions from/to
 669         asr/privileged/hyperprivileged instructions.
 670         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 671         %hva_mask_nz.  Prefer softint_set and softint_clear over
 672         set_softint and clear_softint.
 673         (print_insn_sparc): Support %ver in Rd.
 674
 675 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 676
 677         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 678         architecture according to the hardware capabilities they require.
 679
 680 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 681
 682         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 683         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 684         bfd_mach_sparc_v9{c,d,e,v,m}.
 685         * sparc-opc.c (MASK_V9C): Define.
 686         (MASK_V9D): Likewise.
 687         (MASK_V9E): Likewise.
 688         (MASK_V9V): Likewise.
 689         (MASK_V9M): Likewise.
 690         (v6): Add MASK_V9{C,D,E,V,M}.
 691         (v6notlet): Likewise.
 692         (v7): Likewise.
 693         (v8): Likewise.
 694         (v9): Likewise.
 695         (v9andleon): Likewise.
 696         (v9a): Likewise.
 697         (v9b): Likewise.
 698         (v9c): Define.
 699         (v9d): Likewise.
 700         (v9e): Likewise.
 701         (v9v): Likewise.
 702         (v9m): Likewise.
 703         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 704
 705 2016-06-15  Nick Clifton  <nickc@redhat.com>
 706
 707         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 708         constants to match expected behaviour.
 709         (nds32_parse_opcode): Likewise.  Also for whitespace.
 710
 711 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 712
 713         * arc-opc.c (extract_rhv1): Extract value from insn.
 714
 715 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 716
 717         * arc-nps400-tbl.h: Add ldbit instruction.
 718         * arc-opc.c: Add flag classes required for ldbit.
 719
 720 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 721
 722         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 723         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 724         support the above instructions.
 725
 726 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 727
 728         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 729         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 730         csma, cbba, zncv, and hofs.
 731         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 732         support the above instructions.
 733
 734 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 735
 736         * arc-nps400-tbl.h: Add andab and orab instructions.
 737
 738 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 739
 740         * arc-nps400-tbl.h: Add addl-like instructions.
 741
 742 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 743
 744         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 745
 746 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 747
 748         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 749         instructions.
 750
 751 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 752
 753         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 754         variable.
 755         (init_disasm): Handle new command line option "insnlength".
 756         (print_s390_disassembler_options): Mention new option in help
 757         output.
 758         (print_insn_s390): Use the encoded insn length when dumping
 759         unknown instructions.
 760
 761 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 762
 763         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 764          to the address and set as symbol address for LDS/ STS immediate operands.
 765
 766 2016-06-07  Alan Modra  <amodra@gmail.com>
 767
 768         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 769         cpu for "vle" to e500.
 770         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 771         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 772         (PPCNONE): Delete, substitute throughout.
 773         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 774         except for major opcode 4 and 31.
 775         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 776
 777 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 778
 779         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 780         ARM_EXT_RAS in relevant entries.
 781
 782 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 783
 784         PR binutils/20196
 785         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 786         opcodes for E6500.
 787
 788 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 789
 790         PR binutis/18386
 791         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 792         (indir_v_mode): New.
 793         Add comments for '&'.
 794         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 795         (putop): Handle '&'.
 796         (intel_operand_size): Handle indir_v_mode.
 797         (OP_E_register): Likewise.
 798         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 799         64-bit indirect call/jmp for AMD64.
 800         * i386-tbl.h: Regenerated
 801
 802 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 803
 804         * arc-dis.c (struct arc_operand_iterator): New structure.
 805         (find_format_from_table): All the old content from find_format,
 806         with some minor adjustments, and parameter renaming.
 807         (find_format_long_instructions): New function.
 808         (find_format): Rewritten.
 809         (arc_insn_length): Add LSB parameter.
 810         (extract_operand_value): New function.
 811         (operand_iterator_next): New function.
 812         (print_insn_arc): Use new functions to find opcode, and iterator
 813         over operands.
 814         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 815         (extract_nps_3bit_dst_short): New function.
 816         (insert_nps_3bit_src2_short): New function.
 817         (extract_nps_3bit_src2_short): New function.
 818         (insert_nps_bitop1_size): New function.
 819         (extract_nps_bitop1_size): New function.
 820         (insert_nps_bitop2_size): New function.
 821         (extract_nps_bitop2_size): New function.
 822         (insert_nps_bitop_mod4_msb): New function.
 823         (extract_nps_bitop_mod4_msb): New function.
 824         (insert_nps_bitop_mod4_lsb): New function.
 825         (extract_nps_bitop_mod4_lsb): New function.
 826         (insert_nps_bitop_dst_pos3_pos4): New function.
 827         (extract_nps_bitop_dst_pos3_pos4): New function.
 828         (insert_nps_bitop_ins_ext): New function.
 829         (extract_nps_bitop_ins_ext): New function.
 830         (arc_operands): Add new operands.
 831         (arc_long_opcodes): New global array.
 832         (arc_num_long_opcodes): New global.
 833         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 834
 835 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 836
 837         * nds32-asm.h: Add extern "C".
 838         * sh-opc.h: Likewise.
 839
 840 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 841
 842         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 843         0,b,limm to the rflt instruction.
 844
 845 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 846
 847         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 848         constant.
 849
 850 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 851
 852         PR gas/20145
 853         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 854         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 855         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 856         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 857         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 858         * i386-init.h: Regenerated.
 859
 860 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 861
 862         PR gas/20145
 863         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 864         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 865         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 866         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 867         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 868         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 869         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 870         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 871         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 872         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 873         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 874         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 875         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 876         CpuRegMask for AVX512.
 877         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 878         and CpuRegMask.
 879         (set_bitfield_from_cpu_flag_init): New function.
 880         (set_bitfield): Remove const on f.  Call
 881         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 882         * i386-opc.h (CpuRegMMX): New.
 883         (CpuRegXMM): Likewise.
 884         (CpuRegYMM): Likewise.
 885         (CpuRegZMM): Likewise.
 886         (CpuRegMask): Likewise.
 887         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 888         and cpuregmask.
 889         * i386-init.h: Regenerated.
 890         * i386-tbl.h: Likewise.
 891
 892 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 893
 894         PR gas/20154
 895         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 896         (opcode_modifiers): Add AMD64 and Intel64.
 897         (main): Properly verify CpuMax.
 898         * i386-opc.h (CpuAMD64): Removed.
 899         (CpuIntel64): Likewise.
 900         (CpuMax): Set to CpuNo64.
 901         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 902         (AMD64): New.
 903         (Intel64): Likewise.
 904         (i386_opcode_modifier): Add amd64 and intel64.
 905         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 906         on call and jmp.
 907         * i386-init.h: Regenerated.
 908         * i386-tbl.h: Likewise.
 909
 910 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 911
 912         PR gas/20154
 913         * i386-gen.c (main): Fail if CpuMax is incorrect.
 914         * i386-opc.h (CpuMax): Set to CpuIntel64.
 915         * i386-tbl.h: Regenerated.
 916
 917 2016-05-27  Nick Clifton  <nickc@redhat.com>
 918
 919         PR target/20150
 920         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 921         (msp430dis_opcode_unsigned): New function.
 922         (msp430dis_opcode_signed): New function.
 923         (msp430_singleoperand): Use the new opcode reading functions.
 924         Only disassenmble bytes if they were successfully read.
 925         (msp430_doubleoperand): Likewise.
 926         (msp430_branchinstr): Likewise.
 927         (msp430x_callx_instr): Likewise.
 928         (print_insn_msp430): Check that it is safe to read bytes before
 929         attempting disassembly.  Use the new opcode reading functions.
 930
 931 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 932
 933         * ppc-opc.c (CY): New define.  Document it.
 934         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 935
 936 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 937
 938         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 939         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 940         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 941         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 942         CPU_ANY_AVX_FLAGS.
 943         * i386-init.h: Regenerated.
 944
 945 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 946
 947         PR gas/20141
 948         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 949         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 950         * i386-init.h: Regenerated.
 951
 952 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 953
 954         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 955         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 956         * i386-init.h: Regenerated.
 957
 958 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 959
 960         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 961         information.
 962         (print_insn_arc): Set insn_type information.
 963         * arc-opc.c (C_CC): Add F_CLASS_COND.
 964         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 965         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 966         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 967         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 968         (brne, brne_s, jeq_s, jne_s): Likewise.
 969
 970 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 971
 972         * arc-tbl.h (neg): New instruction variant.
 973
 974 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 975
 976         * arc-dis.c (find_format, find_format, get_auxreg)
 977         (print_insn_arc): Changed.
 978         * arc-ext.h (INSERT_XOP): Likewise.
 979
 980 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 981
 982         * tic54x-dis.c (sprint_mmr): Adjust.
 983         * tic54x-opc.c: Likewise.
 984
 985 2016-05-19  Alan Modra  <amodra@gmail.com>
 986
 987         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 988
 989 2016-05-19  Alan Modra  <amodra@gmail.com>
 990
 991         * ppc-opc.c: Formatting.
 992         (NSISIGNOPT): Define.
 993         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 994
 995 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 996
 997         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 998         replacing references to `micromips_ase' throughout.
 999         (_print_insn_mips): Don't use file-level microMIPS annotation to
1000         determine the disassembly mode with the symbol table.
1001
1002 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1003
1004         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1005
1006 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1007
1008         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1009         mips64r6.
1010         * mips-opc.c (D34): New macro.
1011         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1012
1013 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1014
1015         * i386-dis.c (prefix_table): Add RDPID instruction.
1016         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1017         (cpu_flags): Add RDPID bitfield.
1018         * i386-opc.h (enum): Add RDPID element.
1019         (i386_cpu_flags): Add RDPID field.
1020         * i386-opc.tbl: Add RDPID instruction.
1021         * i386-init.h: Regenerate.
1022         * i386-tbl.h: Regenerate.
1023
1024 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1025
1026         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1027         branch type of a symbol.
1028         (print_insn): Likewise.
1029
1030 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1031
1032         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1033         Mainline Security Extensions instructions.
1034         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1035         Extensions instructions.
1036         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1037         instructions.
1038         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1039         special registers.
1040
1041 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1042
1043         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1044
1045 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1046
1047         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1048         (arcExtMap_genOpcode): Likewise.
1049         * arc-opc.c (arg_32bit_rc): Define new variable.
1050         (arg_32bit_u6): Likewise.
1051         (arg_32bit_limm): Likewise.
1052
1053 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1054
1055         * aarch64-gen.c (VERIFIER): Define.
1056         * aarch64-opc.c (VERIFIER): Define.
1057         (verify_ldpsw): Use static linkage.
1058         * aarch64-opc.h (verify_ldpsw): Remove.
1059         * aarch64-tbl.h: Use VERIFIER for verifiers.
1060
1061 2016-04-28  Nick Clifton  <nickc@redhat.com>
1062
1063         PR target/19722
1064         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1065         * aarch64-opc.c (verify_ldpsw): New function.
1066         * aarch64-opc.h (verify_ldpsw): New prototype.
1067         * aarch64-tbl.h: Add initialiser for verifier field.
1068         (LDPSW): Set verifier to verify_ldpsw.
1069
1070 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1071
1072         PR binutils/19983
1073         PR binutils/19984
1074         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1075         smaller than address size.
1076
1077 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1078
1079         * alpha-dis.c: Regenerate.
1080         * crx-dis.c: Likewise.
1081         * disassemble.c: Likewise.
1082         * epiphany-opc.c: Likewise.
1083         * fr30-opc.c: Likewise.
1084         * frv-opc.c: Likewise.
1085         * ip2k-opc.c: Likewise.
1086         * iq2000-opc.c: Likewise.
1087         * lm32-opc.c: Likewise.
1088         * lm32-opinst.c: Likewise.
1089         * m32c-opc.c: Likewise.
1090         * m32r-opc.c: Likewise.
1091         * m32r-opinst.c: Likewise.
1092         * mep-opc.c: Likewise.
1093         * mt-opc.c: Likewise.
1094         * or1k-opc.c: Likewise.
1095         * or1k-opinst.c: Likewise.
1096         * tic80-opc.c: Likewise.
1097         * xc16x-opc.c: Likewise.
1098         * xstormy16-opc.c: Likewise.
1099
1100 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1101
1102         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1103         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1104         calcsd, and calcxd instructions.
1105         * arc-opc.c (insert_nps_bitop_size): Delete.
1106         (extract_nps_bitop_size): Delete.
1107         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1108         (extract_nps_qcmp_m3): Define.
1109         (extract_nps_qcmp_m2): Define.
1110         (extract_nps_qcmp_m1): Define.
1111         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1112         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1113         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1114         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1115         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1116         NPS_QCMP_M3.
1117
1118 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1119
1120         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1121
1122 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1123
1124         * Makefile.in: Regenerated with automake 1.11.6.
1125         * aclocal.m4: Likewise.
1126
1127 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1128
1129         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1130         instructions.
1131         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1132         (extract_nps_cmem_uimm16): New function.
1133         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1134
1135 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1136
1137         * arc-dis.c (arc_insn_length): New function.
1138         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1139         (find_format): Change insnLen parameter to unsigned.
1140
1141 2016-04-13  Nick Clifton  <nickc@redhat.com>
1142
1143         PR target/19937
1144         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1145         the LD.B and LD.BU instructions.
1146
1147 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1148
1149         * arc-dis.c (find_format): Check for extension flags.
1150         (print_flags): New function.
1151         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1152         .extAuxRegister.
1153         * arc-ext.c (arcExtMap_coreRegName): Use
1154         LAST_EXTENSION_CORE_REGISTER.
1155         (arcExtMap_coreReadWrite): Likewise.
1156         (dump_ARC_extmap): Update printing.
1157         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1158         (arc_aux_regs): Add cpu field.
1159         * arc-regs.h: Add cpu field, lower case name aux registers.
1160
1161 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1162
1163         * arc-tbl.h: Add rtsc, sleep with no arguments.
1164
1165 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1166
1167         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1168         Initialize.
1169         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1170         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1171         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1172         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1173         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1174         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1175         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1176         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1177         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1178         (arc_opcode arc_opcodes): Null terminate the array.
1179         (arc_num_opcodes): Remove.
1180         * arc-ext.h (INSERT_XOP): Define.
1181         (extInstruction_t): Likewise.
1182         (arcExtMap_instName): Delete.
1183         (arcExtMap_insn): New function.
1184         (arcExtMap_genOpcode): Likewise.
1185         * arc-ext.c (ExtInstruction): Remove.
1186         (create_map): Zero initialize instruction fields.
1187         (arcExtMap_instName): Remove.
1188         (arcExtMap_insn): New function.
1189         (dump_ARC_extmap): More info while debuging.
1190         (arcExtMap_genOpcode): New function.
1191         * arc-dis.c (find_format): New function.
1192         (print_insn_arc): Use find_format.
1193         (arc_get_disassembler): Enable dump_ARC_extmap only when
1194         debugging.
1195
1196 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1197
1198         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1199         instruction bits out.
1200
1201 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1202
1203         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1204         * arc-opc.c (arc_flag_operands): Add new flags.
1205         (arc_flag_classes): Add new classes.
1206
1207 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1208
1209         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1210
1211 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1212
1213         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1214         encode1, rflt, crc16, and crc32 instructions.
1215         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1216         (arc_flag_classes): Add C_NPS_R.
1217         (insert_nps_bitop_size_2b): New function.
1218         (extract_nps_bitop_size_2b): Likewise.
1219         (insert_nps_bitop_uimm8): Likewise.
1220         (extract_nps_bitop_uimm8): Likewise.
1221         (arc_operands): Add new operand entries.
1222
1223 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1224
1225         * arc-regs.h: Add a new subclass field.  Add double assist
1226         accumulator register values.
1227         * arc-tbl.h: Use DPA subclass to mark the double assist
1228         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1229         * arc-opc.c (RSP): Define instead of SP.
1230         (arc_aux_regs): Add the subclass field.
1231
1232 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1233
1234         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1235
1236 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1237
1238         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1239         NPS_R_SRC1.
1240
1241 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1242
1243         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1244         issues.  No functional changes.
1245
1246 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1247
1248         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1249         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1250         (RTT): Remove duplicate.
1251         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1252         (PCT_CONFIG*): Remove.
1253         (D1L, D1H, D2H, D2L): Define.
1254
1255 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1256
1257         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1258
1259 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1260
1261         * arc-tbl.h (invld07): Remove.
1262         * arc-ext-tbl.h: New file.
1263         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1264         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1265
1266 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1267
1268         Fix -Wstack-usage warnings.
1269         * aarch64-dis.c (print_operands): Substitute size.
1270         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1271
1272 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1273
1274         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1275         to get a proper diagnostic when an invalid ASR register is used.
1276
1277 2016-03-22  Nick Clifton  <nickc@redhat.com>
1278
1279         * configure: Regenerate.
1280
1281 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1282
1283         * arc-nps400-tbl.h: New file.
1284         * arc-opc.c: Add top level comment.
1285         (insert_nps_3bit_dst): New function.
1286         (extract_nps_3bit_dst): New function.
1287         (insert_nps_3bit_src2): New function.
1288         (extract_nps_3bit_src2): New function.
1289         (insert_nps_bitop_size): New function.
1290         (extract_nps_bitop_size): New function.
1291         (arc_flag_operands): Add nps400 entries.
1292         (arc_flag_classes): Add nps400 entries.
1293         (arc_operands): Add nps400 entries.
1294         (arc_opcodes): Add nps400 include.
1295
1296 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1297
1298         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1299         the new class enum values.
1300
1301 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1302
1303         * arc-dis.c (print_insn_arc): Handle nps400.
1304
1305 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1306
1307         * arc-opc.c (BASE): Delete.
1308
1309 2016-03-18  Nick Clifton  <nickc@redhat.com>
1310
1311         PR target/19721
1312         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1313         of MOV insn that aliases an ORR insn.
1314
1315 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1316
1317         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1318
1319 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1320
1321         * mcore-opc.h: Add const qualifiers.
1322         * microblaze-opc.h (struct op_code_struct): Likewise.
1323         * sh-opc.h: Likewise.
1324         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1325         (tic4x_print_op): Likewise.
1326
1327 2016-03-02  Alan Modra  <amodra@gmail.com>
1328
1329         * or1k-desc.h: Regenerate.
1330         * fr30-ibld.c: Regenerate.
1331         * rl78-decode.c: Regenerate.
1332
1333 2016-03-01  Nick Clifton  <nickc@redhat.com>
1334
1335         PR target/19747
1336         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1337
1338 2016-02-24  Renlin Li  <renlin.li@arm.com>
1339
1340         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1341         (print_insn_coprocessor): Support fp16 instructions.
1342
1343 2016-02-24  Renlin Li  <renlin.li@arm.com>
1344
1345         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1346         vminnm, vrint(mpna).
1347
1348 2016-02-24  Renlin Li  <renlin.li@arm.com>
1349
1350         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1351         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1352
1353 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1354
1355         * i386-dis.c (print_insn): Parenthesize expression to prevent
1356         truncated addresses.
1357         (OP_J): Likewise.
1358
1359 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1360             Janek van Oirschot  <jvanoirs@synopsys.com>
1361
1362         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1363         variable.
1364
1365 2016-02-04  Nick Clifton  <nickc@redhat.com>
1366
1367         PR target/19561
1368         * msp430-dis.c (print_insn_msp430): Add a special case for
1369         decoding an RRC instruction with the ZC bit set in the extension
1370         word.
1371
1372 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1373
1374         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1375         * epiphany-ibld.c: Regenerate.
1376         * fr30-ibld.c: Regenerate.
1377         * frv-ibld.c: Regenerate.
1378         * ip2k-ibld.c: Regenerate.
1379         * iq2000-ibld.c: Regenerate.
1380         * lm32-ibld.c: Regenerate.
1381         * m32c-ibld.c: Regenerate.
1382         * m32r-ibld.c: Regenerate.
1383         * mep-ibld.c: Regenerate.
1384         * mt-ibld.c: Regenerate.
1385         * or1k-ibld.c: Regenerate.
1386         * xc16x-ibld.c: Regenerate.
1387         * xstormy16-ibld.c: Regenerate.
1388
1389 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1390
1391         * epiphany-dis.c: Regenerated from latest cpu files.
1392
1393 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1394
1395         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1396         test bit.
1397
1398 2016-01-25  Renlin Li  <renlin.li@arm.com>
1399
1400         * arm-dis.c (mapping_symbol_for_insn): New function.
1401         (find_ifthen_state): Call mapping_symbol_for_insn().
1402
1403 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1404
1405         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1406         of MSR UAO immediate operand.
1407
1408 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1409
1410         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1411         instruction support.
1412
1413 2016-01-17  Alan Modra  <amodra@gmail.com>
1414
1415         * configure: Regenerate.
1416
1417 2016-01-14  Nick Clifton  <nickc@redhat.com>
1418
1419         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1420         instructions that can support stack pointer operations.
1421         * rl78-decode.c: Regenerate.
1422         * rl78-dis.c: Fix display of stack pointer in MOVW based
1423         instructions.
1424
1425 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1426
1427         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1428         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1429         erxtatus_el1 and erxaddr_el1.
1430
1431 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1432
1433         * arm-dis.c (arm_opcodes): Add "esb".
1434         (thumb_opcodes): Likewise.
1435
1436 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1437
1438         * ppc-opc.c <xscmpnedp>: Delete.
1439         <xvcmpnedp>: Likewise.
1440         <xvcmpnedp.>: Likewise.
1441         <xvcmpnesp>: Likewise.
1442         <xvcmpnesp.>: Likewise.
1443
1444 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1445
1446         PR gas/13050
1447         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1448         addition to ISA_A.
1449
1450 2016-01-01  Alan Modra  <amodra@gmail.com>
1451
1452         Update year range in copyright notice of all files.
1453
1454 For older changes see ChangeLog-2015
1455 \f
1456 Copyright (C) 2016 Free Software Foundation, Inc.
1457
1458 Copying and distribution of this file, with or without modification,
1459 are permitted in any medium without royalty provided the copyright
1460 notice and this notice are preserved.
1461
1462 Local Variables:
1463 mode: change-log
1464 left-margin: 8
1465 fill-column: 74
1466 version-control: never
1467 End: