opcodes/ChangeLog

   1 2013-03-12  Michael Eager <eager@eagercon.com>
   2
   3         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
   4
   5 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
   6
   7         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
   8
   9 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  10
  11         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
  12
  13 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  14
  15         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
  16
  17 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  18
  19         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
  20         (thumb32_opcodes): Likewise.
  21         (print_insn_thumb32): Handle 'S' control char.
  22
  23 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
  24
  25         * lm32-desc.c: Regenerate.
  26
  27 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         * i386-reg.tbl (riz): Add RegRex64.
  30         * i386-tbl.h: Regenerated.
  31
  32 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
  33
  34         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
  35         (aarch64_feature_crc): New static.
  36         (CRC): New macro.
  37         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
  38         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
  39         * aarch64-asm-2.c: Re-generate.
  40         * aarch64-dis-2.c: Ditto.
  41         * aarch64-opc-2.c: Ditto.
  42
  43 2013-02-27  Alan Modra  <amodra@gmail.com>
  44
  45         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
  46         * rl78-decode.c: Regenerate.
  47
  48 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
  49
  50         * rl78-decode.opc: Fix encoding of DIVWU insn.
  51         * rl78-decode.c: Regenerate.
  52
  53 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
  54
  55         PR gas/15159
  56         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
  57
  58         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
  59         (cpu_flags): Add CpuSMAP.
  60
  61         * i386-opc.h (CpuSMAP): New.
  62         (i386_cpu_flags): Add cpusmap.
  63
  64         * i386-opc.tbl: Add clac and stac.
  65
  66         * i386-init.h: Regenerated.
  67         * i386-tbl.h: Likewise.
  68
  69 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
  70
  71         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
  72         which also makes the disassembler output be in little
  73         endian like it should be.
  74
  75 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
  76
  77         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
  78         fields to NULL.
  79         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
  80
  81 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
  82
  83         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
  84         section disassembled.
  85
  86 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  87
  88         * arm-dis.c: Update strht pattern.
  89
  90 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
  91
  92         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
  93         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
  94         trunc.w.s macro for EE.
  95
  96 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
  97             Andrew Jenner <andrew@codesourcery.com>
  98
  99         Based on patches from Altera Corporation.
 100
 101         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 102         nios2-opc.c.
 103         * Makefile.in: Regenerated.
 104         * configure.in: Add case for bfd_nios2_arch.
 105         * configure: Regenerated.
 106         * disassemble.c (ARCH_nios2): Define.
 107         (disassembler): Add case for bfd_arch_nios2.
 108         * nios2-dis.c: New file.
 109         * nios2-opc.c: New file.
 110
 111 2013-02-04  Alan Modra  <amodra@gmail.com>
 112
 113         * po/POTFILES.in: Regenerate.
 114         * rl78-decode.c: Regenerate.
 115         * rx-decode.c: Regenerate.
 116
 117 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 118
 119         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 120         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 121         * aarch64-asm.c (convert_xtl_to_shll): New function.
 122         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 123         calling convert_xtl_to_shll.
 124         * aarch64-dis.c (convert_shll_to_xtl): New function.
 125         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 126         calling convert_shll_to_xtl.
 127         * aarch64-gen.c: Update copyright year.
 128         * aarch64-asm-2.c: Re-generate.
 129         * aarch64-dis-2.c: Re-generate.
 130         * aarch64-opc-2.c: Re-generate.
 131
 132 2013-01-24  Nick Clifton  <nickc@redhat.com>
 133
 134         * v850-dis.c: Add support for e3v5 architecture.
 135         * v850-opc.c: Likewise.
 136
 137 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 138
 139         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 140         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 141         * aarch64-opc.c (operand_general_constraint_met_p): For
 142         AARCH64_MOD_LSL, move the range check on the shift amount before the
 143         alignment check; change to call set_sft_amount_out_of_range_error
 144         instead of set_imm_out_of_range_error.
 145         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 146         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 147         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 148         SIMD_IMM_SFT.
 149
 150 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 151
 152         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 153
 154         * i386-init.h: Regenerated.
 155         * i386-tbl.h: Likewise.
 156
 157 2013-01-15  Nick Clifton  <nickc@redhat.com>
 158
 159         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 160         values.
 161         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 162
 163 2013-01-14  Will Newton <will.newton@imgtec.com>
 164
 165         * metag-dis.c (REG_WIDTH): Increase to 64.
 166
 167 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 168
 169         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 170         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 171         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 172         (SH6): Update.
 173         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 174         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 175         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 176         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 177
 178 2013-01-10  Will Newton <will.newton@imgtec.com>
 179
 180         * Makefile.am: Add Meta.
 181         * configure.in: Add Meta.
 182         * disassemble.c: Add Meta support.
 183         * metag-dis.c: New file.
 184         * Makefile.in: Regenerate.
 185         * configure: Regenerate.
 186
 187 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 188
 189         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 190         (match_opcode): Rename to cr16_match_opcode.
 191
 192 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 193
 194         * mips-dis.c: Add names for CP0 registers of r5900.
 195         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 196         instructions sq and lq.
 197         Add support for MIPS r5900 CPU.
 198         Add support for 128 bit MMI (Multimedia Instructions).
 199         Add support for EE instructions (Emotion Engine).
 200         Disable unsupported floating point instructions (64 bit and
 201         undefined compare operations).
 202         Enable instructions of MIPS ISA IV which are supported by r5900.
 203         Disable 64 bit co processor instructions.
 204         Disable 64 bit multiplication and division instructions.
 205         Disable instructions for co-processor 2 and 3, because these are
 206         not supported (preparation for later VU0 support (Vector Unit)).
 207         Disable cvt.w.s because this behaves like trunc.w.s and the
 208         correct execution can't be ensured on r5900.
 209         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 210         will confuse less developers and compilers.
 211
 212 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 213
 214         * aarch64-opc.c (aarch64_print_operand): Change to print
 215         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 216         in comment.
 217         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 218         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 219         OP_MOV_IMM_WIDE.
 220
 221 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 222
 223         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 224         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 225
 226 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         * i386-gen.c (process_copyright): Update copyright year to 2013.
 229
 230 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 231
 232         * cr16-dis.c (match_opcode,make_instruction): Remove static
 233         declaration.
 234         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 235         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 236
 237 For older changes see ChangeLog-2012
 238 \f
 239 Copyright (C) 2013 Free Software Foundation, Inc.
 240
 241 Copying and distribution of this file, with or without modification,
 242 are permitted in any medium without royalty provided the copyright
 243 notice and this notice are preserved.
 244
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 246 mode: change-log
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