1 2018-11-12 Sudakshina Das <sudi.das@arm.com>
3 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
4 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
5 * aarch64-opc.c (fields): Add entry for imm4_3.
6 (operand_general_constraint_met_p): Add cases for
7 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
8 (aarch64_print_operand): Likewise.
9 * aarch64-tbl.h (QL_ADDG): New.
10 (aarch64_opcode_table): Add addg, subg, irg and gmi.
11 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
12 * aarch64-asm.c (aarch64_ins_imm): Add case for
13 operand_need_shift_by_four.
14 * aarch64-asm-2.c: Regenerated.
15 * aarch64-dis-2.c: Regenerated.
16 * aarch64-opc-2.c: Regenerated.
18 2018-11-12 Sudakshina Das <sudi.das@arm.com>
20 * aarch64-tbl.h (aarch64_feature_memtag): New.
21 (MEMTAG, MEMTAG_INSN): New.
23 2018-11-06 Sudakshina Das <sudi.das@arm.com>
25 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
26 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
28 2018-11-06 Alan Modra <amodra@gmail.com>
30 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
31 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
32 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
33 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
34 Don't return zero on error, insert mask bits instead.
35 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
36 (insert_sh6, extract_sh6): Delete dead code.
37 (insert_sprbat, insert_sprg): Use unsigned comparisions.
38 (powerpc_operands <OIMM>): Set shift count rather than using
40 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
42 2018-11-06 Jan Beulich <jbeulich@suse.com>
44 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
45 vpbroadcast{d,q} with GPR operand.
47 2018-11-06 Jan Beulich <jbeulich@suse.com>
49 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
50 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
51 cases up one level in the hierarchy.
53 2018-11-06 Jan Beulich <jbeulich@suse.com>
55 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
56 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
57 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
58 into MOD_VEX_0F93_P_3_LEN_0.
59 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
60 operand cases up one level in the hierarchy.
62 2018-11-06 Jan Beulich <jbeulich@suse.com>
64 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
65 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
66 EVEX_W_0F3A22_P_2): Delete.
67 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
68 entries up one level in the hierarchy.
69 (OP_E_memory): Handle dq_mode when determining Disp8 shift
71 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
72 entries up one level in the hierarchy.
73 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
74 VexWIG for AVX flavors.
75 * i386-tbl.h: Re-generate.
77 2018-11-06 Jan Beulich <jbeulich@suse.com>
79 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
80 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
81 vcvtusi2ss, kmovd): Drop VexW=1.
82 * i386-tbl.h: Re-generate.
84 2018-11-06 Jan Beulich <jbeulich@suse.com>
86 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
87 EVex512, EVexLIG, EVexDYN): New.
88 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
89 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
90 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
91 of EVex=4 (aka EVexLIG).
92 * i386-tbl.h: Re-generate.
94 2018-11-06 Jan Beulich <jbeulich@suse.com>
96 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
97 (vpmaxub): Re-order attributes on AVX512BW flavor.
98 * i386-tbl.h: Re-generate.
100 2018-11-06 Jan Beulich <jbeulich@suse.com>
102 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
103 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
104 Vex=1 on AVX / AVX2 flavors.
105 (vpmaxub): Re-order attributes on AVX512BW flavor.
106 * i386-tbl.h: Re-generate.
108 2018-11-06 Jan Beulich <jbeulich@suse.com>
110 * i386-opc.tbl (VexW0, VexW1): New.
111 (vphadd*, vphsub*): Use VexW0 on XOP variants.
112 * i386-tbl.h: Re-generate.
114 2018-10-22 John Darrington <john@darrington.wattle.id.au>
116 * s12z-dis.c (decode_possible_symbol): Add fallback case.
117 (rel_15_7): Likewise.
119 2018-10-19 Tamar Christina <tamar.christina@arm.com>
121 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
122 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
123 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
125 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
127 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
128 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
130 2018-10-10 Jan Beulich <jbeulich@suse.com>
132 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
134 * i386-opc.h (Size16, Size32, Size64): Delete.
136 (SIZE16, SIZE32, SIZE64): Define.
137 (struct i386_opcode_modifier): Drop size16, size32, and size64.
139 * i386-opc.tbl (Size16, Size32, Size64): Define.
140 * i386-tbl.h: Re-generate.
142 2018-10-09 Sudakshina Das <sudi.das@arm.com>
144 * aarch64-opc.c (operand_general_constraint_met_p): Add
145 SSBS in the check for one-bit immediate.
146 (aarch64_sys_regs): New entry for SSBS.
147 (aarch64_sys_reg_supported_p): New check for above.
148 (aarch64_pstatefields): New entry for SSBS.
149 (aarch64_pstatefield_supported_p): New check for above.
151 2018-10-09 Sudakshina Das <sudi.das@arm.com>
153 * aarch64-opc.c (aarch64_sys_regs): New entries for
154 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
155 (aarch64_sys_reg_supported_p): New checks for above.
157 2018-10-09 Sudakshina Das <sudi.das@arm.com>
159 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
160 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
161 with the hint immediate.
162 * aarch64-opc.c (aarch64_hint_options): New entries for
163 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
164 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
165 while checking for HINT_OPD_F_NOPRINT flag.
166 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
168 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
169 (aarch64_opcode_table): Add entry for BTI.
170 (AARCH64_OPERANDS): Add new description for BTI targets.
171 * aarch64-asm-2.c: Regenerate.
172 * aarch64-dis-2.c: Regenerate.
173 * aarch64-opc-2.c: Regenerate.
175 2018-10-09 Sudakshina Das <sudi.das@arm.com>
177 * aarch64-opc.c (aarch64_sys_regs): New entries for
179 (aarch64_sys_reg_supported_p): New check for above.
181 2018-10-09 Sudakshina Das <sudi.das@arm.com>
183 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
184 (aarch64_sys_ins_reg_supported_p): New check for above.
186 2018-10-09 Sudakshina Das <sudi.das@arm.com>
188 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
189 AARCH64_OPND_SYSREG_SR.
190 * aarch64-opc.c (aarch64_print_operand): Likewise.
191 (aarch64_sys_regs_sr): Define table.
192 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
193 AARCH64_FEATURE_PREDRES.
194 * aarch64-tbl.h (aarch64_feature_predres): New.
195 (PREDRES, PREDRES_INSN): New.
196 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
197 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
198 * aarch64-asm-2.c: Regenerate.
199 * aarch64-dis-2.c: Regenerate.
200 * aarch64-opc-2.c: Regenerate.
202 2018-10-09 Sudakshina Das <sudi.das@arm.com>
204 * aarch64-tbl.h (aarch64_feature_sb): New.
206 (aarch64_opcode_table): Add entry for sb.
207 * aarch64-asm-2.c: Regenerate.
208 * aarch64-dis-2.c: Regenerate.
209 * aarch64-opc-2.c: Regenerate.
211 2018-10-09 Sudakshina Das <sudi.das@arm.com>
213 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
214 (aarch64_feature_frintts): New.
215 (FLAGMANIP, FRINTTS): New.
216 (aarch64_opcode_table): Add entries for xaflag, axflag
217 and frint[32,64][x,z] instructions.
218 * aarch64-asm-2.c: Regenerate.
219 * aarch64-dis-2.c: Regenerate.
220 * aarch64-opc-2.c: Regenerate.
222 2018-10-09 Sudakshina Das <sudi.das@arm.com>
224 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
225 (ARMV8_5, V8_5_INSN): New.
227 2018-10-08 Tamar Christina <tamar.christina@arm.com>
229 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
231 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
233 * i386-dis.c (rm_table): Add enclv.
234 * i386-opc.tbl: Add enclv.
235 * i386-tbl.h: Regenerated.
237 2018-10-05 Sudakshina Das <sudi.das@arm.com>
239 * arm-dis.c (arm_opcodes): Add sb.
240 (thumb32_opcodes): Likewise.
242 2018-10-05 Richard Henderson <rth@twiddle.net>
243 Stafford Horne <shorne@gmail.com>
245 * or1k-desc.c: Regenerate.
246 * or1k-desc.h: Regenerate.
247 * or1k-opc.c: Regenerate.
248 * or1k-opc.h: Regenerate.
249 * or1k-opinst.c: Regenerate.
251 2018-10-05 Richard Henderson <rth@twiddle.net>
253 * or1k-asm.c: Regenerated.
254 * or1k-desc.c: Regenerated.
255 * or1k-desc.h: Regenerated.
256 * or1k-dis.c: Regenerated.
257 * or1k-ibld.c: Regenerated.
258 * or1k-opc.c: Regenerated.
259 * or1k-opc.h: Regenerated.
260 * or1k-opinst.c: Regenerated.
262 2018-10-05 Richard Henderson <rth@twiddle.net>
264 * or1k-asm.c: Regenerate.
266 2018-10-03 Tamar Christina <tamar.christina@arm.com>
268 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
269 * aarch64-dis.c (print_operands): Refactor to take notes.
270 (print_verifier_notes): New.
271 (print_aarch64_insn): Apply constraint verifier.
272 (print_insn_aarch64_word): Update call to print_aarch64_insn.
273 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
275 2018-10-03 Tamar Christina <tamar.christina@arm.com>
277 * aarch64-opc.c (init_insn_block): New.
278 (verify_constraints, aarch64_is_destructive_by_operands): New.
279 * aarch64-opc.h (verify_constraints): New.
281 2018-10-03 Tamar Christina <tamar.christina@arm.com>
283 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
284 * aarch64-opc.c (verify_ldpsw): Update arguments.
286 2018-10-03 Tamar Christina <tamar.christina@arm.com>
288 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
289 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
291 2018-10-03 Tamar Christina <tamar.christina@arm.com>
293 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
294 * aarch64-dis.c (insn_sequence): New.
296 2018-10-03 Tamar Christina <tamar.christina@arm.com>
298 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
299 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
300 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
301 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
304 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
306 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
308 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
309 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
310 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
311 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
312 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
313 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
314 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
316 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
318 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
320 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
322 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
323 are used when extracting signed fields and converting them to
324 potentially 64-bit types.
326 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
328 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
329 * Makefile.in: Re-generate.
330 * aclocal.m4: Re-generate.
331 * configure: Re-generate.
332 * configure.ac: Remove check for -Wno-missing-field-initializers.
333 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
334 (csky_v2_opcodes): Likewise.
336 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
338 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
340 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
342 * nds32-asm.c (operand_fields): Remove the unused fields.
343 (nds32_opcodes): Remove the unused instructions.
344 * nds32-dis.c (nds32_ex9_info): Removed.
345 (nds32_parse_opcode): Updated.
346 (print_insn_nds32): Likewise.
347 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
348 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
349 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
350 build_opcode_hash_table): New functions.
351 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
352 nds32_opcode_table): New.
353 (hw_ktabs): Declare it to a pointer rather than an array.
354 (build_hash_table): Removed.
355 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
356 SYN_ROPT and upadte HW_GPR and HW_INT.
357 * nds32-dis.c (keywords): Remove const.
358 (match_field): New function.
359 (nds32_parse_opcode): Updated.
360 * disassemble.c (disassemble_init_for_target):
361 Add disassemble_init_nds32.
362 * nds32-dis.c (eum map_type): New.
363 (nds32_private_data): Likewise.
364 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
365 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
366 (print_insn_nds32): Updated.
367 * nds32-asm.c (parse_aext_reg): Add new parameter.
368 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
371 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
372 (operand_fields): Add new fields.
373 (nds32_opcodes): Add new instructions.
374 (keyword_aridxi_mx): New keyword.
375 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
377 (ALU2_1, ALU2_2, ALU2_3): New macros.
378 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
380 2018-09-17 Kito Cheng <kito@andestech.com>
382 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
384 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
387 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
388 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
389 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
390 (EVEX_LEN_0F7E_P_1): Likewise.
391 (EVEX_LEN_0F7E_P_2): Likewise.
392 (EVEX_LEN_0FD6_P_2): Likewise.
393 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
394 (EVEX_LEN_TABLE): Likewise.
395 (EVEX_LEN_0F6E_P_2): New enum.
396 (EVEX_LEN_0F7E_P_1): Likewise.
397 (EVEX_LEN_0F7E_P_2): Likewise.
398 (EVEX_LEN_0FD6_P_2): Likewise.
399 (evex_len_table): New.
400 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
401 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
402 * i386-tbl.h: Regenerated.
404 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
407 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
408 VEX_LEN_0F7E_P_2 entries.
409 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
410 * i386-tbl.h: Regenerated.
412 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
414 * i386-dis.c (VZERO_Fixup): Removed.
416 (VEX_LEN_0F10_P_1): Likewise.
417 (VEX_LEN_0F10_P_3): Likewise.
418 (VEX_LEN_0F11_P_1): Likewise.
419 (VEX_LEN_0F11_P_3): Likewise.
420 (VEX_LEN_0F2E_P_0): Likewise.
421 (VEX_LEN_0F2E_P_2): Likewise.
422 (VEX_LEN_0F2F_P_0): Likewise.
423 (VEX_LEN_0F2F_P_2): Likewise.
424 (VEX_LEN_0F51_P_1): Likewise.
425 (VEX_LEN_0F51_P_3): Likewise.
426 (VEX_LEN_0F52_P_1): Likewise.
427 (VEX_LEN_0F53_P_1): Likewise.
428 (VEX_LEN_0F58_P_1): Likewise.
429 (VEX_LEN_0F58_P_3): Likewise.
430 (VEX_LEN_0F59_P_1): Likewise.
431 (VEX_LEN_0F59_P_3): Likewise.
432 (VEX_LEN_0F5A_P_1): Likewise.
433 (VEX_LEN_0F5A_P_3): Likewise.
434 (VEX_LEN_0F5C_P_1): Likewise.
435 (VEX_LEN_0F5C_P_3): Likewise.
436 (VEX_LEN_0F5D_P_1): Likewise.
437 (VEX_LEN_0F5D_P_3): Likewise.
438 (VEX_LEN_0F5E_P_1): Likewise.
439 (VEX_LEN_0F5E_P_3): Likewise.
440 (VEX_LEN_0F5F_P_1): Likewise.
441 (VEX_LEN_0F5F_P_3): Likewise.
442 (VEX_LEN_0FC2_P_1): Likewise.
443 (VEX_LEN_0FC2_P_3): Likewise.
444 (VEX_LEN_0F3A0A_P_2): Likewise.
445 (VEX_LEN_0F3A0B_P_2): Likewise.
446 (VEX_W_0F10_P_0): Likewise.
447 (VEX_W_0F10_P_1): Likewise.
448 (VEX_W_0F10_P_2): Likewise.
449 (VEX_W_0F10_P_3): Likewise.
450 (VEX_W_0F11_P_0): Likewise.
451 (VEX_W_0F11_P_1): Likewise.
452 (VEX_W_0F11_P_2): Likewise.
453 (VEX_W_0F11_P_3): Likewise.
454 (VEX_W_0F12_P_0_M_0): Likewise.
455 (VEX_W_0F12_P_0_M_1): Likewise.
456 (VEX_W_0F12_P_1): Likewise.
457 (VEX_W_0F12_P_2): Likewise.
458 (VEX_W_0F12_P_3): Likewise.
459 (VEX_W_0F13_M_0): Likewise.
460 (VEX_W_0F14): Likewise.
461 (VEX_W_0F15): Likewise.
462 (VEX_W_0F16_P_0_M_0): Likewise.
463 (VEX_W_0F16_P_0_M_1): Likewise.
464 (VEX_W_0F16_P_1): Likewise.
465 (VEX_W_0F16_P_2): Likewise.
466 (VEX_W_0F17_M_0): Likewise.
467 (VEX_W_0F28): Likewise.
468 (VEX_W_0F29): Likewise.
469 (VEX_W_0F2B_M_0): Likewise.
470 (VEX_W_0F2E_P_0): Likewise.
471 (VEX_W_0F2E_P_2): Likewise.
472 (VEX_W_0F2F_P_0): Likewise.
473 (VEX_W_0F2F_P_2): Likewise.
474 (VEX_W_0F50_M_0): Likewise.
475 (VEX_W_0F51_P_0): Likewise.
476 (VEX_W_0F51_P_1): Likewise.
477 (VEX_W_0F51_P_2): Likewise.
478 (VEX_W_0F51_P_3): Likewise.
479 (VEX_W_0F52_P_0): Likewise.
480 (VEX_W_0F52_P_1): Likewise.
481 (VEX_W_0F53_P_0): Likewise.
482 (VEX_W_0F53_P_1): Likewise.
483 (VEX_W_0F58_P_0): Likewise.
484 (VEX_W_0F58_P_1): Likewise.
485 (VEX_W_0F58_P_2): Likewise.
486 (VEX_W_0F58_P_3): Likewise.
487 (VEX_W_0F59_P_0): Likewise.
488 (VEX_W_0F59_P_1): Likewise.
489 (VEX_W_0F59_P_2): Likewise.
490 (VEX_W_0F59_P_3): Likewise.
491 (VEX_W_0F5A_P_0): Likewise.
492 (VEX_W_0F5A_P_1): Likewise.
493 (VEX_W_0F5A_P_3): Likewise.
494 (VEX_W_0F5B_P_0): Likewise.
495 (VEX_W_0F5B_P_1): Likewise.
496 (VEX_W_0F5B_P_2): Likewise.
497 (VEX_W_0F5C_P_0): Likewise.
498 (VEX_W_0F5C_P_1): Likewise.
499 (VEX_W_0F5C_P_2): Likewise.
500 (VEX_W_0F5C_P_3): Likewise.
501 (VEX_W_0F5D_P_0): Likewise.
502 (VEX_W_0F5D_P_1): Likewise.
503 (VEX_W_0F5D_P_2): Likewise.
504 (VEX_W_0F5D_P_3): Likewise.
505 (VEX_W_0F5E_P_0): Likewise.
506 (VEX_W_0F5E_P_1): Likewise.
507 (VEX_W_0F5E_P_2): Likewise.
508 (VEX_W_0F5E_P_3): Likewise.
509 (VEX_W_0F5F_P_0): Likewise.
510 (VEX_W_0F5F_P_1): Likewise.
511 (VEX_W_0F5F_P_2): Likewise.
512 (VEX_W_0F5F_P_3): Likewise.
513 (VEX_W_0F60_P_2): Likewise.
514 (VEX_W_0F61_P_2): Likewise.
515 (VEX_W_0F62_P_2): Likewise.
516 (VEX_W_0F63_P_2): Likewise.
517 (VEX_W_0F64_P_2): Likewise.
518 (VEX_W_0F65_P_2): Likewise.
519 (VEX_W_0F66_P_2): Likewise.
520 (VEX_W_0F67_P_2): Likewise.
521 (VEX_W_0F68_P_2): Likewise.
522 (VEX_W_0F69_P_2): Likewise.
523 (VEX_W_0F6A_P_2): Likewise.
524 (VEX_W_0F6B_P_2): Likewise.
525 (VEX_W_0F6C_P_2): Likewise.
526 (VEX_W_0F6D_P_2): Likewise.
527 (VEX_W_0F6F_P_1): Likewise.
528 (VEX_W_0F6F_P_2): Likewise.
529 (VEX_W_0F70_P_1): Likewise.
530 (VEX_W_0F70_P_2): Likewise.
531 (VEX_W_0F70_P_3): Likewise.
532 (VEX_W_0F71_R_2_P_2): Likewise.
533 (VEX_W_0F71_R_4_P_2): Likewise.
534 (VEX_W_0F71_R_6_P_2): Likewise.
535 (VEX_W_0F72_R_2_P_2): Likewise.
536 (VEX_W_0F72_R_4_P_2): Likewise.
537 (VEX_W_0F72_R_6_P_2): Likewise.
538 (VEX_W_0F73_R_2_P_2): Likewise.
539 (VEX_W_0F73_R_3_P_2): Likewise.
540 (VEX_W_0F73_R_6_P_2): Likewise.
541 (VEX_W_0F73_R_7_P_2): Likewise.
542 (VEX_W_0F74_P_2): Likewise.
543 (VEX_W_0F75_P_2): Likewise.
544 (VEX_W_0F76_P_2): Likewise.
545 (VEX_W_0F77_P_0): Likewise.
546 (VEX_W_0F7C_P_2): Likewise.
547 (VEX_W_0F7C_P_3): Likewise.
548 (VEX_W_0F7D_P_2): Likewise.
549 (VEX_W_0F7D_P_3): Likewise.
550 (VEX_W_0F7E_P_1): Likewise.
551 (VEX_W_0F7F_P_1): Likewise.
552 (VEX_W_0F7F_P_2): Likewise.
553 (VEX_W_0FAE_R_2_M_0): Likewise.
554 (VEX_W_0FAE_R_3_M_0): Likewise.
555 (VEX_W_0FC2_P_0): Likewise.
556 (VEX_W_0FC2_P_1): Likewise.
557 (VEX_W_0FC2_P_2): Likewise.
558 (VEX_W_0FC2_P_3): Likewise.
559 (VEX_W_0FD0_P_2): Likewise.
560 (VEX_W_0FD0_P_3): Likewise.
561 (VEX_W_0FD1_P_2): Likewise.
562 (VEX_W_0FD2_P_2): Likewise.
563 (VEX_W_0FD3_P_2): Likewise.
564 (VEX_W_0FD4_P_2): Likewise.
565 (VEX_W_0FD5_P_2): Likewise.
566 (VEX_W_0FD6_P_2): Likewise.
567 (VEX_W_0FD7_P_2_M_1): Likewise.
568 (VEX_W_0FD8_P_2): Likewise.
569 (VEX_W_0FD9_P_2): Likewise.
570 (VEX_W_0FDA_P_2): Likewise.
571 (VEX_W_0FDB_P_2): Likewise.
572 (VEX_W_0FDC_P_2): Likewise.
573 (VEX_W_0FDD_P_2): Likewise.
574 (VEX_W_0FDE_P_2): Likewise.
575 (VEX_W_0FDF_P_2): Likewise.
576 (VEX_W_0FE0_P_2): Likewise.
577 (VEX_W_0FE1_P_2): Likewise.
578 (VEX_W_0FE2_P_2): Likewise.
579 (VEX_W_0FE3_P_2): Likewise.
580 (VEX_W_0FE4_P_2): Likewise.
581 (VEX_W_0FE5_P_2): Likewise.
582 (VEX_W_0FE6_P_1): Likewise.
583 (VEX_W_0FE6_P_2): Likewise.
584 (VEX_W_0FE6_P_3): Likewise.
585 (VEX_W_0FE7_P_2_M_0): Likewise.
586 (VEX_W_0FE8_P_2): Likewise.
587 (VEX_W_0FE9_P_2): Likewise.
588 (VEX_W_0FEA_P_2): Likewise.
589 (VEX_W_0FEB_P_2): Likewise.
590 (VEX_W_0FEC_P_2): Likewise.
591 (VEX_W_0FED_P_2): Likewise.
592 (VEX_W_0FEE_P_2): Likewise.
593 (VEX_W_0FEF_P_2): Likewise.
594 (VEX_W_0FF0_P_3_M_0): Likewise.
595 (VEX_W_0FF1_P_2): Likewise.
596 (VEX_W_0FF2_P_2): Likewise.
597 (VEX_W_0FF3_P_2): Likewise.
598 (VEX_W_0FF4_P_2): Likewise.
599 (VEX_W_0FF5_P_2): Likewise.
600 (VEX_W_0FF6_P_2): Likewise.
601 (VEX_W_0FF7_P_2): Likewise.
602 (VEX_W_0FF8_P_2): Likewise.
603 (VEX_W_0FF9_P_2): Likewise.
604 (VEX_W_0FFA_P_2): Likewise.
605 (VEX_W_0FFB_P_2): Likewise.
606 (VEX_W_0FFC_P_2): Likewise.
607 (VEX_W_0FFD_P_2): Likewise.
608 (VEX_W_0FFE_P_2): Likewise.
609 (VEX_W_0F3800_P_2): Likewise.
610 (VEX_W_0F3801_P_2): Likewise.
611 (VEX_W_0F3802_P_2): Likewise.
612 (VEX_W_0F3803_P_2): Likewise.
613 (VEX_W_0F3804_P_2): Likewise.
614 (VEX_W_0F3805_P_2): Likewise.
615 (VEX_W_0F3806_P_2): Likewise.
616 (VEX_W_0F3807_P_2): Likewise.
617 (VEX_W_0F3808_P_2): Likewise.
618 (VEX_W_0F3809_P_2): Likewise.
619 (VEX_W_0F380A_P_2): Likewise.
620 (VEX_W_0F380B_P_2): Likewise.
621 (VEX_W_0F3817_P_2): Likewise.
622 (VEX_W_0F381C_P_2): Likewise.
623 (VEX_W_0F381D_P_2): Likewise.
624 (VEX_W_0F381E_P_2): Likewise.
625 (VEX_W_0F3820_P_2): Likewise.
626 (VEX_W_0F3821_P_2): Likewise.
627 (VEX_W_0F3822_P_2): Likewise.
628 (VEX_W_0F3823_P_2): Likewise.
629 (VEX_W_0F3824_P_2): Likewise.
630 (VEX_W_0F3825_P_2): Likewise.
631 (VEX_W_0F3828_P_2): Likewise.
632 (VEX_W_0F3829_P_2): Likewise.
633 (VEX_W_0F382A_P_2_M_0): Likewise.
634 (VEX_W_0F382B_P_2): Likewise.
635 (VEX_W_0F3830_P_2): Likewise.
636 (VEX_W_0F3831_P_2): Likewise.
637 (VEX_W_0F3832_P_2): Likewise.
638 (VEX_W_0F3833_P_2): Likewise.
639 (VEX_W_0F3834_P_2): Likewise.
640 (VEX_W_0F3835_P_2): Likewise.
641 (VEX_W_0F3837_P_2): Likewise.
642 (VEX_W_0F3838_P_2): Likewise.
643 (VEX_W_0F3839_P_2): Likewise.
644 (VEX_W_0F383A_P_2): Likewise.
645 (VEX_W_0F383B_P_2): Likewise.
646 (VEX_W_0F383C_P_2): Likewise.
647 (VEX_W_0F383D_P_2): Likewise.
648 (VEX_W_0F383E_P_2): Likewise.
649 (VEX_W_0F383F_P_2): Likewise.
650 (VEX_W_0F3840_P_2): Likewise.
651 (VEX_W_0F3841_P_2): Likewise.
652 (VEX_W_0F38DB_P_2): Likewise.
653 (VEX_W_0F3A08_P_2): Likewise.
654 (VEX_W_0F3A09_P_2): Likewise.
655 (VEX_W_0F3A0A_P_2): Likewise.
656 (VEX_W_0F3A0B_P_2): Likewise.
657 (VEX_W_0F3A0C_P_2): Likewise.
658 (VEX_W_0F3A0D_P_2): Likewise.
659 (VEX_W_0F3A0E_P_2): Likewise.
660 (VEX_W_0F3A0F_P_2): Likewise.
661 (VEX_W_0F3A21_P_2): Likewise.
662 (VEX_W_0F3A40_P_2): Likewise.
663 (VEX_W_0F3A41_P_2): Likewise.
664 (VEX_W_0F3A42_P_2): Likewise.
665 (VEX_W_0F3A62_P_2): Likewise.
666 (VEX_W_0F3A63_P_2): Likewise.
667 (VEX_W_0F3ADF_P_2): Likewise.
668 (VEX_LEN_0F77_P_0): New.
669 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
670 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
671 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
672 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
673 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
674 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
675 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
676 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
677 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
678 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
679 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
680 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
681 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
682 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
683 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
684 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
685 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
686 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
687 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
688 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
689 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
690 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
691 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
692 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
693 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
694 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
695 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
696 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
697 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
698 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
699 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
700 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
701 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
702 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
703 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
704 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
705 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
706 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
707 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
708 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
709 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
710 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
711 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
712 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
713 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
714 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
715 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
716 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
717 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
718 (vex_table): Update VEX 0F28 and 0F29 entries.
719 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
720 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
721 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
722 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
723 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
724 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
725 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
726 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
727 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
728 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
729 VEX_LEN_0F3A0B_P_2 entries.
730 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
731 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
732 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
733 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
734 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
735 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
736 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
737 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
738 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
739 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
740 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
741 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
742 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
743 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
744 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
745 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
746 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
747 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
748 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
749 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
750 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
751 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
752 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
753 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
754 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
755 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
756 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
757 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
758 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
759 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
760 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
761 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
762 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
763 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
764 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
765 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
766 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
767 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
768 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
769 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
770 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
771 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
772 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
773 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
774 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
775 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
776 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
777 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
778 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
779 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
780 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
781 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
782 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
783 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
784 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
785 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
786 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
787 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
788 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
789 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
790 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
791 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
792 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
793 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
794 VEX_W_0F3ADF_P_2 entries.
795 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
796 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
797 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
799 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
801 * i386-opc.tbl (VexWIG): New.
802 Replace VexW=3 with VexWIG.
804 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
806 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
807 * i386-tbl.h: Regenerated.
809 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
812 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
813 VEX_LEN_0FD6_P_2 entries.
814 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
815 * i386-tbl.h: Regenerated.
817 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
820 * i386-opc.h (VEXWIG): New.
821 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
822 * i386-tbl.h: Regenerated.
824 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
827 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
828 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
829 * i386-dis.c (EXxEVexR64): New.
830 (evex_rounding_64_mode): Likewise.
831 (OP_Rounding): Handle evex_rounding_64_mode.
833 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
836 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
837 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
838 * i386-dis.c (Edqa): New.
839 (dqa_mode): Likewise.
840 (intel_operand_size): Handle dqa_mode as m_mode.
841 (OP_E_register): Handle dqa_mode as dq_mode.
842 (OP_E_memory): Set shift for dqa_mode based on address_mode.
844 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
846 * i386-dis.c (OP_E_memory): Reformat.
848 2018-09-14 Jan Beulich <jbeulich@suse.com>
850 * i386-opc.tbl (crc32): Fold byte and word forms.
851 * i386-tbl.h: Re-generate.
853 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
855 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
856 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
857 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
858 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
859 * i386-tbl.h: Regenerated.
861 2018-09-13 Jan Beulich <jbeulich@suse.com>
863 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
865 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
866 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
867 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
868 * i386-tbl.h: Re-generate.
870 2018-09-13 Jan Beulich <jbeulich@suse.com>
872 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
874 * i386-tbl.h: Re-generate.
876 2018-09-13 Jan Beulich <jbeulich@suse.com>
878 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
880 * i386-tbl.h: Re-generate.
882 2018-09-13 Jan Beulich <jbeulich@suse.com>
884 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
886 * i386-tbl.h: Re-generate.
888 2018-09-13 Jan Beulich <jbeulich@suse.com>
890 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
892 * i386-tbl.h: Re-generate.
894 2018-09-13 Jan Beulich <jbeulich@suse.com>
896 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
898 * i386-tbl.h: Re-generate.
900 2018-09-13 Jan Beulich <jbeulich@suse.com>
902 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
904 * i386-tbl.h: Re-generate.
906 2018-09-13 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
909 * i386-tbl.h: Re-generate.
911 2018-09-13 Jan Beulich <jbeulich@suse.com>
913 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
914 * i386-tbl.h: Re-generate.
916 2018-09-13 Jan Beulich <jbeulich@suse.com>
918 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
920 * i386-tbl.h: Re-generate.
922 2018-09-13 Jan Beulich <jbeulich@suse.com>
924 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
926 * i386-tbl.h: Re-generate.
928 2018-09-13 Jan Beulich <jbeulich@suse.com>
930 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
931 * i386-tbl.h: Re-generate.
933 2018-09-13 Jan Beulich <jbeulich@suse.com>
935 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
936 * i386-tbl.h: Re-generate.
938 2018-09-13 Jan Beulich <jbeulich@suse.com>
940 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
941 * i386-tbl.h: Re-generate.
943 2018-09-13 Jan Beulich <jbeulich@suse.com>
945 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
947 * i386-tbl.h: Re-generate.
949 2018-09-13 Jan Beulich <jbeulich@suse.com>
951 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
953 * i386-tbl.h: Re-generate.
955 2018-09-13 Jan Beulich <jbeulich@suse.com>
957 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
959 * i386-tbl.h: Re-generate.
961 2018-09-13 Jan Beulich <jbeulich@suse.com>
963 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
964 * i386-tbl.h: Re-generate.
966 2018-09-13 Jan Beulich <jbeulich@suse.com>
968 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
969 * i386-tbl.h: Re-generate.
971 2018-09-13 Jan Beulich <jbeulich@suse.com>
973 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
974 * i386-tbl.h: Re-generate.
976 2018-09-13 Jan Beulich <jbeulich@suse.com>
978 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
979 (vpbroadcastw, rdpid): Drop NoRex64.
980 * i386-tbl.h: Re-generate.
982 2018-09-13 Jan Beulich <jbeulich@suse.com>
984 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
985 store templates, adding D.
986 * i386-tbl.h: Re-generate.
988 2018-09-13 Jan Beulich <jbeulich@suse.com>
990 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
991 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
992 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
993 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
994 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
995 Fold load and store templates where possible, adding D. Drop
996 IgnoreSize where it was pointlessly present. Drop redundant
998 * i386-tbl.h: Re-generate.
1000 2018-09-13 Jan Beulich <jbeulich@suse.com>
1002 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1003 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1004 (intel_operand_size): Handle v_bndmk_mode.
1005 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1007 2018-09-08 John Darrington <john@darrington.wattle.id.au>
1009 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1011 2018-08-31 Kito Cheng <kito@andestech.com>
1013 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1014 compressed floating point instructions.
1016 2018-08-30 Kito Cheng <kito@andestech.com>
1018 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1019 riscv_opcode.xlen_requirement.
1020 * riscv-opc.c (riscv_opcodes): Update for struct change.
1022 2018-08-29 Martin Aberg <maberg@gaisler.com>
1024 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1025 psr (PWRPSR) instruction.
1027 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1029 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1031 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1033 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1035 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1037 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1038 loongson3a as an alias of gs464 for compatibility.
1039 * mips-opc.c (mips_opcodes): Change Comments.
1041 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1043 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1045 (print_mips_disassembler_options): Document -M loongson-ext.
1046 * mips-opc.c (LEXT2): New macro.
1047 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1049 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1051 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1053 (parse_mips_ase_option): Handle -M loongson-ext option.
1054 (print_mips_disassembler_options): Document -M loongson-ext.
1055 * mips-opc.c (IL3A): Delete.
1056 * mips-opc.c (LEXT): New macro.
1057 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1060 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1062 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1064 (parse_mips_ase_option): Handle -M loongson-cam option.
1065 (print_mips_disassembler_options): Document -M loongson-cam.
1066 * mips-opc.c (LCAM): New macro.
1067 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1070 2018-08-21 Alan Modra <amodra@gmail.com>
1072 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1073 (skip_optional_operands): Count optional operands, and update
1074 ppc_optional_operand_value call.
1075 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1076 (extract_vlensi): Likewise.
1077 (extract_fxm): Return default value for missing optional operand.
1078 (extract_ls, extract_raq, extract_tbr): Likewise.
1079 (insert_sxl, extract_sxl): New functions.
1080 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1081 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1082 flag and extra entry.
1083 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1086 2018-08-20 Alan Modra <amodra@gmail.com>
1088 * sh-opc.h (MASK): Simplify.
1090 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1092 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1093 BM_RESERVED0 or BM_RESERVED1
1094 (bm_rel_decode, bm_n_bytes): Ditto.
1096 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1100 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1102 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1103 address with the addr32 prefix and without base nor index
1106 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1108 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1109 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1110 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1111 (cpu_flags): Add CpuCMOV and CpuFXSR.
1112 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1113 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1114 * i386-init.h: Regenerated.
1115 * i386-tbl.h: Likewise.
1117 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1119 * arc-regs.h: Update auxiliary registers.
1121 2018-08-06 Jan Beulich <jbeulich@suse.com>
1123 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1124 (RegIP, RegIZ): Define.
1125 * i386-reg.tbl: Adjust comments.
1126 (rip): Use Qword instead of BaseIndex. Use RegIP.
1127 (eip): Use Dword instead of BaseIndex. Use RegIP.
1128 (riz): Add Qword. Use RegIZ.
1129 (eiz): Add Dword. Use RegIZ.
1130 * i386-tbl.h: Re-generate.
1132 2018-08-03 Jan Beulich <jbeulich@suse.com>
1134 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1135 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1136 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1137 * i386-tbl.h: Re-generate.
1139 2018-08-03 Jan Beulich <jbeulich@suse.com>
1141 * i386-gen.c (operand_types): Remove Mem field.
1142 * i386-opc.h (union i386_operand_type): Remove mem field.
1143 * i386-init.h, i386-tbl.h: Re-generate.
1145 2018-08-01 Alan Modra <amodra@gmail.com>
1147 * po/POTFILES.in: Regenerate.
1149 2018-07-31 Nick Clifton <nickc@redhat.com>
1151 * po/sv.po: Updated Swedish translation.
1153 2018-07-31 Jan Beulich <jbeulich@suse.com>
1155 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1156 * i386-init.h, i386-tbl.h: Re-generate.
1158 2018-07-31 Jan Beulich <jbeulich@suse.com>
1160 * i386-opc.h (ZEROING_MASKING) Rename to ...
1161 (DYNAMIC_MASKING): ... this. Adjust comment.
1162 * i386-opc.tbl (MaskingMorZ): Define.
1163 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1164 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1165 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1166 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1167 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1168 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1169 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1170 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1171 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1173 2018-07-31 Jan Beulich <jbeulich@suse.com>
1175 * i386-opc.tbl: Use element rather than vector size for AVX512*
1176 scatter/gather insns.
1177 * i386-tbl.h: Re-generate.
1179 2018-07-31 Jan Beulich <jbeulich@suse.com>
1181 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1182 (cpu_flags): Drop CpuVREX.
1183 * i386-opc.h (CpuVREX): Delete.
1184 (union i386_cpu_flags): Remove cpuvrex.
1185 * i386-init.h, i386-tbl.h: Re-generate.
1187 2018-07-30 Jim Wilson <jimw@sifive.com>
1189 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1191 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1193 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1195 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1196 * Makefile.in: Regenerated.
1197 * configure.ac: Add C-SKY.
1198 * configure: Regenerated.
1199 * csky-dis.c: New file.
1200 * csky-opc.h: New file.
1201 * disassemble.c (ARCH_csky): Define.
1202 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1203 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1205 2018-07-27 Alan Modra <amodra@gmail.com>
1207 * ppc-opc.c (insert_sprbat): Correct function parameter and
1209 (extract_sprbat): Likewise, variable too.
1211 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1212 Alan Modra <amodra@gmail.com>
1214 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1215 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1216 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1217 support disjointed BAT.
1218 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1219 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1220 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1222 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1223 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1225 * i386-gen.c (adjust_broadcast_modifier): New function.
1226 (process_i386_opcode_modifier): Add an argument for operands.
1227 Adjust the Broadcast value based on operands.
1228 (output_i386_opcode): Pass operand_types to
1229 process_i386_opcode_modifier.
1230 (process_i386_opcodes): Pass NULL as operands to
1231 process_i386_opcode_modifier.
1232 * i386-opc.h (BYTE_BROADCAST): New.
1233 (WORD_BROADCAST): Likewise.
1234 (DWORD_BROADCAST): Likewise.
1235 (QWORD_BROADCAST): Likewise.
1236 (i386_opcode_modifier): Expand broadcast to 3 bits.
1237 * i386-tbl.h: Regenerated.
1239 2018-07-24 Alan Modra <amodra@gmail.com>
1242 * or1k-desc.h: Regenerate.
1244 2018-07-24 Jan Beulich <jbeulich@suse.com>
1246 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1247 vcvtusi2ss, and vcvtusi2sd.
1248 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1249 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1250 * i386-tbl.h: Re-generate.
1252 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1254 * arc-opc.c (extract_w6): Fix extending the sign.
1256 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1258 * arc-tbl.h (vewt): Allow it for ARC EM family.
1260 2018-07-23 Alan Modra <amodra@gmail.com>
1263 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1264 opcode variants for mtspr/mfspr encodings.
1266 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1267 Maciej W. Rozycki <macro@mips.com>
1269 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1270 loongson3a descriptors.
1271 (parse_mips_ase_option): Handle -M loongson-mmi option.
1272 (print_mips_disassembler_options): Document -M loongson-mmi.
1273 * mips-opc.c (LMMI): New macro.
1274 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1277 2018-07-19 Jan Beulich <jbeulich@suse.com>
1279 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1280 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1281 IgnoreSize and [XYZ]MMword where applicable.
1282 * i386-tbl.h: Re-generate.
1284 2018-07-19 Jan Beulich <jbeulich@suse.com>
1286 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1287 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1288 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1289 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1290 * i386-tbl.h: Re-generate.
1292 2018-07-19 Jan Beulich <jbeulich@suse.com>
1294 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1295 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1296 VPCLMULQDQ templates into their respective AVX512VL counterparts
1297 where possible, using Disp8ShiftVL and CheckRegSize instead of
1298 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1299 * i386-tbl.h: Re-generate.
1301 2018-07-19 Jan Beulich <jbeulich@suse.com>
1303 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1304 AVX512VL counterparts where possible, using Disp8ShiftVL and
1305 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1306 IgnoreSize) as appropriate.
1307 * i386-tbl.h: Re-generate.
1309 2018-07-19 Jan Beulich <jbeulich@suse.com>
1311 * i386-opc.tbl: Fold AVX512BW templates into their respective
1312 AVX512VL counterparts where possible, using Disp8ShiftVL and
1313 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1314 IgnoreSize) as appropriate.
1315 * i386-tbl.h: Re-generate.
1317 2018-07-19 Jan Beulich <jbeulich@suse.com>
1319 * i386-opc.tbl: Fold AVX512CD templates into their respective
1320 AVX512VL counterparts where possible, using Disp8ShiftVL and
1321 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1322 IgnoreSize) as appropriate.
1323 * i386-tbl.h: Re-generate.
1325 2018-07-19 Jan Beulich <jbeulich@suse.com>
1327 * i386-opc.h (DISP8_SHIFT_VL): New.
1328 * i386-opc.tbl (Disp8ShiftVL): Define.
1329 (various): Fold AVX512VL templates into their respective
1330 AVX512F counterparts where possible, using Disp8ShiftVL and
1331 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1332 IgnoreSize) as appropriate.
1333 * i386-tbl.h: Re-generate.
1335 2018-07-19 Jan Beulich <jbeulich@suse.com>
1337 * Makefile.am: Change dependencies and rule for
1338 $(srcdir)/i386-init.h.
1339 * Makefile.in: Re-generate.
1340 * i386-gen.c (process_i386_opcodes): New local variable
1341 "marker". Drop opening of input file. Recognize marker and line
1343 * i386-opc.tbl (OPCODE_I386_H): Define.
1344 (i386-opc.h): Include it.
1347 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1350 * i386-opc.h (Byte): Update comments.
1356 (Xmmword): Likewise.
1357 (Ymmword): Likewise.
1358 (Zmmword): Likewise.
1359 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1361 * i386-tbl.h: Regenerated.
1363 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1365 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1366 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1367 * aarch64-asm-2.c: Regenerate.
1368 * aarch64-dis-2.c: Regenerate.
1369 * aarch64-opc-2.c: Regenerate.
1371 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1374 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1375 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1376 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1377 sqdmulh, sqrdmulh): Use Em16.
1379 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1381 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1382 csdb together with them.
1383 (thumb32_opcodes): Likewise.
1385 2018-07-11 Jan Beulich <jbeulich@suse.com>
1387 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1388 requiring 32-bit registers as operands 2 and 3. Improve
1390 (mwait, mwaitx): Fold templates. Improve comments.
1391 OPERAND_TYPE_INOUTPORTREG.
1392 * i386-tbl.h: Re-generate.
1394 2018-07-11 Jan Beulich <jbeulich@suse.com>
1396 * i386-gen.c (operand_type_init): Remove
1397 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1398 OPERAND_TYPE_INOUTPORTREG.
1399 * i386-init.h: Re-generate.
1401 2018-07-11 Jan Beulich <jbeulich@suse.com>
1403 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1404 (wrssq, wrussq): Add Qword.
1405 * i386-tbl.h: Re-generate.
1407 2018-07-11 Jan Beulich <jbeulich@suse.com>
1409 * i386-opc.h: Rename OTMax to OTNum.
1410 (OTNumOfUints): Adjust calculation.
1411 (OTUnused): Directly alias to OTNum.
1413 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1415 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1417 (lea_reg_xys): Likewise.
1418 (print_insn_loop_primitive): Rename `reg' local variable to
1421 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1424 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1426 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1429 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1430 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1432 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1435 * mips-dis.c (mips_option_arg_t): New enumeration.
1436 (mips_options): New variable.
1437 (disassembler_options_mips): New function.
1438 (print_mips_disassembler_options): Reimplement in terms of
1439 `disassembler_options_mips'.
1440 * arm-dis.c (disassembler_options_arm): Adapt to using the
1441 `disasm_options_and_args_t' structure.
1442 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1443 * s390-dis.c (disassembler_options_s390): Likewise.
1445 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1447 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1449 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1450 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1451 * testsuite/ld-arm/tls-longplt.d: Likewise.
1453 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1456 * aarch64-asm-2.c: Regenerate.
1457 * aarch64-dis-2.c: Likewise.
1458 * aarch64-opc-2.c: Likewise.
1459 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1460 * aarch64-opc.c (operand_general_constraint_met_p,
1461 aarch64_print_operand): Likewise.
1462 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1463 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1465 (AARCH64_OPERANDS): Add Em2.
1467 2018-06-26 Nick Clifton <nickc@redhat.com>
1469 * po/uk.po: Updated Ukranian translation.
1470 * po/de.po: Updated German translation.
1471 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1473 2018-06-26 Nick Clifton <nickc@redhat.com>
1475 * nfp-dis.c: Fix spelling mistake.
1477 2018-06-24 Nick Clifton <nickc@redhat.com>
1479 * configure: Regenerate.
1480 * po/opcodes.pot: Regenerate.
1482 2018-06-24 Nick Clifton <nickc@redhat.com>
1484 2.31 branch created.
1486 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1488 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1489 * aarch64-asm-2.c: Regenerate.
1490 * aarch64-dis-2.c: Likewise.
1492 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1494 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1495 `-M ginv' option description.
1497 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1500 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1503 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1505 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1506 * configure.ac: Remove AC_PREREQ.
1507 * Makefile.in: Re-generate.
1508 * aclocal.m4: Re-generate.
1509 * configure: Re-generate.
1511 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1513 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1514 mips64r6 descriptors.
1515 (parse_mips_ase_option): Handle -Mginv option.
1516 (print_mips_disassembler_options): Document -Mginv.
1517 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1519 (mips_opcodes): Define ginvi and ginvt.
1521 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1522 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1524 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1525 * mips-opc.c (CRC, CRC64): New macros.
1526 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1527 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1530 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1533 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1534 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1536 2018-06-06 Alan Modra <amodra@gmail.com>
1538 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1539 setjmp. Move init for some other vars later too.
1541 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1543 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1544 (dis_private): Add new fields for property section tracking.
1545 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1546 (xtensa_instruction_fits): New functions.
1547 (fetch_data): Bump minimal fetch size to 4.
1548 (print_insn_xtensa): Make struct dis_private static.
1549 Load and prepare property table on section change.
1550 Don't disassemble literals. Don't disassemble instructions that
1551 cross property table boundaries.
1553 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1555 * configure: Regenerated.
1557 2018-06-01 Jan Beulich <jbeulich@suse.com>
1559 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1560 * i386-tbl.h: Re-generate.
1562 2018-06-01 Jan Beulich <jbeulich@suse.com>
1564 * i386-opc.tbl (sldt, str): Add NoRex64.
1565 * i386-tbl.h: Re-generate.
1567 2018-06-01 Jan Beulich <jbeulich@suse.com>
1569 * i386-opc.tbl (invpcid): Add Oword.
1570 * i386-tbl.h: Re-generate.
1572 2018-06-01 Alan Modra <amodra@gmail.com>
1574 * sysdep.h (_bfd_error_handler): Don't declare.
1575 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1576 * rl78-decode.opc: Likewise.
1577 * msp430-decode.c: Regenerate.
1578 * rl78-decode.c: Regenerate.
1580 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1582 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1583 * i386-init.h : Regenerated.
1585 2018-05-25 Alan Modra <amodra@gmail.com>
1587 * Makefile.in: Regenerate.
1588 * po/POTFILES.in: Regenerate.
1590 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1592 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1593 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1594 (insert_bab, extract_bab, insert_btab, extract_btab,
1595 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1596 (BAT, BBA VBA RBS XB6S): Delete macros.
1597 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1598 (BB, BD, RBX, XC6): Update for new macros.
1599 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1600 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1601 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1602 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1604 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1606 * Makefile.am: Add support for s12z architecture.
1607 * configure.ac: Likewise.
1608 * disassemble.c: Likewise.
1609 * disassemble.h: Likewise.
1610 * Makefile.in: Regenerate.
1611 * configure: Regenerate.
1612 * s12z-dis.c: New file.
1615 2018-05-18 Alan Modra <amodra@gmail.com>
1617 * nfp-dis.c: Don't #include libbfd.h.
1618 (init_nfp3200_priv): Use bfd_get_section_contents.
1619 (nit_nfp6000_mecsr_sec): Likewise.
1621 2018-05-17 Nick Clifton <nickc@redhat.com>
1623 * po/zh_CN.po: Updated simplified Chinese translation.
1625 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1628 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1629 * aarch64-dis-2.c: Regenerate.
1631 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1634 * aarch64-asm.c (opintl.h): Include.
1635 (aarch64_ins_sysreg): Enforce read/write constraints.
1636 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1637 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1638 (F_REG_READ, F_REG_WRITE): New.
1639 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1640 AARCH64_OPND_SYSREG.
1641 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1642 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1643 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1644 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1645 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1646 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1647 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1648 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1649 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1650 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1651 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1652 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1653 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1654 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1655 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1656 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1657 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1659 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1662 * aarch64-dis.c (no_notes: New.
1663 (parse_aarch64_dis_option): Support notes.
1664 (aarch64_decode_insn, print_operands): Likewise.
1665 (print_aarch64_disassembler_options): Document notes.
1666 * aarch64-opc.c (aarch64_print_operand): Support notes.
1668 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1671 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1672 and take error struct.
1673 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1674 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1675 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1676 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1677 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1678 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1679 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1680 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1681 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1682 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1683 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1684 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1685 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1686 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1687 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1688 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1689 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1690 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1691 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1692 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1693 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1694 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1695 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1696 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1697 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1698 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1699 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1700 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1701 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1702 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1703 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1704 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1705 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1706 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1707 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1708 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1709 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1710 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1711 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1712 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1713 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1714 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1715 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1716 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1717 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1718 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1719 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1720 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1721 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1722 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1723 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1724 (determine_disassembling_preference, aarch64_decode_insn,
1725 print_insn_aarch64_word, print_insn_data): Take errors struct.
1726 (print_insn_aarch64): Use errors.
1727 * aarch64-asm-2.c: Regenerate.
1728 * aarch64-dis-2.c: Regenerate.
1729 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1730 boolean in aarch64_insert_operan.
1731 (print_operand_extractor): Likewise.
1732 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1734 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1736 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1738 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1740 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1742 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1744 * cr16-opc.c (cr16_instruction): Comment typo fix.
1745 * hppa-dis.c (print_insn_hppa): Likewise.
1747 2018-05-08 Jim Wilson <jimw@sifive.com>
1749 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1750 (match_c_slli64, match_srxi_as_c_srxi): New.
1751 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1752 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1753 <c.slli, c.srli, c.srai>: Use match_s_slli.
1754 <c.slli64, c.srli64, c.srai64>: New.
1756 2018-05-08 Alan Modra <amodra@gmail.com>
1758 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1759 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1760 partition opcode space for index lookup.
1762 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1764 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1765 <insn_length>: ...with this. Update usage.
1766 Remove duplicate call to *info->memory_error_func.
1768 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1769 H.J. Lu <hongjiu.lu@intel.com>
1771 * i386-dis.c (Gva): New.
1772 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1773 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1774 (prefix_table): New instructions (see prefix above).
1775 (mod_table): New instructions (see prefix above).
1776 (OP_G): Handle va_mode.
1777 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1778 CPU_MOVDIR64B_FLAGS.
1779 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1780 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1781 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1782 * i386-opc.tbl: Add movidir{i,64b}.
1783 * i386-init.h: Regenerated.
1784 * i386-tbl.h: Likewise.
1786 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1788 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1790 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1791 (AddrPrefixOpReg): This.
1792 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1793 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1795 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1797 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1798 (vle_num_opcodes): Likewise.
1799 (spe2_num_opcodes): Likewise.
1800 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1801 initialization loop.
1802 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1803 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1806 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1808 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1810 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1812 Makefile.am: Added nfp-dis.c.
1813 configure.ac: Added bfd_nfp_arch.
1814 disassemble.h: Added print_insn_nfp prototype.
1815 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1816 nfp-dis.c: New, for NFP support.
1817 po/POTFILES.in: Added nfp-dis.c to the list.
1818 Makefile.in: Regenerate.
1819 configure: Regenerate.
1821 2018-04-26 Jan Beulich <jbeulich@suse.com>
1823 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1824 templates into their base ones.
1825 * i386-tlb.h: Re-generate.
1827 2018-04-26 Jan Beulich <jbeulich@suse.com>
1829 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1830 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1831 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1832 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1833 * i386-init.h: Re-generate.
1835 2018-04-26 Jan Beulich <jbeulich@suse.com>
1837 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1838 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1839 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1840 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1842 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1844 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1846 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1847 cpuregzmm, and cpuregmask.
1848 * i386-init.h: Re-generate.
1849 * i386-tbl.h: Re-generate.
1851 2018-04-26 Jan Beulich <jbeulich@suse.com>
1853 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1854 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1855 * i386-init.h: Re-generate.
1857 2018-04-26 Jan Beulich <jbeulich@suse.com>
1859 * i386-gen.c (VexImmExt): Delete.
1860 * i386-opc.h (VexImmExt, veximmext): Delete.
1861 * i386-opc.tbl: Drop all VexImmExt uses.
1862 * i386-tlb.h: Re-generate.
1864 2018-04-25 Jan Beulich <jbeulich@suse.com>
1866 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1867 register-only forms.
1868 * i386-tlb.h: Re-generate.
1870 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1872 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1874 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1876 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1878 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1879 (cpu_flags): Add CpuCLDEMOTE.
1880 * i386-init.h: Regenerate.
1881 * i386-opc.h (enum): Add CpuCLDEMOTE,
1882 (i386_cpu_flags): Add cpucldemote.
1883 * i386-opc.tbl: Add cldemote.
1884 * i386-tbl.h: Regenerate.
1886 2018-04-16 Alan Modra <amodra@gmail.com>
1888 * Makefile.am: Remove sh5 and sh64 support.
1889 * configure.ac: Likewise.
1890 * disassemble.c: Likewise.
1891 * disassemble.h: Likewise.
1892 * sh-dis.c: Likewise.
1893 * sh64-dis.c: Delete.
1894 * sh64-opc.c: Delete.
1895 * sh64-opc.h: Delete.
1896 * Makefile.in: Regenerate.
1897 * configure: Regenerate.
1898 * po/POTFILES.in: Regenerate.
1900 2018-04-16 Alan Modra <amodra@gmail.com>
1902 * Makefile.am: Remove w65 support.
1903 * configure.ac: Likewise.
1904 * disassemble.c: Likewise.
1905 * disassemble.h: Likewise.
1906 * w65-dis.c: Delete.
1907 * w65-opc.h: Delete.
1908 * Makefile.in: Regenerate.
1909 * configure: Regenerate.
1910 * po/POTFILES.in: Regenerate.
1912 2018-04-16 Alan Modra <amodra@gmail.com>
1914 * configure.ac: Remove we32k support.
1915 * configure: Regenerate.
1917 2018-04-16 Alan Modra <amodra@gmail.com>
1919 * Makefile.am: Remove m88k support.
1920 * configure.ac: Likewise.
1921 * disassemble.c: Likewise.
1922 * disassemble.h: Likewise.
1923 * m88k-dis.c: Delete.
1924 * Makefile.in: Regenerate.
1925 * configure: Regenerate.
1926 * po/POTFILES.in: Regenerate.
1928 2018-04-16 Alan Modra <amodra@gmail.com>
1930 * Makefile.am: Remove i370 support.
1931 * configure.ac: Likewise.
1932 * disassemble.c: Likewise.
1933 * disassemble.h: Likewise.
1934 * i370-dis.c: Delete.
1935 * i370-opc.c: Delete.
1936 * Makefile.in: Regenerate.
1937 * configure: Regenerate.
1938 * po/POTFILES.in: Regenerate.
1940 2018-04-16 Alan Modra <amodra@gmail.com>
1942 * Makefile.am: Remove h8500 support.
1943 * configure.ac: Likewise.
1944 * disassemble.c: Likewise.
1945 * disassemble.h: Likewise.
1946 * h8500-dis.c: Delete.
1947 * h8500-opc.h: Delete.
1948 * Makefile.in: Regenerate.
1949 * configure: Regenerate.
1950 * po/POTFILES.in: Regenerate.
1952 2018-04-16 Alan Modra <amodra@gmail.com>
1954 * configure.ac: Remove tahoe support.
1955 * configure: Regenerate.
1957 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1959 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1961 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1963 * i386-tbl.h: Regenerated.
1965 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1967 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1968 PREFIX_MOD_1_0FAE_REG_6.
1970 (OP_E_register): Use va_mode.
1971 * i386-dis-evex.h (prefix_table):
1972 New instructions (see prefixes above).
1973 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1974 (cpu_flags): Likewise.
1975 * i386-opc.h (enum): Likewise.
1976 (i386_cpu_flags): Likewise.
1977 * i386-opc.tbl: Add umonitor, umwait, tpause.
1978 * i386-init.h: Regenerate.
1979 * i386-tbl.h: Likewise.
1981 2018-04-11 Alan Modra <amodra@gmail.com>
1983 * opcodes/i860-dis.c: Delete.
1984 * opcodes/i960-dis.c: Delete.
1985 * Makefile.am: Remove i860 and i960 support.
1986 * configure.ac: Likewise.
1987 * disassemble.c: Likewise.
1988 * disassemble.h: Likewise.
1989 * Makefile.in: Regenerate.
1990 * configure: Regenerate.
1991 * po/POTFILES.in: Regenerate.
1993 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1996 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1998 (print_insn): Clear vex instead of vex.evex.
2000 2018-04-04 Nick Clifton <nickc@redhat.com>
2002 * po/es.po: Updated Spanish translation.
2004 2018-03-28 Jan Beulich <jbeulich@suse.com>
2006 * i386-gen.c (opcode_modifiers): Delete VecESize.
2007 * i386-opc.h (VecESize): Delete.
2008 (struct i386_opcode_modifier): Delete vecesize.
2009 * i386-opc.tbl: Drop VecESize.
2010 * i386-tlb.h: Re-generate.
2012 2018-03-28 Jan Beulich <jbeulich@suse.com>
2014 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2015 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2016 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2017 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2018 * i386-tlb.h: Re-generate.
2020 2018-03-28 Jan Beulich <jbeulich@suse.com>
2022 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2024 * i386-tlb.h: Re-generate.
2026 2018-03-28 Jan Beulich <jbeulich@suse.com>
2028 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2029 (vex_len_table): Drop Y for vcvt*2si.
2030 (putop): Replace plain 'Y' handling by abort().
2032 2018-03-28 Nick Clifton <nickc@redhat.com>
2035 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2036 instructions with only a base address register.
2037 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2038 handle AARHC64_OPND_SVE_ADDR_R.
2039 (aarch64_print_operand): Likewise.
2040 * aarch64-asm-2.c: Regenerate.
2041 * aarch64_dis-2.c: Regenerate.
2042 * aarch64-opc-2.c: Regenerate.
2044 2018-03-22 Jan Beulich <jbeulich@suse.com>
2046 * i386-opc.tbl: Drop VecESize from register only insn forms and
2047 memory forms not allowing broadcast.
2048 * i386-tlb.h: Re-generate.
2050 2018-03-22 Jan Beulich <jbeulich@suse.com>
2052 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2053 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2054 sha256*): Drop Disp<N>.
2056 2018-03-22 Jan Beulich <jbeulich@suse.com>
2058 * i386-dis.c (EbndS, bnd_swap_mode): New.
2059 (prefix_table): Use EbndS.
2060 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2061 * i386-opc.tbl (bndmov): Move misplaced Load.
2062 * i386-tlb.h: Re-generate.
2064 2018-03-22 Jan Beulich <jbeulich@suse.com>
2066 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2067 templates allowing memory operands and folded ones for register
2069 * i386-tlb.h: Re-generate.
2071 2018-03-22 Jan Beulich <jbeulich@suse.com>
2073 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2074 256-bit templates. Drop redundant leftover Disp<N>.
2075 * i386-tlb.h: Re-generate.
2077 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2079 * riscv-opc.c (riscv_insn_types): New.
2081 2018-03-13 Nick Clifton <nickc@redhat.com>
2083 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2085 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2087 * i386-opc.tbl: Add Optimize to clr.
2088 * i386-tbl.h: Regenerated.
2090 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2092 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2093 * i386-opc.h (OldGcc): Removed.
2094 (i386_opcode_modifier): Remove oldgcc.
2095 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2096 instructions for old (<= 2.8.1) versions of gcc.
2097 * i386-tbl.h: Regenerated.
2099 2018-03-08 Jan Beulich <jbeulich@suse.com>
2101 * i386-opc.h (EVEXDYN): New.
2102 * i386-opc.tbl: Fold various AVX512VL templates.
2103 * i386-tlb.h: Re-generate.
2105 2018-03-08 Jan Beulich <jbeulich@suse.com>
2107 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2108 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2109 vpexpandd, vpexpandq): Fold AFX512VF templates.
2110 * i386-tlb.h: Re-generate.
2112 2018-03-08 Jan Beulich <jbeulich@suse.com>
2114 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2115 Fold 128- and 256-bit VEX-encoded templates.
2116 * i386-tlb.h: Re-generate.
2118 2018-03-08 Jan Beulich <jbeulich@suse.com>
2120 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2121 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2122 vpexpandd, vpexpandq): Fold AVX512F templates.
2123 * i386-tlb.h: Re-generate.
2125 2018-03-08 Jan Beulich <jbeulich@suse.com>
2127 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2128 64-bit templates. Drop Disp<N>.
2129 * i386-tlb.h: Re-generate.
2131 2018-03-08 Jan Beulich <jbeulich@suse.com>
2133 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2134 and 256-bit templates.
2135 * i386-tlb.h: Re-generate.
2137 2018-03-08 Jan Beulich <jbeulich@suse.com>
2139 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2140 * i386-tlb.h: Re-generate.
2142 2018-03-08 Jan Beulich <jbeulich@suse.com>
2144 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2146 * i386-tlb.h: Re-generate.
2148 2018-03-08 Jan Beulich <jbeulich@suse.com>
2150 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2151 * i386-tlb.h: Re-generate.
2153 2018-03-08 Jan Beulich <jbeulich@suse.com>
2155 * i386-gen.c (opcode_modifiers): Delete FloatD.
2156 * i386-opc.h (FloatD): Delete.
2157 (struct i386_opcode_modifier): Delete floatd.
2158 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2160 * i386-tlb.h: Re-generate.
2162 2018-03-08 Jan Beulich <jbeulich@suse.com>
2164 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2166 2018-03-08 Jan Beulich <jbeulich@suse.com>
2168 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2169 * i386-tlb.h: Re-generate.
2171 2018-03-08 Jan Beulich <jbeulich@suse.com>
2173 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2175 * i386-tlb.h: Re-generate.
2177 2018-03-07 Alan Modra <amodra@gmail.com>
2179 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2181 * disassemble.h (print_insn_rs6000): Delete.
2182 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2183 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2184 (print_insn_rs6000): Delete.
2186 2018-03-03 Alan Modra <amodra@gmail.com>
2188 * sysdep.h (opcodes_error_handler): Define.
2189 (_bfd_error_handler): Declare.
2190 * Makefile.am: Remove stray #.
2191 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2193 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2194 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2195 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2196 opcodes_error_handler to print errors. Standardize error messages.
2197 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2198 and include opintl.h.
2199 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2200 * i386-gen.c: Standardize error messages.
2201 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2202 * Makefile.in: Regenerate.
2203 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2204 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2205 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2206 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2207 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2208 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2209 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2210 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2211 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2212 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2213 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2214 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2215 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2217 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2219 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2220 vpsub[bwdq] instructions.
2221 * i386-tbl.h: Regenerated.
2223 2018-03-01 Alan Modra <amodra@gmail.com>
2225 * configure.ac (ALL_LINGUAS): Sort.
2226 * configure: Regenerate.
2228 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2230 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2231 macro by assignements.
2233 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2236 * i386-gen.c (opcode_modifiers): Add Optimize.
2237 * i386-opc.h (Optimize): New enum.
2238 (i386_opcode_modifier): Add optimize.
2239 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2240 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2241 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2242 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2243 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2245 * i386-tbl.h: Regenerated.
2247 2018-02-26 Alan Modra <amodra@gmail.com>
2249 * crx-dis.c (getregliststring): Allocate a large enough buffer
2250 to silence false positive gcc8 warning.
2252 2018-02-22 Shea Levy <shea@shealevy.com>
2254 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2256 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2258 * i386-opc.tbl: Add {rex},
2259 * i386-tbl.h: Regenerated.
2261 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2263 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2264 (mips16_opcodes): Replace `M' with `m' for "restore".
2266 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2268 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2270 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2272 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2273 variable to `function_index'.
2275 2018-02-13 Nick Clifton <nickc@redhat.com>
2278 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2279 about truncation of printing.
2281 2018-02-12 Henry Wong <henry@stuffedcow.net>
2283 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2285 2018-02-05 Nick Clifton <nickc@redhat.com>
2287 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2289 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2291 * i386-dis.c (enum): Add pconfig.
2292 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2293 (cpu_flags): Add CpuPCONFIG.
2294 * i386-opc.h (enum): Add CpuPCONFIG.
2295 (i386_cpu_flags): Add cpupconfig.
2296 * i386-opc.tbl: Add PCONFIG instruction.
2297 * i386-init.h: Regenerate.
2298 * i386-tbl.h: Likewise.
2300 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2302 * i386-dis.c (enum): Add PREFIX_0F09.
2303 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2304 (cpu_flags): Add CpuWBNOINVD.
2305 * i386-opc.h (enum): Add CpuWBNOINVD.
2306 (i386_cpu_flags): Add cpuwbnoinvd.
2307 * i386-opc.tbl: Add WBNOINVD instruction.
2308 * i386-init.h: Regenerate.
2309 * i386-tbl.h: Likewise.
2311 2018-01-17 Jim Wilson <jimw@sifive.com>
2313 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2315 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2317 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2318 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2319 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2320 (cpu_flags): Add CpuIBT, CpuSHSTK.
2321 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2322 (i386_cpu_flags): Add cpuibt, cpushstk.
2323 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2324 * i386-init.h: Regenerate.
2325 * i386-tbl.h: Likewise.
2327 2018-01-16 Nick Clifton <nickc@redhat.com>
2329 * po/pt_BR.po: Updated Brazilian Portugese translation.
2330 * po/de.po: Updated German translation.
2332 2018-01-15 Jim Wilson <jimw@sifive.com>
2334 * riscv-opc.c (match_c_nop): New.
2335 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2337 2018-01-15 Nick Clifton <nickc@redhat.com>
2339 * po/uk.po: Updated Ukranian translation.
2341 2018-01-13 Nick Clifton <nickc@redhat.com>
2343 * po/opcodes.pot: Regenerated.
2345 2018-01-13 Nick Clifton <nickc@redhat.com>
2347 * configure: Regenerate.
2349 2018-01-13 Nick Clifton <nickc@redhat.com>
2351 2.30 branch created.
2353 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2355 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2356 * i386-tbl.h: Regenerate.
2358 2018-01-10 Jan Beulich <jbeulich@suse.com>
2360 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2361 * i386-tbl.h: Re-generate.
2363 2018-01-10 Jan Beulich <jbeulich@suse.com>
2365 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2366 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2367 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2368 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2369 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2370 Disp8MemShift of AVX512VL forms.
2371 * i386-tbl.h: Re-generate.
2373 2018-01-09 Jim Wilson <jimw@sifive.com>
2375 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2376 then the hi_addr value is zero.
2378 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2380 * arm-dis.c (arm_opcodes): Add csdb.
2381 (thumb32_opcodes): Add csdb.
2383 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2385 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2386 * aarch64-asm-2.c: Regenerate.
2387 * aarch64-dis-2.c: Regenerate.
2388 * aarch64-opc-2.c: Regenerate.
2390 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2393 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2394 Remove AVX512 vmovd with 64-bit operands.
2395 * i386-tbl.h: Regenerated.
2397 2018-01-05 Jim Wilson <jimw@sifive.com>
2399 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2402 2018-01-03 Alan Modra <amodra@gmail.com>
2404 Update year range in copyright notice of all files.
2406 2018-01-02 Jan Beulich <jbeulich@suse.com>
2408 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2409 and OPERAND_TYPE_REGZMM entries.
2411 For older changes see ChangeLog-2017
2413 Copyright (C) 2018 Free Software Foundation, Inc.
2415 Copying and distribution of this file, with or without modification,
2416 are permitted in any medium without royalty provided the copyright
2417 notice and this notice are preserved.
2423 version-control: never
projects / deliverable / binutils-gdb.git / blob