1 2005-03-12 Zack Weinberg <zack@codesourcery.com>
3 * arm-dis.c (arm_opcodes): Document %E and %V.
4 Add entries for v6T2 ARM instructions:
5 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
6 (print_insn_arm): Add support for %E and %V.
7 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
9 2005-03-10 Jeff Baker <jbaker@qnx.com>
10 Alan Modra <amodra@bigpond.net.au>
12 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
13 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
15 (XSPRG_MASK): Mask off extra bits now part of sprg field.
16 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
17 mfsprg4..7 after msprg and consolidate.
19 2005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
21 * vax-dis.c (entry_mask_bit): New array.
22 (print_insn_vax): Decode function entry mask.
24 2005-03-07 Aldy Hernandez <aldyh@redhat.com>
26 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
28 2005-03-05 Alan Modra <amodra@bigpond.net.au>
30 * po/opcodes.pot: Regenerate.
32 2005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
34 * arc-dis.c (a4_decoding_class): New enum.
35 (dsmOneArcInst): Use the enum values for the decoding class.
36 Remove redundant case in the switch for decodingClass value 11.
38 2005-03-02 Jan Beulich <jbeulich@novell.com>
40 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
42 (OP_C): Consider lock prefix in non-64-bit modes.
44 2005-02-24 Alan Modra <amodra@bigpond.net.au>
46 * cris-dis.c (format_hex): Remove ineffective warning fix.
47 * crx-dis.c (make_instruction): Warning fix.
48 * frv-asm.c: Regenerate.
50 2005-02-23 Nick Clifton <nickc@redhat.com>
52 * cgen-dis.in: Use bfd_byte for buffers that are passed to
55 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
57 * crx-dis.c (make_instruction): Move argument structure into inner
58 scope and ensure that all of its fields are initialised before
61 * fr30-asm.c: Regenerate.
62 * fr30-dis.c: Regenerate.
63 * frv-asm.c: Regenerate.
64 * frv-dis.c: Regenerate.
65 * ip2k-asm.c: Regenerate.
66 * ip2k-dis.c: Regenerate.
67 * iq2000-asm.c: Regenerate.
68 * iq2000-dis.c: Regenerate.
69 * m32r-asm.c: Regenerate.
70 * m32r-dis.c: Regenerate.
71 * openrisc-asm.c: Regenerate.
72 * openrisc-dis.c: Regenerate.
73 * xstormy16-asm.c: Regenerate.
74 * xstormy16-dis.c: Regenerate.
76 2005-02-22 Alan Modra <amodra@bigpond.net.au>
78 * arc-ext.c: Warning fixes.
79 * arc-ext.h: Likewise.
80 * cgen-opc.c: Likewise.
81 * ia64-gen.c: Likewise.
82 * maxq-dis.c: Likewise.
83 * ns32k-dis.c: Likewise.
84 * w65-dis.c: Likewise.
85 * ia64-asmtab.c: Regenerate.
87 2005-02-22 Alan Modra <amodra@bigpond.net.au>
89 * fr30-desc.c: Regenerate.
90 * fr30-desc.h: Regenerate.
91 * fr30-opc.c: Regenerate.
92 * fr30-opc.h: Regenerate.
93 * frv-desc.c: Regenerate.
94 * frv-desc.h: Regenerate.
95 * frv-opc.c: Regenerate.
96 * frv-opc.h: Regenerate.
97 * ip2k-desc.c: Regenerate.
98 * ip2k-desc.h: Regenerate.
99 * ip2k-opc.c: Regenerate.
100 * ip2k-opc.h: Regenerate.
101 * iq2000-desc.c: Regenerate.
102 * iq2000-desc.h: Regenerate.
103 * iq2000-opc.c: Regenerate.
104 * iq2000-opc.h: Regenerate.
105 * m32r-desc.c: Regenerate.
106 * m32r-desc.h: Regenerate.
107 * m32r-opc.c: Regenerate.
108 * m32r-opc.h: Regenerate.
109 * m32r-opinst.c: Regenerate.
110 * openrisc-desc.c: Regenerate.
111 * openrisc-desc.h: Regenerate.
112 * openrisc-opc.c: Regenerate.
113 * openrisc-opc.h: Regenerate.
114 * xstormy16-desc.c: Regenerate.
115 * xstormy16-desc.h: Regenerate.
116 * xstormy16-opc.c: Regenerate.
117 * xstormy16-opc.h: Regenerate.
119 2005-02-21 Alan Modra <amodra@bigpond.net.au>
121 * Makefile.am: Run "make dep-am"
122 * Makefile.in: Regenerate.
124 2005-02-15 Nick Clifton <nickc@redhat.com>
126 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
127 compile time warnings.
128 (print_keyword): Likewise.
129 (default_print_insn): Likewise.
131 * fr30-desc.c: Regenerated.
132 * fr30-desc.h: Regenerated.
133 * fr30-dis.c: Regenerated.
134 * fr30-opc.c: Regenerated.
135 * fr30-opc.h: Regenerated.
136 * frv-desc.c: Regenerated.
137 * frv-dis.c: Regenerated.
138 * frv-opc.c: Regenerated.
139 * ip2k-asm.c: Regenerated.
140 * ip2k-desc.c: Regenerated.
141 * ip2k-desc.h: Regenerated.
142 * ip2k-dis.c: Regenerated.
143 * ip2k-opc.c: Regenerated.
144 * ip2k-opc.h: Regenerated.
145 * iq2000-desc.c: Regenerated.
146 * iq2000-dis.c: Regenerated.
147 * iq2000-opc.c: Regenerated.
148 * m32r-asm.c: Regenerated.
149 * m32r-desc.c: Regenerated.
150 * m32r-desc.h: Regenerated.
151 * m32r-dis.c: Regenerated.
152 * m32r-opc.c: Regenerated.
153 * m32r-opc.h: Regenerated.
154 * m32r-opinst.c: Regenerated.
155 * openrisc-desc.c: Regenerated.
156 * openrisc-desc.h: Regenerated.
157 * openrisc-dis.c: Regenerated.
158 * openrisc-opc.c: Regenerated.
159 * openrisc-opc.h: Regenerated.
160 * xstormy16-desc.c: Regenerated.
161 * xstormy16-desc.h: Regenerated.
162 * xstormy16-dis.c: Regenerated.
163 * xstormy16-opc.c: Regenerated.
164 * xstormy16-opc.h: Regenerated.
166 2005-02-14 H.J. Lu <hongjiu.lu@intel.com>
168 * dis-buf.c (perror_memory): Use sprintf_vma to print out
171 2005-02-11 Nick Clifton <nickc@redhat.com>
173 * iq2000-asm.c: Regenerate.
175 * frv-dis.c: Regenerate.
177 2005-02-07 Jim Blandy <jimb@redhat.com>
179 * Makefile.am (CGEN): Load guile.scm before calling the main
181 * Makefile.in: Regenerated.
182 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
183 Simply pass the cgen-opc.scm path to ${cgen} as its first
184 argument; ${cgen} itself now contains the '-s', or whatever is
185 appropriate for the Scheme being used.
187 2005-01-31 Andrew Cagney <cagney@gnu.org>
189 * configure: Regenerate to track ../gettext.m4.
191 2005-01-31 Jan Beulich <jbeulich@novell.com>
193 * ia64-gen.c (NELEMS): Define.
194 (shrink): Generate alias with missing second predicate register when
195 opcode has two outputs and these are both predicates.
196 * ia64-opc-i.c (FULL17): Define.
197 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
198 here to generate output template.
199 (TBITCM, TNATCM): Undefine after use.
200 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
201 first input. Add ld16 aliases without ar.csd as second output. Add
202 st16 aliases without ar.csd as second input. Add cmpxchg aliases
203 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
204 ar.ccv as third/fourth inputs. Consolidate through...
205 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
206 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
207 * ia64-asmtab.c: Regenerate.
209 2005-01-27 Andrew Cagney <cagney@gnu.org>
211 * configure: Regenerate to track ../gettext.m4 change.
213 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
215 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
216 * frv-asm.c: Rebuilt.
217 * frv-desc.c: Rebuilt.
218 * frv-desc.h: Rebuilt.
219 * frv-dis.c: Rebuilt.
220 * frv-ibld.c: Rebuilt.
221 * frv-opc.c: Rebuilt.
222 * frv-opc.h: Rebuilt.
224 2005-01-24 Andrew Cagney <cagney@gnu.org>
226 * configure: Regenerate, ../gettext.m4 was updated.
228 2005-01-21 Fred Fish <fnf@specifixinc.com>
230 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
231 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
232 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
235 2005-01-20 Alan Modra <amodra@bigpond.net.au>
237 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
239 2005-01-19 Fred Fish <fnf@specifixinc.com>
241 * mips-dis.c (no_aliases): New disassembly option flag.
242 (set_default_mips_dis_options): Init no_aliases to zero.
243 (parse_mips_dis_option): Handle no-aliases option.
244 (print_insn_mips): Ignore table entries that are aliases
245 if no_aliases is set.
246 (print_insn_mips16): Ditto.
247 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
248 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
249 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
250 * mips16-opc.c (mips16_opcodes): Ditto.
252 2005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
254 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
255 (inheritance diagram): Add missing edge.
256 (arch_sh1_up): Rename arch_sh_up to match external name to make life
257 easier for the testsuite.
258 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
259 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
260 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
261 arch_sh2a_or_sh4_up child.
262 (sh_table): Do renaming as above.
263 Correct comment for ldc.l for gas testsuite to read.
264 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
265 Correct comments for movy.w and movy.l for gas testsuite to read.
266 Correct comments for fmov.d and fmov.s for gas testsuite to read.
268 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
270 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
272 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
274 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
276 2005-01-10 Andreas Schwab <schwab@suse.de>
278 * disassemble.c (disassemble_init_for_target) <case
279 bfd_arch_ia64>: Set skip_zeroes to 16.
280 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
282 2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
284 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
286 2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
288 * avr-dis.c: Prettyprint. Added printing of symbol names in all
289 memory references. Convert avr_operand() to C90 formatting.
291 2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
293 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
295 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
297 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
298 (no_op_insn): Initialize array with instructions that have no
300 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
302 2004-11-29 Richard Earnshaw <rearnsha@arm.com>
304 * arm-dis.c: Correct top-level comment.
306 2004-11-27 Richard Earnshaw <rearnsha@arm.com>
308 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
309 architecuture defining the insn.
310 (arm_opcodes, thumb_opcodes): Delete. Move to ...
311 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
313 Also include opcode/arm.h.
314 * Makefile.am (arm-dis.lo): Update dependency list.
315 * Makefile.in: Regenerate.
317 2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
319 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
320 reflect the change to the short immediate syntax.
322 2004-11-19 Alan Modra <amodra@bigpond.net.au>
324 * or32-opc.c (debug): Warning fix.
325 * po/POTFILES.in: Regenerate.
327 * maxq-dis.c: Formatting.
328 (print_insn): Warning fix.
330 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
332 * arm-dis.c (WORD_ADDRESS): Define.
333 (print_insn): Use it. Correct big-endian end-of-section handling.
335 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
336 Vineet Sharma <vineets@noida.hcltech.com>
338 * maxq-dis.c: New file.
339 * disassemble.c (ARCH_maxq): Define.
340 (disassembler): Add 'print_insn_maxq_little' for handling maxq
342 * configure.in: Add case for bfd_maxq_arch.
343 * configure: Regenerate.
344 * Makefile.am: Add support for maxq-dis.c
345 * Makefile.in: Regenerate.
346 * aclocal.m4: Regenerate.
348 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
350 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
352 * crx-dis.c: Likewise.
354 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
356 Generally, handle CRISv32.
357 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
358 (struct cris_disasm_data): New type.
359 (format_reg, format_hex, cris_constraint, print_flags)
360 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
362 (format_sup_reg, print_insn_crisv32_with_register_prefix)
363 (print_insn_crisv32_without_register_prefix)
364 (print_insn_crisv10_v32_with_register_prefix)
365 (print_insn_crisv10_v32_without_register_prefix)
366 (cris_parse_disassembler_options): New functions.
367 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
368 parameter. All callers changed.
369 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
371 (cris_constraint) <case 'Y', 'U'>: New cases.
372 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
374 (print_with_operands) <case 'Y'>: New case.
375 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
376 <case 'N', 'Y', 'Q'>: New cases.
377 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
378 (print_insn_cris_with_register_prefix)
379 (print_insn_cris_without_register_prefix): Call
380 cris_parse_disassembler_options.
381 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
382 for CRISv32 and the size of immediate operands. New v32-only
383 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
384 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
385 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
386 Change brp to be v3..v10.
387 (cris_support_regs): New vector.
388 (cris_opcodes): Update head comment. New format characters '[',
389 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
390 Add new opcodes for v32 and adjust existing opcodes to accommodate
391 differences to earlier variants.
392 (cris_cond15s): New vector.
394 2004-11-04 Jan Beulich <jbeulich@novell.com>
396 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
398 (Mp): Use f_mode rather than none at all.
399 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
400 replaces what previously was x_mode; x_mode now means 128-bit SSE
402 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
403 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
404 pinsrw's second operand is Edqw.
405 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
406 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
407 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
408 mode when an operand size override is present or always suffixing.
409 More instructions will need to be added to this group.
410 (putop): Handle new macro chars 'C' (short/long suffix selector),
411 'I' (Intel mode override for following macro char), and 'J' (for
412 adding the 'l' prefix to far branches in AT&T mode). When an
413 alternative was specified in the template, honor macro character when
414 specified for Intel mode.
415 (OP_E): Handle new *_mode values. Correct pointer specifications for
416 memory operands. Consolidate output of index register.
417 (OP_G): Handle new *_mode values.
418 (OP_I): Handle const_1_mode.
419 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
420 respective opcode prefix bits have been consumed.
421 (OP_EM, OP_EX): Provide some default handling for generating pointer
424 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
426 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
429 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
431 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
432 (getregliststring): Support HI/LO and user registers.
433 * crx-opc.c (crx_instruction): Update data structure according to the
434 rearrangement done in CRX opcode header file.
435 (crx_regtab): Likewise.
436 (crx_optab): Likewise.
437 (crx_instruction): Reorder load/stor instructions, remove unsupported
439 support new Co-Processor instruction 'cpi'.
441 2004-10-27 Nick Clifton <nickc@redhat.com>
443 * opcodes/iq2000-asm.c: Regenerate.
444 * opcodes/iq2000-desc.c: Regenerate.
445 * opcodes/iq2000-desc.h: Regenerate.
446 * opcodes/iq2000-dis.c: Regenerate.
447 * opcodes/iq2000-ibld.c: Regenerate.
448 * opcodes/iq2000-opc.c: Regenerate.
449 * opcodes/iq2000-opc.h: Regenerate.
451 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
453 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
454 us4, us5 (respectively).
455 Remove unsupported 'popa' instruction.
456 Reverse operands order in store co-processor instructions.
458 2004-10-15 Alan Modra <amodra@bigpond.net.au>
460 * Makefile.am: Run "make dep-am"
461 * Makefile.in: Regenerate.
463 2004-10-12 Bob Wilson <bob.wilson@acm.org>
465 * xtensa-dis.c: Use ISO C90 formatting.
467 2004-10-09 Alan Modra <amodra@bigpond.net.au>
469 * ppc-opc.c: Revert 2004-09-09 change.
471 2004-10-07 Bob Wilson <bob.wilson@acm.org>
473 * xtensa-dis.c (state_names): Delete.
474 (fetch_data): Use xtensa_isa_maxlength.
475 (print_xtensa_operand): Replace operand parameter with opcode/operand
476 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
477 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
478 instruction bundles. Use xmalloc instead of malloc.
480 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
482 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
485 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
487 * crx-opc.c (crx_instruction): Support Co-processor insns.
488 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
489 (getregliststring): Change function to use the above enum.
490 (print_arg): Handle CO-Processor insns.
491 (crx_cinvs): Add 'b' option to invalidate the branch-target
494 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
496 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
497 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
498 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
499 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
500 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
502 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
504 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
507 2004-09-30 Paul Brook <paul@codesourcery.com>
509 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
510 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
512 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
514 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
515 (CONFIG_STATUS_DEPENDENCIES): New.
517 (config.status): Likewise.
518 * Makefile.in: Regenerated.
520 2004-09-17 Alan Modra <amodra@bigpond.net.au>
522 * Makefile.am: Run "make dep-am".
523 * Makefile.in: Regenerate.
524 * aclocal.m4: Regenerate.
525 * configure: Regenerate.
526 * po/POTFILES.in: Regenerate.
527 * po/opcodes.pot: Regenerate.
529 2004-09-11 Andreas Schwab <schwab@suse.de>
531 * configure: Rebuild.
533 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
535 * ppc-opc.c (L): Make this field not optional.
537 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
539 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
540 Fix parameter to 'm[t|f]csr' insns.
542 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
544 * configure.in: Autoupdate to autoconf 2.59.
545 * aclocal.m4: Rebuild with aclocal 1.4p6.
546 * configure: Rebuild with autoconf 2.59.
547 * Makefile.in: Rebuild with automake 1.4p6 (picking up
548 bfd changes for autoconf 2.59 on the way).
549 * config.in: Rebuild with autoheader 2.59.
551 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
553 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
555 2004-07-30 Michal Ludvig <mludvig@suse.cz>
557 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
558 (GRPPADLCK2): New define.
559 (twobyte_has_modrm): True for 0xA6.
560 (grps): GRPPADLCK2 for opcode 0xA6.
562 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
564 Introduce SH2a support.
565 * sh-opc.h (arch_sh2a_base): Renumber.
566 (arch_sh2a_nofpu_base): Remove.
567 (arch_sh_base_mask): Adjust.
568 (arch_opann_mask): New.
569 (arch_sh2a, arch_sh2a_nofpu): Adjust.
570 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
571 (sh_table): Adjust whitespace.
572 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
573 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
574 instruction list throughout.
575 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
576 of arch_sh2a in instruction list throughout.
577 (arch_sh2e_up): Accomodate above changes.
578 (arch_sh2_up): Ditto.
579 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
580 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
581 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
582 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
583 * sh-opc.h (arch_sh2a_nofpu): New.
584 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
585 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
587 2004-01-20 DJ Delorie <dj@redhat.com>
588 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
589 2003-12-29 DJ Delorie <dj@redhat.com>
590 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
591 sh_opcode_info, sh_table): Add sh2a support.
592 (arch_op32): New, to tag 32-bit opcodes.
593 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
594 2003-12-02 Michael Snyder <msnyder@redhat.com>
595 * sh-opc.h (arch_sh2a): Add.
596 * sh-dis.c (arch_sh2a): Handle.
597 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
599 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
601 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
603 2004-07-22 Nick Clifton <nickc@redhat.com>
606 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
607 insns - this is done by objdump itself.
608 * h8500-dis.c (print_insn_h8500): Likewise.
610 2004-07-21 Jan Beulich <jbeulich@novell.com>
612 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
613 regardless of address size prefix in effect.
614 (ptr_reg): Size or address registers does not depend on rex64, but
615 on the presence of an address size override.
616 (OP_MMX): Use rex.x only for xmm registers.
617 (OP_EM): Use rex.z only for xmm registers.
619 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
621 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
622 move/branch operations to the bottom so that VR5400 multimedia
623 instructions take precedence in disassembly.
625 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
627 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
628 ISA-specific "break" encoding.
630 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
632 * arm-opc.h: Fix typo in comment.
634 2004-07-11 Andreas Schwab <schwab@suse.de>
636 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
638 2004-07-09 Andreas Schwab <schwab@suse.de>
640 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
642 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
644 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
645 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
646 (crx-dis.lo): New target.
647 (crx-opc.lo): Likewise.
648 * Makefile.in: Regenerate.
649 * configure.in: Handle bfd_crx_arch.
650 * configure: Regenerate.
651 * crx-dis.c: New file.
652 * crx-opc.c: New file.
653 * disassemble.c (ARCH_crx): Define.
654 (disassembler): Handle ARCH_crx.
656 2004-06-29 James E Wilson <wilson@specifixinc.com>
658 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
659 * ia64-asmtab.c: Regnerate.
661 2004-06-28 Alan Modra <amodra@bigpond.net.au>
663 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
664 (extract_fxm): Don't test dialect.
665 (XFXFXM_MASK): Include the power4 bit.
666 (XFXM): Add p4 param.
667 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
669 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
671 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
672 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
674 2004-06-26 Alan Modra <amodra@bigpond.net.au>
676 * ppc-opc.c (BH, XLBH_MASK): Define.
677 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
679 2004-06-24 Alan Modra <amodra@bigpond.net.au>
681 * i386-dis.c (x_mode): Comment.
682 (two_source_ops): File scope.
683 (float_mem): Correct fisttpll and fistpll.
684 (float_mem_mode): New table.
686 (OP_E): Correct intel mode PTR output.
687 (ptr_reg): Use open_char and close_char.
688 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
689 operands. Set two_source_ops.
691 2004-06-15 Alan Modra <amodra@bigpond.net.au>
693 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
694 instead of _raw_size.
696 2004-06-08 Jakub Jelinek <jakub@redhat.com>
698 * ia64-gen.c (in_iclass): Handle more postinc st
700 * ia64-asmtab.c: Rebuilt.
702 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
704 * s390-opc.txt: Correct architecture mask for some opcodes.
705 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
706 in the esa mode as well.
708 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
710 * sh-dis.c (target_arch): Make unsigned.
711 (print_insn_sh): Replace (most of) switch with a call to
712 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
713 * sh-opc.h: Redefine architecture flags values.
714 Add sh3-nommu architecture.
715 Reorganise <arch>_up macros so they make more visual sense.
716 (SH_MERGE_ARCH_SET): Define new macro.
717 (SH_VALID_BASE_ARCH_SET): Likewise.
718 (SH_VALID_MMU_ARCH_SET): Likewise.
719 (SH_VALID_CO_ARCH_SET): Likewise.
720 (SH_VALID_ARCH_SET): Likewise.
721 (SH_MERGE_ARCH_SET_VALID): Likewise.
722 (SH_ARCH_SET_HAS_FPU): Likewise.
723 (SH_ARCH_SET_HAS_DSP): Likewise.
724 (SH_ARCH_UNKNOWN_ARCH): Likewise.
725 (sh_get_arch_from_bfd_mach): Add prototype.
726 (sh_get_arch_up_from_bfd_mach): Likewise.
727 (sh_get_bfd_mach_from_arch_set): Likewise.
728 (sh_merge_bfd_arc): Likewise.
730 2004-05-24 Peter Barada <peter@the-baradas.com>
732 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
733 into new match_insn_m68k function. Loop over canidate
734 matches and select first that completely matches.
735 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
736 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
737 to verify addressing for MAC/EMAC.
738 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
739 reigster halves since 'fpu' and 'spl' look misleading.
740 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
741 * m68k-opc.c: Rearragne mac/emac cases to use longest for
742 first, tighten up match masks.
743 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
744 'size' from special case code in print_insn_m68k to
745 determine decode size of insns.
747 2004-05-19 Alan Modra <amodra@bigpond.net.au>
749 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
750 well as when -mpower4.
752 2004-05-13 Nick Clifton <nickc@redhat.com>
754 * po/fr.po: Updated French translation.
756 2004-05-05 Peter Barada <peter@the-baradas.com>
758 * m68k-dis.c(print_insn_m68k): Add new chips, use core
759 variants in arch_mask. Only set m68881/68851 for 68k chips.
760 * m68k-op.c: Switch from ColdFire chips to core variants.
762 2004-05-05 Alan Modra <amodra@bigpond.net.au>
765 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
767 2004-04-29 Ben Elliston <bje@au.ibm.com>
769 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
770 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
772 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
774 * sh-dis.c (print_insn_sh): Print the value in constant pool
775 as a symbol if it looks like a symbol.
777 2004-04-22 Peter Barada <peter@the-baradas.com>
779 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
780 appropriate ColdFire architectures.
781 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
783 Add EMAC instructions, fix MAC instructions. Remove
784 macmw/macml/msacmw/msacml instructions since mask addressing now
787 2004-04-20 Jakub Jelinek <jakub@redhat.com>
789 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
790 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
791 suffix. Use fmov*x macros, create all 3 fpsize variants in one
792 macro. Adjust all users.
794 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
796 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
799 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
801 * m32r-asm.c: Regenerate.
803 2004-03-29 Stan Shebs <shebs@apple.com>
805 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
808 2004-03-19 Alan Modra <amodra@bigpond.net.au>
810 * aclocal.m4: Regenerate.
811 * config.in: Regenerate.
812 * configure: Regenerate.
813 * po/POTFILES.in: Regenerate.
814 * po/opcodes.pot: Regenerate.
816 2004-03-16 Alan Modra <amodra@bigpond.net.au>
818 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
820 * ppc-opc.c (RA0): Define.
821 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
822 (RAOPT): Rename from RAO. Update all uses.
823 (powerpc_opcodes): Use RA0 as appropriate.
825 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
827 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
829 2004-03-15 Alan Modra <amodra@bigpond.net.au>
831 * sparc-dis.c (print_insn_sparc): Update getword prototype.
833 2004-03-12 Michal Ludvig <mludvig@suse.cz>
835 * i386-dis.c (GRPPLOCK): Delete.
836 (grps): Delete GRPPLOCK entry.
838 2004-03-12 Alan Modra <amodra@bigpond.net.au>
840 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
842 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
844 (dis386): Use NOP_Fixup on "nop".
845 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
846 (twobyte_has_modrm): Set for 0xa7.
847 (padlock_table): Delete. Move to..
848 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
850 (print_insn): Revert PADLOCK_SPECIAL code.
851 (OP_E): Delete sfence, lfence, mfence checks.
853 2004-03-12 Jakub Jelinek <jakub@redhat.com>
855 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
856 (INVLPG_Fixup): New function.
857 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
859 2004-03-12 Michal Ludvig <mludvig@suse.cz>
861 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
862 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
863 (padlock_table): New struct with PadLock instructions.
864 (print_insn): Handle PADLOCK_SPECIAL.
866 2004-03-12 Alan Modra <amodra@bigpond.net.au>
868 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
869 (OP_E): Twiddle clflush to sfence here.
871 2004-03-08 Nick Clifton <nickc@redhat.com>
873 * po/de.po: Updated German translation.
875 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
877 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
878 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
879 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
882 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
884 * frv-asm.c: Regenerate.
885 * frv-desc.c: Regenerate.
886 * frv-desc.h: Regenerate.
887 * frv-dis.c: Regenerate.
888 * frv-ibld.c: Regenerate.
889 * frv-opc.c: Regenerate.
890 * frv-opc.h: Regenerate.
892 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
894 * frv-desc.c, frv-opc.c: Regenerate.
896 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
898 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
900 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
902 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
903 Also correct mistake in the comment.
905 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
907 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
908 ensure that double registers have even numbers.
909 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
910 that reserved instruction 0xfffd does not decode the same
912 * sh-opc.h: Add REG_N_D nibble type and use it whereever
913 REG_N refers to a double register.
914 Add REG_N_B01 nibble type and use it instead of REG_NM
916 Adjust the bit patterns in a few comments.
918 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
920 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
922 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
924 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
926 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
928 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
930 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
932 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
933 mtivor32, mtivor33, mtivor34.
935 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
937 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
939 2004-02-10 Petko Manolov <petkan@nucleusys.com>
941 * arm-opc.h Maverick accumulator register opcode fixes.
943 2004-02-13 Ben Elliston <bje@wasabisystems.com>
945 * m32r-dis.c: Regenerate.
947 2004-01-27 Michael Snyder <msnyder@redhat.com>
949 * sh-opc.h (sh_table): "fsrra", not "fssra".
951 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
953 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
956 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
958 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
960 2004-01-19 Alan Modra <amodra@bigpond.net.au>
962 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
963 1. Don't print scale factor on AT&T mode when index missing.
965 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
967 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
968 when loaded into XR registers.
970 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
972 * frv-desc.h: Regenerate.
973 * frv-desc.c: Regenerate.
974 * frv-opc.c: Regenerate.
976 2004-01-13 Michael Snyder <msnyder@redhat.com>
978 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
980 2004-01-09 Paul Brook <paul@codesourcery.com>
982 * arm-opc.h (arm_opcodes): Move generic mcrr after known
985 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
987 * Makefile.am (libopcodes_la_DEPENDENCIES)
988 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
989 comment about the problem.
990 * Makefile.in: Regenerate.
992 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
994 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
995 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
996 cut&paste errors in shifting/truncating numerical operands.
997 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
998 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
999 (parse_uslo16): Likewise.
1000 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1001 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1002 (parse_s12): Likewise.
1003 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1004 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1005 (parse_uslo16): Likewise.
1006 (parse_uhi16): Parse gothi and gotfuncdeschi.
1007 (parse_d12): Parse got12 and gotfuncdesc12.
1008 (parse_s12): Likewise.
1010 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1012 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1013 instruction which looks similar to an 'rla' instruction.
1015 For older changes see ChangeLog-0203
1021 version-control: never