1 2019-11-14 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (opcode_modifiers): Add AnySize entry.
4 (operand_types): Remove AnySize entry.
5 * i386-opc.h (AnySize): Move between enums.
6 (struct i386_opcode_modifier): Add anysize field.
7 (OTUnused): Un-comment.
8 (union i386_operand_type): Remove anysize field.
9 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
10 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
11 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
13 * i386-tbl.h: Re-generate.
15 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
17 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
18 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
19 use the floating point register (FPR).
21 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
23 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
25 (is_mve_encoding_conflict): Update cmode conflict checks for
28 2019-11-12 Jan Beulich <jbeulich@suse.com>
30 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
32 (operand_types): Remove EsSeg entry.
33 (main): Replace stale use of OTMax.
34 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
35 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
37 (OTUnused): Comment out.
38 (union i386_operand_type): Remove esseg field.
39 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
40 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
41 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
42 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
43 * i386-init.h, i386-tbl.h: Re-generate.
45 2019-11-12 Jan Beulich <jbeulich@suse.com>
47 * i386-gen.c (operand_instances): Add RegB entry.
48 * i386-opc.h (enum operand_instance): Add RegB.
49 * i386-opc.tbl (RegC, RegD, RegB): Define.
50 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
51 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
52 monitorx, mwaitx): Drop ImmExt and convert encodings
54 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
55 (edx, rdx): Add Instance=RegD.
56 (ebx, rbx): Add Instance=RegB.
57 * i386-tbl.h: Re-generate.
59 2019-11-12 Jan Beulich <jbeulich@suse.com>
61 * i386-gen.c (operand_type_init): Adjust
62 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
63 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
64 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
65 (operand_instances): New.
66 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
67 (output_operand_type): New parameter "instance". Process it.
68 (process_i386_operand_type): New local variable "instance".
69 (main): Adjust static assertions.
70 * i386-opc.h (INSTANCE_WIDTH): Define.
71 (enum operand_instance): New.
72 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
73 (union i386_operand_type): Replace acc, inoutportreg, and
74 shiftcount by instance.
75 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
76 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
78 * i386-init.h, i386-tbl.h: Re-generate.
80 2019-11-11 Jan Beulich <jbeulich@suse.com>
82 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
83 smaxp/sminp entries' "tied_operand" field to 2.
85 2019-11-11 Jan Beulich <jbeulich@suse.com>
87 * aarch64-opc.c (operand_general_constraint_met_p): Replace
88 "index" local variable by that of the already existing "num".
90 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
93 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
94 * i386-tbl.h: Regenerated.
96 2019-11-08 Jan Beulich <jbeulich@suse.com>
98 * i386-gen.c (operand_type_init): Add Class= to
99 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
100 OPERAND_TYPE_REGBND entry.
101 (operand_classes): Add RegMask and RegBND entries.
102 (operand_types): Drop RegMask and RegBND entry.
103 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
104 (RegMask, RegBND): Delete.
105 (union i386_operand_type): Remove regmask and regbnd fields.
106 * i386-opc.tbl (RegMask, RegBND): Define.
107 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
109 * i386-init.h, i386-tbl.h: Re-generate.
111 2019-11-08 Jan Beulich <jbeulich@suse.com>
113 * i386-gen.c (operand_type_init): Add Class= to
114 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
115 OPERAND_TYPE_REGZMM entries.
116 (operand_classes): Add RegMMX and RegSIMD entries.
117 (operand_types): Drop RegMMX and RegSIMD entries.
118 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
119 (RegMMX, RegSIMD): Delete.
120 (union i386_operand_type): Remove regmmx and regsimd fields.
121 * i386-opc.tbl (RegMMX): Define.
122 (RegXMM, RegYMM, RegZMM): Add Class=.
123 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
125 * i386-init.h, i386-tbl.h: Re-generate.
127 2019-11-08 Jan Beulich <jbeulich@suse.com>
129 * i386-gen.c (operand_type_init): Add Class= to
130 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
132 (operand_classes): Add RegCR, RegDR, and RegTR entries.
133 (operand_types): Drop Control, Debug, and Test entries.
134 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
135 (Control, Debug, Test): Delete.
136 (union i386_operand_type): Remove control, debug, and test
138 * i386-opc.tbl (Control, Debug, Test): Define.
139 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
140 Class=RegDR, and Test by Class=RegTR.
141 * i386-init.h, i386-tbl.h: Re-generate.
143 2019-11-08 Jan Beulich <jbeulich@suse.com>
145 * i386-gen.c (operand_type_init): Add Class= to
146 OPERAND_TYPE_SREG entry.
147 (operand_classes): Add SReg entry.
148 (operand_types): Drop SReg entry.
149 * i386-opc.h (enum operand_class): Add SReg.
151 (union i386_operand_type): Remove sreg field.
152 * i386-opc.tbl (SReg): Define.
153 * i386-reg.tbl: Replace SReg by Class=SReg.
154 * i386-init.h, i386-tbl.h: Re-generate.
156 2019-11-08 Jan Beulich <jbeulich@suse.com>
158 * i386-gen.c (operand_type_init): Add Class=. New
159 OPERAND_TYPE_ANYIMM entry.
160 (operand_classes): New.
161 (operand_types): Drop Reg entry.
162 (output_operand_type): New parameter "class". Process it.
163 (process_i386_operand_type): New local variable "class".
164 (main): Adjust static assertions.
165 * i386-opc.h (CLASS_WIDTH): Define.
166 (enum operand_class): New.
167 (Reg): Replace by Class. Adjust comment.
168 (union i386_operand_type): Replace reg by class.
169 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
171 * i386-reg.tbl: Replace Reg by Class=Reg.
172 * i386-init.h: Re-generate.
174 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
176 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
177 (aarch64_opcode_table): Add data gathering hint mnemonic.
178 * opcodes/aarch64-dis-2.c: Account for new instruction.
180 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
182 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
185 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
187 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
188 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
189 aarch64_feature_f64mm): New feature sets.
190 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
191 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
193 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
195 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
196 (OP_SVE_QQQ): New qualifier.
197 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
198 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
199 the movprfx constraint.
200 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
201 (aarch64_opcode_table): Define new instructions smmla,
202 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
204 * aarch64-opc.c (operand_general_constraint_met_p): Handle
205 AARCH64_OPND_SVE_ADDR_RI_S4x32.
206 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
207 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
208 Account for new instructions.
209 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
211 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
213 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
214 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
216 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
218 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
219 (neon_opcodes): Add bfloat SIMD instructions.
220 (print_insn_coprocessor): Add new control character %b to print
221 condition code without checking cp_num.
222 (print_insn_neon): Account for BFloat16 instructions that have no
223 special top-byte handling.
225 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
226 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
228 * arm-dis.c (print_insn_coprocessor,
229 print_insn_generic_coprocessor): Create wrapper functions around
230 the implementation of the print_insn_coprocessor control codes.
231 (print_insn_coprocessor_1): Original print_insn_coprocessor
232 function that now takes which array to look at as an argument.
233 (print_insn_arm): Use both print_insn_coprocessor and
234 print_insn_generic_coprocessor.
235 (print_insn_thumb32): As above.
237 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
238 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
240 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
241 in reglane special case.
242 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
243 aarch64_find_next_opcode): Account for new instructions.
244 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
245 in reglane special case.
246 * aarch64-opc.c (struct operand_qualifier_data): Add data for
247 new AARCH64_OPND_QLF_S_2H qualifier.
248 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
249 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
250 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
252 (BFLOAT_SVE, BFLOAT): New feature set macros.
253 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
255 (aarch64_opcode_table): Define new instructions bfdot,
256 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
259 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
260 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
262 * aarch64-tbl.h (ARMV8_6): New macro.
264 2019-11-07 Jan Beulich <jbeulich@suse.com>
266 * i386-dis.c (prefix_table): Add mcommit.
267 (rm_table): Add rdpru.
268 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
269 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
270 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
271 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
272 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
273 * i386-opc.tbl (mcommit, rdpru): New.
274 * i386-init.h, i386-tbl.h: Re-generate.
276 2019-11-07 Jan Beulich <jbeulich@suse.com>
278 * i386-dis.c (OP_Mwait): Drop local variable "names", use
280 (OP_Monitor): Drop local variable "op1_names", re-purpose
281 "names" for it instead, and replace former "names" uses by
284 2019-11-07 Jan Beulich <jbeulich@suse.com>
287 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
289 * opcodes/i386-tbl.h: Re-generate.
291 2019-11-05 Jan Beulich <jbeulich@suse.com>
293 * i386-dis.c (OP_Mwaitx): Delete.
294 (prefix_table): Use OP_Mwait for mwaitx entry.
295 (OP_Mwait): Also handle mwaitx.
297 2019-11-05 Jan Beulich <jbeulich@suse.com>
299 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
300 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
301 (prefix_table): Add respective entries.
302 (rm_table): Link to those entries.
304 2019-11-05 Jan Beulich <jbeulich@suse.com>
306 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
307 (REG_0F1C_P_0_MOD_0): ... this.
308 (REG_0F1E_MOD_3): Rename to ...
309 (REG_0F1E_P_1_MOD_3): ... this.
310 (RM_0F01_REG_5): Rename to ...
311 (RM_0F01_REG_5_MOD_3): ... this.
312 (RM_0F01_REG_7): Rename to ...
313 (RM_0F01_REG_7_MOD_3): ... this.
314 (RM_0F1E_MOD_3_REG_7): Rename to ...
315 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
316 (RM_0FAE_REG_6): Rename to ...
317 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
318 (RM_0FAE_REG_7): Rename to ...
319 (RM_0FAE_REG_7_MOD_3): ... this.
320 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
321 (PREFIX_0F01_REG_5_MOD_0): ... this.
322 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
323 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
324 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
325 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
326 (PREFIX_0FAE_REG_0): Rename to ...
327 (PREFIX_0FAE_REG_0_MOD_3): ... this.
328 (PREFIX_0FAE_REG_1): Rename to ...
329 (PREFIX_0FAE_REG_1_MOD_3): ... this.
330 (PREFIX_0FAE_REG_2): Rename to ...
331 (PREFIX_0FAE_REG_2_MOD_3): ... this.
332 (PREFIX_0FAE_REG_3): Rename to ...
333 (PREFIX_0FAE_REG_3_MOD_3): ... this.
334 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
335 (PREFIX_0FAE_REG_4_MOD_0): ... this.
336 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
337 (PREFIX_0FAE_REG_4_MOD_3): ... this.
338 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
339 (PREFIX_0FAE_REG_5_MOD_0): ... this.
340 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
341 (PREFIX_0FAE_REG_5_MOD_3): ... this.
342 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
343 (PREFIX_0FAE_REG_6_MOD_0): ... this.
344 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
345 (PREFIX_0FAE_REG_6_MOD_3): ... this.
346 (PREFIX_0FAE_REG_7): Rename to ...
347 (PREFIX_0FAE_REG_7_MOD_0): ... this.
348 (PREFIX_MOD_0_0FC3): Rename to ...
349 (PREFIX_0FC3_MOD_0): ... this.
350 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
351 (PREFIX_0FC7_REG_6_MOD_0): ... this.
352 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
353 (PREFIX_0FC7_REG_6_MOD_3): ... this.
354 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
355 (PREFIX_0FC7_REG_7_MOD_3): ... this.
356 (reg_table, prefix_table, mod_table, rm_table): Adjust
359 2019-11-04 Nick Clifton <nickc@redhat.com>
361 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
362 of a v850 system register. Move the v850_sreg_names array into
364 (get_v850_reg_name): Likewise for ordinary register names.
365 (get_v850_vreg_name): Likewise for vector register names.
366 (get_v850_cc_name): Likewise for condition codes.
367 * get_v850_float_cc_name): Likewise for floating point condition
369 (get_v850_cacheop_name): Likewise for cache-ops.
370 (get_v850_prefop_name): Likewise for pref-ops.
371 (disassemble): Use the new accessor functions.
373 2019-10-30 Delia Burduv <delia.burduv@arm.com>
375 * aarch64-opc.c (print_immediate_offset_address): Don't print the
376 immediate for the writeback form of ldraa/ldrab if it is 0.
377 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
378 * aarch64-opc-2.c: Regenerated.
380 2019-10-30 Jan Beulich <jbeulich@suse.com>
382 * i386-gen.c (operand_type_shorthands): Delete.
383 (operand_type_init): Expand previous shorthands.
384 (set_bitfield_from_shorthand): Rename back to ...
385 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
386 of operand_type_init[].
387 (set_bitfield): Adjust call to the above function.
388 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
389 RegXMM, RegYMM, RegZMM): Define.
390 * i386-reg.tbl: Expand prior shorthands.
392 2019-10-30 Jan Beulich <jbeulich@suse.com>
394 * i386-gen.c (output_i386_opcode): Change order of fields
396 * i386-opc.h (struct insn_template): Move operands field.
397 Convert extension_opcode field to unsigned short.
398 * i386-tbl.h: Re-generate.
400 2019-10-30 Jan Beulich <jbeulich@suse.com>
402 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
404 * i386-opc.h (W): Extend comment.
405 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
406 general purpose variants not allowing for byte operands.
407 * i386-tbl.h: Re-generate.
409 2019-10-29 Nick Clifton <nickc@redhat.com>
411 * tic30-dis.c (print_branch): Correct size of operand array.
413 2019-10-29 Nick Clifton <nickc@redhat.com>
415 * d30v-dis.c (print_insn): Check that operand index is valid
416 before attempting to access the operands array.
418 2019-10-29 Nick Clifton <nickc@redhat.com>
420 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
421 locating the bit to be tested.
423 2019-10-29 Nick Clifton <nickc@redhat.com>
425 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
427 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
428 (print_insn_s12z): Check for illegal size values.
430 2019-10-28 Nick Clifton <nickc@redhat.com>
432 * csky-dis.c (csky_chars_to_number): Check for a negative
433 count. Use an unsigned integer to construct the return value.
435 2019-10-28 Nick Clifton <nickc@redhat.com>
437 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
438 operand buffer. Set value to 15 not 13.
439 (get_register_operand): Use OPERAND_BUFFER_LEN.
440 (get_indirect_operand): Likewise.
441 (print_two_operand): Likewise.
442 (print_three_operand): Likewise.
443 (print_oar_insn): Likewise.
445 2019-10-28 Nick Clifton <nickc@redhat.com>
447 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
448 (bit_extract_simple): Likewise.
449 (bit_copy): Likewise.
450 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
451 index_offset array are not accessed.
453 2019-10-28 Nick Clifton <nickc@redhat.com>
455 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
458 2019-10-25 Nick Clifton <nickc@redhat.com>
460 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
461 access to opcodes.op array element.
463 2019-10-23 Nick Clifton <nickc@redhat.com>
465 * rx-dis.c (get_register_name): Fix spelling typo in error
467 (get_condition_name, get_flag_name, get_double_register_name)
468 (get_double_register_high_name, get_double_register_low_name)
469 (get_double_control_register_name, get_double_condition_name)
470 (get_opsize_name, get_size_name): Likewise.
472 2019-10-22 Nick Clifton <nickc@redhat.com>
474 * rx-dis.c (get_size_name): New function. Provides safe
475 access to name array.
476 (get_opsize_name): Likewise.
477 (print_insn_rx): Use the accessor functions.
479 2019-10-16 Nick Clifton <nickc@redhat.com>
481 * rx-dis.c (get_register_name): New function. Provides safe
482 access to name array.
483 (get_condition_name, get_flag_name, get_double_register_name)
484 (get_double_register_high_name, get_double_register_low_name)
485 (get_double_control_register_name, get_double_condition_name):
487 (print_insn_rx): Use the accessor functions.
489 2019-10-09 Nick Clifton <nickc@redhat.com>
492 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
495 2019-10-07 Jan Beulich <jbeulich@suse.com>
497 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
498 (cmpsd): Likewise. Move EsSeg to other operand.
499 * opcodes/i386-tbl.h: Re-generate.
501 2019-09-23 Alan Modra <amodra@gmail.com>
503 * m68k-dis.c: Include cpu-m68k.h
505 2019-09-23 Alan Modra <amodra@gmail.com>
507 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
508 "elf/mips.h" earlier.
510 2018-09-20 Jan Beulich <jbeulich@suse.com>
513 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
515 * i386-tbl.h: Re-generate.
517 2019-09-18 Alan Modra <amodra@gmail.com>
519 * arc-ext.c: Update throughout for bfd section macro changes.
521 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
523 * Makefile.in: Re-generate.
524 * configure: Re-generate.
526 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
528 * riscv-opc.c (riscv_opcodes): Change subset field
529 to insn_class field for all instructions.
530 (riscv_insn_types): Likewise.
532 2019-09-16 Phil Blundell <pb@pbcl.net>
534 * configure: Regenerated.
536 2019-09-10 Miod Vallat <miod@online.fr>
539 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
541 2019-09-09 Phil Blundell <pb@pbcl.net>
543 binutils 2.33 branch created.
545 2019-09-03 Nick Clifton <nickc@redhat.com>
548 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
549 greater than zero before indexing via (bufcnt -1).
551 2019-09-03 Nick Clifton <nickc@redhat.com>
554 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
555 (MAX_SPEC_REG_NAME_LEN): Define.
556 (struct mmix_dis_info): Use defined constants for array lengths.
557 (get_reg_name): New function.
558 (get_sprec_reg_name): New function.
559 (print_insn_mmix): Use new functions.
561 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
563 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
564 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
565 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
567 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
569 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
570 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
571 (aarch64_sys_reg_supported_p): Update checks for the above.
573 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
575 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
576 cases MVE_SQRSHRL and MVE_UQRSHLL.
577 (print_insn_mve): Add case for specifier 'k' to check
578 specific bit of the instruction.
580 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
583 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
584 encountering an unknown machine type.
585 (print_insn_arc): Handle arc_insn_length returning 0. In error
586 cases return -1 rather than calling abort.
588 2019-08-07 Jan Beulich <jbeulich@suse.com>
590 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
591 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
593 * i386-tbl.h: Re-generate.
595 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
597 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
600 2019-07-30 Mel Chen <mel.chen@sifive.com>
602 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
603 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
605 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
608 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
610 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
611 and MPY class instructions.
612 (parse_option): Add nps400 option.
613 (print_arc_disassembler_options): Add nps400 info.
615 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
617 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
620 * arc-opc.c (RAD_CHK): Add.
621 * arc-tbl.h: Regenerate.
623 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
625 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
626 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
628 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
630 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
631 instructions as UNPREDICTABLE.
633 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
635 * bpf-desc.c: Regenerated.
637 2019-07-17 Jan Beulich <jbeulich@suse.com>
639 * i386-gen.c (static_assert): Define.
641 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
642 (Opcode_Modifier_Num): ... this.
645 2019-07-16 Jan Beulich <jbeulich@suse.com>
647 * i386-gen.c (operand_types): Move RegMem ...
648 (opcode_modifiers): ... here.
649 * i386-opc.h (RegMem): Move to opcode modifer enum.
650 (union i386_operand_type): Move regmem field ...
651 (struct i386_opcode_modifier): ... here.
652 * i386-opc.tbl (RegMem): Define.
653 (mov, movq): Move RegMem on segment, control, debug, and test
655 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
656 to non-SSE2AVX flavor.
657 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
658 Move RegMem on register only flavors. Drop IgnoreSize from
659 legacy encoding flavors.
660 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
662 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
663 register only flavors.
664 (vmovd): Move RegMem and drop IgnoreSize on register only
665 flavor. Change opcode and operand order to store form.
666 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
668 2019-07-16 Jan Beulich <jbeulich@suse.com>
670 * i386-gen.c (operand_type_init, operand_types): Replace SReg
672 * i386-opc.h (SReg2, SReg3): Replace by ...
674 (union i386_operand_type): Replace sreg fields.
675 * i386-opc.tbl (mov, ): Use SReg.
676 (push, pop): Likewies. Drop i386 and x86-64 specific segment
678 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
679 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
681 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
683 * bpf-desc.c: Regenerate.
684 * bpf-opc.c: Likewise.
685 * bpf-opc.h: Likewise.
687 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
689 * bpf-desc.c: Regenerate.
690 * bpf-opc.c: Likewise.
692 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
694 * arm-dis.c (print_insn_coprocessor): Rename index to
697 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
699 * riscv-opc.c (riscv_insn_types): Add r4 type.
701 * riscv-opc.c (riscv_insn_types): Add b and j type.
703 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
704 format for sb type and correct s type.
706 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
708 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
709 SVE FMOV alias of FCPY.
711 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
713 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
714 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
716 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
718 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
719 registers in an instruction prefixed by MOVPRFX.
721 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
723 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
724 sve_size_13 icode to account for variant behaviour of
726 * aarch64-dis-2.c: Regenerate.
727 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
728 sve_size_13 icode to account for variant behaviour of
730 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
731 (OP_SVE_VVV_Q_D): Add new qualifier.
732 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
733 (struct aarch64_opcode): Split pmull{t,b} into those requiring
736 2019-07-01 Jan Beulich <jbeulich@suse.com>
738 * opcodes/i386-gen.c (operand_type_init): Remove
739 OPERAND_TYPE_VEC_IMM4 entry.
740 (operand_types): Remove Vec_Imm4.
741 * opcodes/i386-opc.h (Vec_Imm4): Delete.
742 (union i386_operand_type): Remove vec_imm4.
743 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
744 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
746 2019-07-01 Jan Beulich <jbeulich@suse.com>
748 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
749 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
750 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
751 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
752 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
753 monitorx, mwaitx): Drop ImmExt from operand-less forms.
754 * i386-tbl.h: Re-generate.
756 2019-07-01 Jan Beulich <jbeulich@suse.com>
758 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
760 * i386-tbl.h: Re-generate.
762 2019-07-01 Jan Beulich <jbeulich@suse.com>
764 * i386-opc.tbl (C): New.
765 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
766 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
767 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
768 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
769 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
770 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
771 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
772 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
773 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
774 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
775 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
776 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
777 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
778 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
779 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
780 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
781 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
782 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
783 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
784 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
785 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
786 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
787 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
788 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
789 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
790 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
792 * i386-tbl.h: Re-generate.
794 2019-07-01 Jan Beulich <jbeulich@suse.com>
796 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
798 * i386-tbl.h: Re-generate.
800 2019-07-01 Jan Beulich <jbeulich@suse.com>
802 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
803 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
804 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
805 * i386-tbl.h: Re-generate.
807 2019-07-01 Jan Beulich <jbeulich@suse.com>
809 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
810 Disp8MemShift from register only templates.
811 * i386-tbl.h: Re-generate.
813 2019-07-01 Jan Beulich <jbeulich@suse.com>
815 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
816 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
817 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
818 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
819 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
820 EVEX_W_0F11_P_3_M_1): Delete.
821 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
822 EVEX_W_0F11_P_3): New.
823 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
824 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
825 MOD_EVEX_0F11_PREFIX_3 table entries.
826 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
827 PREFIX_EVEX_0F11 table entries.
828 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
829 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
830 EVEX_W_0F11_P_3_M_{0,1} table entries.
832 2019-07-01 Jan Beulich <jbeulich@suse.com>
834 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
837 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
840 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
841 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
842 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
843 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
844 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
845 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
846 EVEX_LEN_0F38C7_R_6_P_2_W_1.
847 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
848 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
849 PREFIX_EVEX_0F38C6_REG_6 entries.
850 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
851 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
852 EVEX_W_0F38C7_R_6_P_2 entries.
853 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
854 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
855 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
856 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
857 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
858 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
859 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
861 2019-06-27 Jan Beulich <jbeulich@suse.com>
863 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
864 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
865 VEX_LEN_0F2D_P_3): Delete.
866 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
867 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
868 (prefix_table): ... here.
870 2019-06-27 Jan Beulich <jbeulich@suse.com>
872 * i386-dis.c (Iq): Delete.
874 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
876 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
877 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
878 (OP_E_memory): Also honor needindex when deciding whether an
879 address size prefix needs printing.
880 (OP_I): Remove handling of q_mode. Add handling of d_mode.
882 2019-06-26 Jim Wilson <jimw@sifive.com>
885 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
886 Set info->display_endian to info->endian_code.
888 2019-06-25 Jan Beulich <jbeulich@suse.com>
890 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
891 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
892 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
893 OPERAND_TYPE_ACC64 entries.
894 * i386-init.h: Re-generate.
896 2019-06-25 Jan Beulich <jbeulich@suse.com>
898 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
900 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
902 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
904 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
905 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
907 2019-06-25 Jan Beulich <jbeulich@suse.com>
909 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
912 2019-06-25 Jan Beulich <jbeulich@suse.com>
914 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
915 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
917 * i386-opc.tbl (movnti): Add IgnoreSize.
918 * i386-tbl.h: Re-generate.
920 2019-06-25 Jan Beulich <jbeulich@suse.com>
922 * i386-opc.tbl (and): Mark Imm8S form for optimization.
923 * i386-tbl.h: Re-generate.
925 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
927 * i386-dis-evex.h: Break into ...
928 * i386-dis-evex-len.h: New file.
929 * i386-dis-evex-mod.h: Likewise.
930 * i386-dis-evex-prefix.h: Likewise.
931 * i386-dis-evex-reg.h: Likewise.
932 * i386-dis-evex-w.h: Likewise.
933 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
934 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
937 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
940 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
941 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
943 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
944 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
945 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
946 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
947 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
948 EVEX_LEN_0F385B_P_2_W_1.
949 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
950 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
951 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
952 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
953 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
954 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
955 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
956 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
957 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
958 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
960 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
963 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
964 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
965 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
966 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
967 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
968 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
969 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
970 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
971 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
972 EVEX_LEN_0F3A43_P_2_W_1.
973 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
974 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
975 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
976 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
977 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
978 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
979 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
980 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
981 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
982 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
983 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
984 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
986 2019-06-14 Nick Clifton <nickc@redhat.com>
988 * po/fr.po; Updated French translation.
990 2019-06-13 Stafford Horne <shorne@gmail.com>
992 * or1k-asm.c: Regenerated.
993 * or1k-desc.c: Regenerated.
994 * or1k-desc.h: Regenerated.
995 * or1k-dis.c: Regenerated.
996 * or1k-ibld.c: Regenerated.
997 * or1k-opc.c: Regenerated.
998 * or1k-opc.h: Regenerated.
999 * or1k-opinst.c: Regenerated.
1001 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1003 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1005 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1008 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1009 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1010 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1011 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1012 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1013 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1014 EVEX_LEN_0F3A1B_P_2_W_1.
1015 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1016 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1017 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1018 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1019 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1020 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1021 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1022 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1024 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1027 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1028 EVEX.vvvv when disassembling VEX and EVEX instructions.
1029 (OP_VEX): Set vex.register_specifier to 0 after readding
1030 vex.register_specifier.
1031 (OP_Vex_2src_1): Likewise.
1032 (OP_Vex_2src_2): Likewise.
1033 (OP_LWP_E): Likewise.
1034 (OP_EX_Vex): Don't check vex.register_specifier.
1035 (OP_XMM_Vex): Likewise.
1037 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1038 Lili Cui <lili.cui@intel.com>
1040 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1041 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1043 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1044 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1045 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1046 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1047 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1048 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1049 * i386-init.h: Regenerated.
1050 * i386-tbl.h: Likewise.
1052 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1053 Lili Cui <lili.cui@intel.com>
1055 * doc/c-i386.texi: Document enqcmd.
1056 * testsuite/gas/i386/enqcmd-intel.d: New file.
1057 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1058 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1059 * testsuite/gas/i386/enqcmd.d: Likewise.
1060 * testsuite/gas/i386/enqcmd.s: Likewise.
1061 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1062 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1063 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1064 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1065 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1066 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1067 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1070 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1072 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1074 2019-06-03 Alan Modra <amodra@gmail.com>
1076 * ppc-dis.c (prefix_opcd_indices): Correct size.
1078 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1081 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1083 * i386-tbl.h: Regenerated.
1085 2019-05-24 Alan Modra <amodra@gmail.com>
1087 * po/POTFILES.in: Regenerate.
1089 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1090 Alan Modra <amodra@gmail.com>
1092 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1093 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1094 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1095 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1096 XTOP>): Define and add entries.
1097 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1098 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1099 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1100 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1102 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1103 Alan Modra <amodra@gmail.com>
1105 * ppc-dis.c (ppc_opts): Add "future" entry.
1106 (PREFIX_OPCD_SEGS): Define.
1107 (prefix_opcd_indices): New array.
1108 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1109 (lookup_prefix): New function.
1110 (print_insn_powerpc): Handle 64-bit prefix instructions.
1111 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1112 (PMRR, POWERXX): Define.
1113 (prefix_opcodes): New instruction table.
1114 (prefix_num_opcodes): New constant.
1116 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1118 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1119 * configure: Regenerated.
1120 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1122 (HFILES): Add bpf-desc.h and bpf-opc.h.
1123 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1124 bpf-ibld.c and bpf-opc.c.
1126 * Makefile.in: Regenerated.
1127 * disassemble.c (ARCH_bpf): Define.
1128 (disassembler): Add case for bfd_arch_bpf.
1129 (disassemble_init_for_target): Likewise.
1130 (enum epbf_isa_attr): Define.
1131 * disassemble.h: extern print_insn_bpf.
1132 * bpf-asm.c: Generated.
1133 * bpf-opc.h: Likewise.
1134 * bpf-opc.c: Likewise.
1135 * bpf-ibld.c: Likewise.
1136 * bpf-dis.c: Likewise.
1137 * bpf-desc.h: Likewise.
1138 * bpf-desc.c: Likewise.
1140 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1142 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1143 and VMSR with the new operands.
1145 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1147 * arm-dis.c (enum mve_instructions): New enum
1148 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1150 (mve_opcodes): New instructions as above.
1151 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1153 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1155 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1157 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1158 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1159 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1160 uqshl, urshrl and urshr.
1161 (is_mve_okay_in_it): Add new instructions to TRUE list.
1162 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1163 (print_insn_mve): Updated to accept new %j,
1164 %<bitfield>m and %<bitfield>n patterns.
1166 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1168 * mips-opc.c (mips_builtin_opcodes): Change source register
1169 constraint for DAUI.
1171 2019-05-20 Nick Clifton <nickc@redhat.com>
1173 * po/fr.po: Updated French translation.
1175 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1176 Michael Collison <michael.collison@arm.com>
1178 * arm-dis.c (thumb32_opcodes): Add new instructions.
1179 (enum mve_instructions): Likewise.
1180 (enum mve_undefined): Add new reasons.
1181 (is_mve_encoding_conflict): Handle new instructions.
1182 (is_mve_undefined): Likewise.
1183 (is_mve_unpredictable): Likewise.
1184 (print_mve_undefined): Likewise.
1185 (print_mve_size): Likewise.
1187 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1188 Michael Collison <michael.collison@arm.com>
1190 * arm-dis.c (thumb32_opcodes): Add new instructions.
1191 (enum mve_instructions): Likewise.
1192 (is_mve_encoding_conflict): Handle new instructions.
1193 (is_mve_undefined): Likewise.
1194 (is_mve_unpredictable): Likewise.
1195 (print_mve_size): Likewise.
1197 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1198 Michael Collison <michael.collison@arm.com>
1200 * arm-dis.c (thumb32_opcodes): Add new instructions.
1201 (enum mve_instructions): Likewise.
1202 (is_mve_encoding_conflict): Likewise.
1203 (is_mve_unpredictable): Likewise.
1204 (print_mve_size): Likewise.
1206 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1207 Michael Collison <michael.collison@arm.com>
1209 * arm-dis.c (thumb32_opcodes): Add new instructions.
1210 (enum mve_instructions): Likewise.
1211 (is_mve_encoding_conflict): Handle new instructions.
1212 (is_mve_undefined): Likewise.
1213 (is_mve_unpredictable): Likewise.
1214 (print_mve_size): Likewise.
1216 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1217 Michael Collison <michael.collison@arm.com>
1219 * arm-dis.c (thumb32_opcodes): Add new instructions.
1220 (enum mve_instructions): Likewise.
1221 (is_mve_encoding_conflict): Handle new instructions.
1222 (is_mve_undefined): Likewise.
1223 (is_mve_unpredictable): Likewise.
1224 (print_mve_size): Likewise.
1225 (print_insn_mve): Likewise.
1227 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1228 Michael Collison <michael.collison@arm.com>
1230 * arm-dis.c (thumb32_opcodes): Add new instructions.
1231 (print_insn_thumb32): Handle new instructions.
1233 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1234 Michael Collison <michael.collison@arm.com>
1236 * arm-dis.c (enum mve_instructions): Add new instructions.
1237 (enum mve_undefined): Add new reasons.
1238 (is_mve_encoding_conflict): Handle new instructions.
1239 (is_mve_undefined): Likewise.
1240 (is_mve_unpredictable): Likewise.
1241 (print_mve_undefined): Likewise.
1242 (print_mve_size): Likewise.
1243 (print_mve_shift_n): Likewise.
1244 (print_insn_mve): Likewise.
1246 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1247 Michael Collison <michael.collison@arm.com>
1249 * arm-dis.c (enum mve_instructions): Add new instructions.
1250 (is_mve_encoding_conflict): Handle new instructions.
1251 (is_mve_unpredictable): Likewise.
1252 (print_mve_rotate): Likewise.
1253 (print_mve_size): Likewise.
1254 (print_insn_mve): Likewise.
1256 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1257 Michael Collison <michael.collison@arm.com>
1259 * arm-dis.c (enum mve_instructions): Add new instructions.
1260 (is_mve_encoding_conflict): Handle new instructions.
1261 (is_mve_unpredictable): Likewise.
1262 (print_mve_size): Likewise.
1263 (print_insn_mve): Likewise.
1265 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1266 Michael Collison <michael.collison@arm.com>
1268 * arm-dis.c (enum mve_instructions): Add new instructions.
1269 (enum mve_undefined): Add new reasons.
1270 (is_mve_encoding_conflict): Handle new instructions.
1271 (is_mve_undefined): Likewise.
1272 (is_mve_unpredictable): Likewise.
1273 (print_mve_undefined): Likewise.
1274 (print_mve_size): Likewise.
1275 (print_insn_mve): Likewise.
1277 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1278 Michael Collison <michael.collison@arm.com>
1280 * arm-dis.c (enum mve_instructions): Add new instructions.
1281 (is_mve_encoding_conflict): Handle new instructions.
1282 (is_mve_undefined): Likewise.
1283 (is_mve_unpredictable): Likewise.
1284 (print_mve_size): Likewise.
1285 (print_insn_mve): Likewise.
1287 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1288 Michael Collison <michael.collison@arm.com>
1290 * arm-dis.c (enum mve_instructions): Add new instructions.
1291 (enum mve_unpredictable): Add new reasons.
1292 (enum mve_undefined): Likewise.
1293 (is_mve_okay_in_it): Handle new isntructions.
1294 (is_mve_encoding_conflict): Likewise.
1295 (is_mve_undefined): Likewise.
1296 (is_mve_unpredictable): Likewise.
1297 (print_mve_vmov_index): Likewise.
1298 (print_simd_imm8): Likewise.
1299 (print_mve_undefined): Likewise.
1300 (print_mve_unpredictable): Likewise.
1301 (print_mve_size): Likewise.
1302 (print_insn_mve): Likewise.
1304 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1305 Michael Collison <michael.collison@arm.com>
1307 * arm-dis.c (enum mve_instructions): Add new instructions.
1308 (enum mve_unpredictable): Add new reasons.
1309 (enum mve_undefined): Likewise.
1310 (is_mve_encoding_conflict): Handle new instructions.
1311 (is_mve_undefined): Likewise.
1312 (is_mve_unpredictable): Likewise.
1313 (print_mve_undefined): Likewise.
1314 (print_mve_unpredictable): Likewise.
1315 (print_mve_rounding_mode): Likewise.
1316 (print_mve_vcvt_size): Likewise.
1317 (print_mve_size): Likewise.
1318 (print_insn_mve): Likewise.
1320 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1321 Michael Collison <michael.collison@arm.com>
1323 * arm-dis.c (enum mve_instructions): Add new instructions.
1324 (enum mve_unpredictable): Add new reasons.
1325 (enum mve_undefined): Likewise.
1326 (is_mve_undefined): Handle new instructions.
1327 (is_mve_unpredictable): Likewise.
1328 (print_mve_undefined): Likewise.
1329 (print_mve_unpredictable): Likewise.
1330 (print_mve_size): Likewise.
1331 (print_insn_mve): Likewise.
1333 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1334 Michael Collison <michael.collison@arm.com>
1336 * arm-dis.c (enum mve_instructions): Add new instructions.
1337 (enum mve_undefined): Add new reasons.
1338 (insns): Add new instructions.
1339 (is_mve_encoding_conflict):
1340 (print_mve_vld_str_addr): New print function.
1341 (is_mve_undefined): Handle new instructions.
1342 (is_mve_unpredictable): Likewise.
1343 (print_mve_undefined): Likewise.
1344 (print_mve_size): Likewise.
1345 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1346 (print_insn_mve): Handle new operands.
1348 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1349 Michael Collison <michael.collison@arm.com>
1351 * arm-dis.c (enum mve_instructions): Add new instructions.
1352 (enum mve_unpredictable): Add new reasons.
1353 (is_mve_encoding_conflict): Handle new instructions.
1354 (is_mve_unpredictable): Likewise.
1355 (mve_opcodes): Add new instructions.
1356 (print_mve_unpredictable): Handle new reasons.
1357 (print_mve_register_blocks): New print function.
1358 (print_mve_size): Handle new instructions.
1359 (print_insn_mve): Likewise.
1361 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1362 Michael Collison <michael.collison@arm.com>
1364 * arm-dis.c (enum mve_instructions): Add new instructions.
1365 (enum mve_unpredictable): Add new reasons.
1366 (enum mve_undefined): Likewise.
1367 (is_mve_encoding_conflict): Handle new instructions.
1368 (is_mve_undefined): Likewise.
1369 (is_mve_unpredictable): Likewise.
1370 (coprocessor_opcodes): Move NEON VDUP from here...
1371 (neon_opcodes): ... to here.
1372 (mve_opcodes): Add new instructions.
1373 (print_mve_undefined): Handle new reasons.
1374 (print_mve_unpredictable): Likewise.
1375 (print_mve_size): Handle new instructions.
1376 (print_insn_neon): Handle vdup.
1377 (print_insn_mve): Handle new operands.
1379 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1380 Michael Collison <michael.collison@arm.com>
1382 * arm-dis.c (enum mve_instructions): Add new instructions.
1383 (enum mve_unpredictable): Add new values.
1384 (mve_opcodes): Add new instructions.
1385 (vec_condnames): New array with vector conditions.
1386 (mve_predicatenames): New array with predicate suffixes.
1387 (mve_vec_sizename): New array with vector sizes.
1388 (enum vpt_pred_state): New enum with vector predication states.
1389 (struct vpt_block): New struct type for vpt blocks.
1390 (vpt_block_state): Global struct to keep track of state.
1391 (mve_extract_pred_mask): New helper function.
1392 (num_instructions_vpt_block): Likewise.
1393 (mark_outside_vpt_block): Likewise.
1394 (mark_inside_vpt_block): Likewise.
1395 (invert_next_predicate_state): Likewise.
1396 (update_next_predicate_state): Likewise.
1397 (update_vpt_block_state): Likewise.
1398 (is_vpt_instruction): Likewise.
1399 (is_mve_encoding_conflict): Add entries for new instructions.
1400 (is_mve_unpredictable): Likewise.
1401 (print_mve_unpredictable): Handle new cases.
1402 (print_instruction_predicate): Likewise.
1403 (print_mve_size): New function.
1404 (print_vec_condition): New function.
1405 (print_insn_mve): Handle vpt blocks and new print operands.
1407 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1409 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1410 8, 14 and 15 for Armv8.1-M Mainline.
1412 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1413 Michael Collison <michael.collison@arm.com>
1415 * arm-dis.c (enum mve_instructions): New enum.
1416 (enum mve_unpredictable): Likewise.
1417 (enum mve_undefined): Likewise.
1418 (struct mopcode32): New struct.
1419 (is_mve_okay_in_it): New function.
1420 (is_mve_architecture): Likewise.
1421 (arm_decode_field): Likewise.
1422 (arm_decode_field_multiple): Likewise.
1423 (is_mve_encoding_conflict): Likewise.
1424 (is_mve_undefined): Likewise.
1425 (is_mve_unpredictable): Likewise.
1426 (print_mve_undefined): Likewise.
1427 (print_mve_unpredictable): Likewise.
1428 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1429 (print_insn_mve): New function.
1430 (print_insn_thumb32): Handle MVE architecture.
1431 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1433 2019-05-10 Nick Clifton <nickc@redhat.com>
1436 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1437 end of the table prematurely.
1439 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1441 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1444 2019-05-11 Alan Modra <amodra@gmail.com>
1446 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1447 when -Mraw is in effect.
1449 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1451 * aarch64-dis-2.c: Regenerate.
1452 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1453 (OP_SVE_BBB): New variant set.
1454 (OP_SVE_DDDD): New variant set.
1455 (OP_SVE_HHH): New variant set.
1456 (OP_SVE_HHHU): New variant set.
1457 (OP_SVE_SSS): New variant set.
1458 (OP_SVE_SSSU): New variant set.
1459 (OP_SVE_SHH): New variant set.
1460 (OP_SVE_SBBU): New variant set.
1461 (OP_SVE_DSS): New variant set.
1462 (OP_SVE_DHHU): New variant set.
1463 (OP_SVE_VMV_HSD_BHS): New variant set.
1464 (OP_SVE_VVU_HSD_BHS): New variant set.
1465 (OP_SVE_VVVU_SD_BH): New variant set.
1466 (OP_SVE_VVVU_BHSD): New variant set.
1467 (OP_SVE_VVV_QHD_DBS): New variant set.
1468 (OP_SVE_VVV_HSD_BHS): New variant set.
1469 (OP_SVE_VVV_HSD_BHS2): New variant set.
1470 (OP_SVE_VVV_BHS_HSD): New variant set.
1471 (OP_SVE_VV_BHS_HSD): New variant set.
1472 (OP_SVE_VVV_SD): New variant set.
1473 (OP_SVE_VVU_BHS_HSD): New variant set.
1474 (OP_SVE_VZVV_SD): New variant set.
1475 (OP_SVE_VZVV_BH): New variant set.
1476 (OP_SVE_VZV_SD): New variant set.
1477 (aarch64_opcode_table): Add sve2 instructions.
1479 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1481 * aarch64-asm-2.c: Regenerated.
1482 * aarch64-dis-2.c: Regenerated.
1483 * aarch64-opc-2.c: Regenerated.
1484 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1485 for SVE_SHLIMM_UNPRED_22.
1486 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1487 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1490 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1492 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1493 sve_size_tsz_bhs iclass encode.
1494 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1495 sve_size_tsz_bhs iclass decode.
1497 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1499 * aarch64-asm-2.c: Regenerated.
1500 * aarch64-dis-2.c: Regenerated.
1501 * aarch64-opc-2.c: Regenerated.
1502 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1503 for SVE_Zm4_11_INDEX.
1504 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1505 (fields): Handle SVE_i2h field.
1506 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1507 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1509 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1511 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1512 sve_shift_tsz_bhsd iclass encode.
1513 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1514 sve_shift_tsz_bhsd iclass decode.
1516 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1518 * aarch64-asm-2.c: Regenerated.
1519 * aarch64-dis-2.c: Regenerated.
1520 * aarch64-opc-2.c: Regenerated.
1521 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1522 (aarch64_encode_variant_using_iclass): Handle
1523 sve_shift_tsz_hsd iclass encode.
1524 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1525 sve_shift_tsz_hsd iclass decode.
1526 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1527 for SVE_SHRIMM_UNPRED_22.
1528 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1529 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1532 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1534 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1535 sve_size_013 iclass encode.
1536 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1537 sve_size_013 iclass decode.
1539 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1541 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1542 sve_size_bh iclass encode.
1543 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1544 sve_size_bh iclass decode.
1546 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1548 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1549 sve_size_sd2 iclass encode.
1550 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1551 sve_size_sd2 iclass decode.
1552 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1553 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1555 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1557 * aarch64-asm-2.c: Regenerated.
1558 * aarch64-dis-2.c: Regenerated.
1559 * aarch64-opc-2.c: Regenerated.
1560 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1562 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1563 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1565 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1567 * aarch64-asm-2.c: Regenerated.
1568 * aarch64-dis-2.c: Regenerated.
1569 * aarch64-opc-2.c: Regenerated.
1570 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1571 for SVE_Zm3_11_INDEX.
1572 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1573 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1574 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1576 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1578 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1580 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1581 sve_size_hsd2 iclass encode.
1582 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1583 sve_size_hsd2 iclass decode.
1584 * aarch64-opc.c (fields): Handle SVE_size field.
1585 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1587 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1589 * aarch64-asm-2.c: Regenerated.
1590 * aarch64-dis-2.c: Regenerated.
1591 * aarch64-opc-2.c: Regenerated.
1592 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1594 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1595 (fields): Handle SVE_rot3 field.
1596 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1597 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1599 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1601 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1604 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1607 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1608 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1609 aarch64_feature_sve2bitperm): New feature sets.
1610 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1611 for feature set addresses.
1612 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1613 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1615 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1616 Faraz Shahbazker <fshahbazker@wavecomp.com>
1618 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1619 argument and set ASE_EVA_R6 appropriately.
1620 (set_default_mips_dis_options): Pass ISA to above.
1621 (parse_mips_dis_option): Likewise.
1622 * mips-opc.c (EVAR6): New macro.
1623 (mips_builtin_opcodes): Add llwpe, scwpe.
1625 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1627 * aarch64-asm-2.c: Regenerated.
1628 * aarch64-dis-2.c: Regenerated.
1629 * aarch64-opc-2.c: Regenerated.
1630 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1631 AARCH64_OPND_TME_UIMM16.
1632 (aarch64_print_operand): Likewise.
1633 * aarch64-tbl.h (QL_IMM_NIL): New.
1636 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1638 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1640 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1642 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1643 Faraz Shahbazker <fshahbazker@wavecomp.com>
1645 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1647 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1649 * s12z-opc.h: Add extern "C" bracketing to help
1650 users who wish to use this interface in c++ code.
1652 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1654 * s12z-opc.c (bm_decode): Handle bit map operations with the
1657 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1659 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1660 specifier. Add entries for VLDR and VSTR of system registers.
1661 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1662 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1663 of %J and %K format specifier.
1665 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1667 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1668 Add new entries for VSCCLRM instruction.
1669 (print_insn_coprocessor): Handle new %C format control code.
1671 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1673 * arm-dis.c (enum isa): New enum.
1674 (struct sopcode32): New structure.
1675 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1676 set isa field of all current entries to ANY.
1677 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1678 Only match an entry if its isa field allows the current mode.
1680 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1682 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1684 (print_insn_thumb32): Add logic to print %n CLRM register list.
1686 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1688 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1691 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1693 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1694 (print_insn_thumb32): Edit the switch case for %Z.
1696 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1698 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1700 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1702 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1704 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1706 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1708 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1710 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1711 Arm register with r13 and r15 unpredictable.
1712 (thumb32_opcodes): New instructions for bfx and bflx.
1714 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1716 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1718 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1720 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1722 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1724 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1726 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1728 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1730 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1732 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1733 "optr". ("operator" is a reserved word in c++).
1735 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1737 * aarch64-opc.c (aarch64_print_operand): Add case for
1739 (verify_constraints): Likewise.
1740 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1741 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1742 to accept Rt|SP as first operand.
1743 (AARCH64_OPERANDS): Add new Rt_SP.
1744 * aarch64-asm-2.c: Regenerated.
1745 * aarch64-dis-2.c: Regenerated.
1746 * aarch64-opc-2.c: Regenerated.
1748 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1750 * aarch64-asm-2.c: Regenerated.
1751 * aarch64-dis-2.c: Likewise.
1752 * aarch64-opc-2.c: Likewise.
1753 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1755 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1757 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1759 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1761 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1762 * i386-init.h: Regenerated.
1764 2019-04-07 Alan Modra <amodra@gmail.com>
1766 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1767 op_separator to control printing of spaces, comma and parens
1768 rather than need_comma, need_paren and spaces vars.
1770 2019-04-07 Alan Modra <amodra@gmail.com>
1773 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1774 (print_insn_neon, print_insn_arm): Likewise.
1776 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1778 * i386-dis-evex.h (evex_table): Updated to support BF16
1780 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1781 and EVEX_W_0F3872_P_3.
1782 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1783 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1784 * i386-opc.h (enum): Add CpuAVX512_BF16.
1785 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1786 * i386-opc.tbl: Add AVX512 BF16 instructions.
1787 * i386-init.h: Regenerated.
1788 * i386-tbl.h: Likewise.
1790 2019-04-05 Alan Modra <amodra@gmail.com>
1792 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1793 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1794 to favour printing of "-" branch hint when using the "y" bit.
1795 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1797 2019-04-05 Alan Modra <amodra@gmail.com>
1799 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1800 opcode until first operand is output.
1802 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1805 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1806 (valid_bo_post_v2): Add support for 'at' branch hints.
1807 (insert_bo): Only error on branch on ctr.
1808 (get_bo_hint_mask): New function.
1809 (insert_boe): Add new 'branch_taken' formal argument. Add support
1810 for inserting 'at' branch hints.
1811 (extract_boe): Add new 'branch_taken' formal argument. Add support
1812 for extracting 'at' branch hints.
1813 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1814 (BOE): Delete operand.
1815 (BOM, BOP): New operands.
1817 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1818 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1819 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1820 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1821 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1822 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1823 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1824 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1825 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1826 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1827 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1828 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1829 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1830 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1831 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1832 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1833 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1834 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1835 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1836 bttarl+>: New extended mnemonics.
1838 2019-03-28 Alan Modra <amodra@gmail.com>
1841 * ppc-opc.c (BTF): Define.
1842 (powerpc_opcodes): Use for mtfsb*.
1843 * ppc-dis.c (print_insn_powerpc): Print fields with both
1844 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1846 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1848 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1849 (mapping_symbol_for_insn): Implement new algorithm.
1850 (print_insn): Remove duplicate code.
1852 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1854 * aarch64-dis.c (print_insn_aarch64):
1857 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1859 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1862 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1864 * aarch64-dis.c (last_stop_offset): New.
1865 (print_insn_aarch64): Use stop_offset.
1867 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1870 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1872 * i386-init.h: Regenerated.
1874 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1877 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1878 vmovdqu16, vmovdqu32 and vmovdqu64.
1879 * i386-tbl.h: Regenerated.
1881 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1883 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1884 from vstrszb, vstrszh, and vstrszf.
1886 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1888 * s390-opc.txt: Add instruction descriptions.
1890 2019-02-08 Jim Wilson <jimw@sifive.com>
1892 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1895 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1897 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1899 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1902 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1903 * aarch64-opc.c (verify_elem_sd): New.
1904 (fields): Add FLD_sz entr.
1905 * aarch64-tbl.h (_SIMD_INSN): New.
1906 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1907 fmulx scalar and vector by element isns.
1909 2019-02-07 Nick Clifton <nickc@redhat.com>
1911 * po/sv.po: Updated Swedish translation.
1913 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1915 * s390-mkopc.c (main): Accept arch13 as cpu string.
1916 * s390-opc.c: Add new instruction formats and instruction opcode
1918 * s390-opc.txt: Add new arch13 instructions.
1920 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1922 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1923 (aarch64_opcode): Change encoding for stg, stzg
1925 * aarch64-asm-2.c: Regenerated.
1926 * aarch64-dis-2.c: Regenerated.
1927 * aarch64-opc-2.c: Regenerated.
1929 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1931 * aarch64-asm-2.c: Regenerated.
1932 * aarch64-dis-2.c: Likewise.
1933 * aarch64-opc-2.c: Likewise.
1934 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1936 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1937 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1939 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1940 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1941 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1942 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1943 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1944 case for ldstgv_indexed.
1945 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1946 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1947 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1948 * aarch64-asm-2.c: Regenerated.
1949 * aarch64-dis-2.c: Regenerated.
1950 * aarch64-opc-2.c: Regenerated.
1952 2019-01-23 Nick Clifton <nickc@redhat.com>
1954 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1956 2019-01-21 Nick Clifton <nickc@redhat.com>
1958 * po/de.po: Updated German translation.
1959 * po/uk.po: Updated Ukranian translation.
1961 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1962 * mips-dis.c (mips_arch_choices): Fix typo in
1963 gs464, gs464e and gs264e descriptors.
1965 2019-01-19 Nick Clifton <nickc@redhat.com>
1967 * configure: Regenerate.
1968 * po/opcodes.pot: Regenerate.
1970 2018-06-24 Nick Clifton <nickc@redhat.com>
1972 2.32 branch created.
1974 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1976 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1978 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1981 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1983 * configure: Regenerate.
1985 2019-01-07 Alan Modra <amodra@gmail.com>
1987 * configure: Regenerate.
1988 * po/POTFILES.in: Regenerate.
1990 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1992 * s12z-opc.c: New file.
1993 * s12z-opc.h: New file.
1994 * s12z-dis.c: Removed all code not directly related to display
1995 of instructions. Used the interface provided by the new files
1997 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1998 * Makefile.in: Regenerate.
1999 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2000 * configure: Regenerate.
2002 2019-01-01 Alan Modra <amodra@gmail.com>
2004 Update year range in copyright notice of all files.
2006 For older changes see ChangeLog-2018
2008 Copyright (C) 2019 Free Software Foundation, Inc.
2010 Copying and distribution of this file, with or without modification,
2011 are permitted in any medium without royalty provided the copyright
2012 notice and this notice are preserved.
2018 version-control: never