1 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
3 * arm-dis.c (print_insn_coprocessor): Rename index to
6 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
8 * riscv-opc.c (riscv_insn_types): Add r4 type.
10 * riscv-opc.c (riscv_insn_types): Add b and j type.
12 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
13 format for sb type and correct s type.
15 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
17 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
18 SVE FMOV alias of FCPY.
20 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
22 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
23 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
25 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
27 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
28 registers in an instruction prefixed by MOVPRFX.
30 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
32 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
33 sve_size_13 icode to account for variant behaviour of
35 * aarch64-dis-2.c: Regenerate.
36 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
37 sve_size_13 icode to account for variant behaviour of
39 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
40 (OP_SVE_VVV_Q_D): Add new qualifier.
41 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
42 (struct aarch64_opcode): Split pmull{t,b} into those requiring
45 2019-07-01 Jan Beulich <jbeulich@suse.com>
47 * opcodes/i386-gen.c (operand_type_init): Remove
48 OPERAND_TYPE_VEC_IMM4 entry.
49 (operand_types): Remove Vec_Imm4.
50 * opcodes/i386-opc.h (Vec_Imm4): Delete.
51 (union i386_operand_type): Remove vec_imm4.
52 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
53 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
55 2019-07-01 Jan Beulich <jbeulich@suse.com>
57 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
58 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
59 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
60 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
61 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
62 monitorx, mwaitx): Drop ImmExt from operand-less forms.
63 * i386-tbl.h: Re-generate.
65 2019-07-01 Jan Beulich <jbeulich@suse.com>
67 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
69 * i386-tbl.h: Re-generate.
71 2019-07-01 Jan Beulich <jbeulich@suse.com>
73 * i386-opc.tbl (C): New.
74 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
75 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
76 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
77 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
78 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
79 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
80 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
81 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
82 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
83 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
84 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
85 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
86 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
87 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
88 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
89 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
90 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
91 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
92 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
93 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
94 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
95 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
96 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
97 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
98 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
99 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
101 * i386-tbl.h: Re-generate.
103 2019-07-01 Jan Beulich <jbeulich@suse.com>
105 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
107 * i386-tbl.h: Re-generate.
109 2019-07-01 Jan Beulich <jbeulich@suse.com>
111 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
112 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
113 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
114 * i386-tbl.h: Re-generate.
116 2019-07-01 Jan Beulich <jbeulich@suse.com>
118 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
119 Disp8MemShift from register only templates.
120 * i386-tbl.h: Re-generate.
122 2019-07-01 Jan Beulich <jbeulich@suse.com>
124 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
125 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
126 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
127 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
128 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
129 EVEX_W_0F11_P_3_M_1): Delete.
130 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
131 EVEX_W_0F11_P_3): New.
132 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
133 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
134 MOD_EVEX_0F11_PREFIX_3 table entries.
135 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
136 PREFIX_EVEX_0F11 table entries.
137 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
138 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
139 EVEX_W_0F11_P_3_M_{0,1} table entries.
141 2019-07-01 Jan Beulich <jbeulich@suse.com>
143 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
146 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
149 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
150 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
151 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
152 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
153 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
154 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
155 EVEX_LEN_0F38C7_R_6_P_2_W_1.
156 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
157 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
158 PREFIX_EVEX_0F38C6_REG_6 entries.
159 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
160 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
161 EVEX_W_0F38C7_R_6_P_2 entries.
162 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
163 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
164 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
165 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
166 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
167 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
168 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
170 2019-06-27 Jan Beulich <jbeulich@suse.com>
172 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
173 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
174 VEX_LEN_0F2D_P_3): Delete.
175 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
176 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
177 (prefix_table): ... here.
179 2019-06-27 Jan Beulich <jbeulich@suse.com>
181 * i386-dis.c (Iq): Delete.
183 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
185 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
186 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
187 (OP_E_memory): Also honor needindex when deciding whether an
188 address size prefix needs printing.
189 (OP_I): Remove handling of q_mode. Add handling of d_mode.
191 2019-06-26 Jim Wilson <jimw@sifive.com>
194 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
195 Set info->display_endian to info->endian_code.
197 2019-06-25 Jan Beulich <jbeulich@suse.com>
199 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
200 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
201 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
202 OPERAND_TYPE_ACC64 entries.
203 * i386-init.h: Re-generate.
205 2019-06-25 Jan Beulich <jbeulich@suse.com>
207 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
209 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
211 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
213 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
214 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
216 2019-06-25 Jan Beulich <jbeulich@suse.com>
218 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
221 2019-06-25 Jan Beulich <jbeulich@suse.com>
223 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
224 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
226 * i386-opc.tbl (movnti): Add IgnoreSize.
227 * i386-tbl.h: Re-generate.
229 2019-06-25 Jan Beulich <jbeulich@suse.com>
231 * i386-opc.tbl (and): Mark Imm8S form for optimization.
232 * i386-tbl.h: Re-generate.
234 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
236 * i386-dis-evex.h: Break into ...
237 * i386-dis-evex-len.h: New file.
238 * i386-dis-evex-mod.h: Likewise.
239 * i386-dis-evex-prefix.h: Likewise.
240 * i386-dis-evex-reg.h: Likewise.
241 * i386-dis-evex-w.h: Likewise.
242 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
243 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
246 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
249 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
250 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
252 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
253 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
254 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
255 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
256 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
257 EVEX_LEN_0F385B_P_2_W_1.
258 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
259 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
260 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
261 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
262 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
263 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
264 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
265 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
266 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
267 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
269 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
272 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
273 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
274 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
275 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
276 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
277 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
278 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
279 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
280 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
281 EVEX_LEN_0F3A43_P_2_W_1.
282 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
283 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
284 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
285 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
286 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
287 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
288 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
289 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
290 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
291 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
292 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
293 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
295 2019-06-14 Nick Clifton <nickc@redhat.com>
297 * po/fr.po; Updated French translation.
299 2019-06-13 Stafford Horne <shorne@gmail.com>
301 * or1k-asm.c: Regenerated.
302 * or1k-desc.c: Regenerated.
303 * or1k-desc.h: Regenerated.
304 * or1k-dis.c: Regenerated.
305 * or1k-ibld.c: Regenerated.
306 * or1k-opc.c: Regenerated.
307 * or1k-opc.h: Regenerated.
308 * or1k-opinst.c: Regenerated.
310 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
312 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
314 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
317 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
318 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
319 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
320 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
321 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
322 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
323 EVEX_LEN_0F3A1B_P_2_W_1.
324 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
325 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
326 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
327 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
328 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
329 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
330 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
331 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
333 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
336 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
337 EVEX.vvvv when disassembling VEX and EVEX instructions.
338 (OP_VEX): Set vex.register_specifier to 0 after readding
339 vex.register_specifier.
340 (OP_Vex_2src_1): Likewise.
341 (OP_Vex_2src_2): Likewise.
342 (OP_LWP_E): Likewise.
343 (OP_EX_Vex): Don't check vex.register_specifier.
344 (OP_XMM_Vex): Likewise.
346 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
347 Lili Cui <lili.cui@intel.com>
349 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
350 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
352 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
353 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
354 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
355 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
356 (i386_cpu_flags): Add cpuavx512_vp2intersect.
357 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
358 * i386-init.h: Regenerated.
359 * i386-tbl.h: Likewise.
361 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
362 Lili Cui <lili.cui@intel.com>
364 * doc/c-i386.texi: Document enqcmd.
365 * testsuite/gas/i386/enqcmd-intel.d: New file.
366 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
367 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
368 * testsuite/gas/i386/enqcmd.d: Likewise.
369 * testsuite/gas/i386/enqcmd.s: Likewise.
370 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
371 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
372 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
373 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
374 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
375 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
376 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
379 2019-06-04 Alan Hayward <alan.hayward@arm.com>
381 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
383 2019-06-03 Alan Modra <amodra@gmail.com>
385 * ppc-dis.c (prefix_opcd_indices): Correct size.
387 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
390 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
392 * i386-tbl.h: Regenerated.
394 2019-05-24 Alan Modra <amodra@gmail.com>
396 * po/POTFILES.in: Regenerate.
398 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
399 Alan Modra <amodra@gmail.com>
401 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
402 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
403 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
404 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
405 XTOP>): Define and add entries.
406 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
407 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
408 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
409 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
411 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
412 Alan Modra <amodra@gmail.com>
414 * ppc-dis.c (ppc_opts): Add "future" entry.
415 (PREFIX_OPCD_SEGS): Define.
416 (prefix_opcd_indices): New array.
417 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
418 (lookup_prefix): New function.
419 (print_insn_powerpc): Handle 64-bit prefix instructions.
420 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
421 (PMRR, POWERXX): Define.
422 (prefix_opcodes): New instruction table.
423 (prefix_num_opcodes): New constant.
425 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
427 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
428 * configure: Regenerated.
429 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
431 (HFILES): Add bpf-desc.h and bpf-opc.h.
432 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
433 bpf-ibld.c and bpf-opc.c.
435 * Makefile.in: Regenerated.
436 * disassemble.c (ARCH_bpf): Define.
437 (disassembler): Add case for bfd_arch_bpf.
438 (disassemble_init_for_target): Likewise.
439 (enum epbf_isa_attr): Define.
440 * disassemble.h: extern print_insn_bpf.
441 * bpf-asm.c: Generated.
442 * bpf-opc.h: Likewise.
443 * bpf-opc.c: Likewise.
444 * bpf-ibld.c: Likewise.
445 * bpf-dis.c: Likewise.
446 * bpf-desc.h: Likewise.
447 * bpf-desc.c: Likewise.
449 2019-05-21 Sudakshina Das <sudi.das@arm.com>
451 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
452 and VMSR with the new operands.
454 2019-05-21 Sudakshina Das <sudi.das@arm.com>
456 * arm-dis.c (enum mve_instructions): New enum
457 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
459 (mve_opcodes): New instructions as above.
460 (is_mve_encoding_conflict): Add cases for csinc, csinv,
462 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
464 2019-05-21 Sudakshina Das <sudi.das@arm.com>
466 * arm-dis.c (emun mve_instructions): Updated for new instructions.
467 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
468 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
469 uqshl, urshrl and urshr.
470 (is_mve_okay_in_it): Add new instructions to TRUE list.
471 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
472 (print_insn_mve): Updated to accept new %j,
473 %<bitfield>m and %<bitfield>n patterns.
475 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
477 * mips-opc.c (mips_builtin_opcodes): Change source register
480 2019-05-20 Nick Clifton <nickc@redhat.com>
482 * po/fr.po: Updated French translation.
484 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
485 Michael Collison <michael.collison@arm.com>
487 * arm-dis.c (thumb32_opcodes): Add new instructions.
488 (enum mve_instructions): Likewise.
489 (enum mve_undefined): Add new reasons.
490 (is_mve_encoding_conflict): Handle new instructions.
491 (is_mve_undefined): Likewise.
492 (is_mve_unpredictable): Likewise.
493 (print_mve_undefined): Likewise.
494 (print_mve_size): Likewise.
496 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
497 Michael Collison <michael.collison@arm.com>
499 * arm-dis.c (thumb32_opcodes): Add new instructions.
500 (enum mve_instructions): Likewise.
501 (is_mve_encoding_conflict): Handle new instructions.
502 (is_mve_undefined): Likewise.
503 (is_mve_unpredictable): Likewise.
504 (print_mve_size): Likewise.
506 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
507 Michael Collison <michael.collison@arm.com>
509 * arm-dis.c (thumb32_opcodes): Add new instructions.
510 (enum mve_instructions): Likewise.
511 (is_mve_encoding_conflict): Likewise.
512 (is_mve_unpredictable): Likewise.
513 (print_mve_size): Likewise.
515 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
516 Michael Collison <michael.collison@arm.com>
518 * arm-dis.c (thumb32_opcodes): Add new instructions.
519 (enum mve_instructions): Likewise.
520 (is_mve_encoding_conflict): Handle new instructions.
521 (is_mve_undefined): Likewise.
522 (is_mve_unpredictable): Likewise.
523 (print_mve_size): Likewise.
525 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
526 Michael Collison <michael.collison@arm.com>
528 * arm-dis.c (thumb32_opcodes): Add new instructions.
529 (enum mve_instructions): Likewise.
530 (is_mve_encoding_conflict): Handle new instructions.
531 (is_mve_undefined): Likewise.
532 (is_mve_unpredictable): Likewise.
533 (print_mve_size): Likewise.
534 (print_insn_mve): Likewise.
536 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
537 Michael Collison <michael.collison@arm.com>
539 * arm-dis.c (thumb32_opcodes): Add new instructions.
540 (print_insn_thumb32): Handle new instructions.
542 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
543 Michael Collison <michael.collison@arm.com>
545 * arm-dis.c (enum mve_instructions): Add new instructions.
546 (enum mve_undefined): Add new reasons.
547 (is_mve_encoding_conflict): Handle new instructions.
548 (is_mve_undefined): Likewise.
549 (is_mve_unpredictable): Likewise.
550 (print_mve_undefined): Likewise.
551 (print_mve_size): Likewise.
552 (print_mve_shift_n): Likewise.
553 (print_insn_mve): Likewise.
555 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
556 Michael Collison <michael.collison@arm.com>
558 * arm-dis.c (enum mve_instructions): Add new instructions.
559 (is_mve_encoding_conflict): Handle new instructions.
560 (is_mve_unpredictable): Likewise.
561 (print_mve_rotate): Likewise.
562 (print_mve_size): Likewise.
563 (print_insn_mve): Likewise.
565 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
566 Michael Collison <michael.collison@arm.com>
568 * arm-dis.c (enum mve_instructions): Add new instructions.
569 (is_mve_encoding_conflict): Handle new instructions.
570 (is_mve_unpredictable): Likewise.
571 (print_mve_size): Likewise.
572 (print_insn_mve): Likewise.
574 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
575 Michael Collison <michael.collison@arm.com>
577 * arm-dis.c (enum mve_instructions): Add new instructions.
578 (enum mve_undefined): Add new reasons.
579 (is_mve_encoding_conflict): Handle new instructions.
580 (is_mve_undefined): Likewise.
581 (is_mve_unpredictable): Likewise.
582 (print_mve_undefined): Likewise.
583 (print_mve_size): Likewise.
584 (print_insn_mve): Likewise.
586 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
587 Michael Collison <michael.collison@arm.com>
589 * arm-dis.c (enum mve_instructions): Add new instructions.
590 (is_mve_encoding_conflict): Handle new instructions.
591 (is_mve_undefined): Likewise.
592 (is_mve_unpredictable): Likewise.
593 (print_mve_size): Likewise.
594 (print_insn_mve): Likewise.
596 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
597 Michael Collison <michael.collison@arm.com>
599 * arm-dis.c (enum mve_instructions): Add new instructions.
600 (enum mve_unpredictable): Add new reasons.
601 (enum mve_undefined): Likewise.
602 (is_mve_okay_in_it): Handle new isntructions.
603 (is_mve_encoding_conflict): Likewise.
604 (is_mve_undefined): Likewise.
605 (is_mve_unpredictable): Likewise.
606 (print_mve_vmov_index): Likewise.
607 (print_simd_imm8): Likewise.
608 (print_mve_undefined): Likewise.
609 (print_mve_unpredictable): Likewise.
610 (print_mve_size): Likewise.
611 (print_insn_mve): Likewise.
613 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
614 Michael Collison <michael.collison@arm.com>
616 * arm-dis.c (enum mve_instructions): Add new instructions.
617 (enum mve_unpredictable): Add new reasons.
618 (enum mve_undefined): Likewise.
619 (is_mve_encoding_conflict): Handle new instructions.
620 (is_mve_undefined): Likewise.
621 (is_mve_unpredictable): Likewise.
622 (print_mve_undefined): Likewise.
623 (print_mve_unpredictable): Likewise.
624 (print_mve_rounding_mode): Likewise.
625 (print_mve_vcvt_size): Likewise.
626 (print_mve_size): Likewise.
627 (print_insn_mve): Likewise.
629 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
630 Michael Collison <michael.collison@arm.com>
632 * arm-dis.c (enum mve_instructions): Add new instructions.
633 (enum mve_unpredictable): Add new reasons.
634 (enum mve_undefined): Likewise.
635 (is_mve_undefined): Handle new instructions.
636 (is_mve_unpredictable): Likewise.
637 (print_mve_undefined): Likewise.
638 (print_mve_unpredictable): Likewise.
639 (print_mve_size): Likewise.
640 (print_insn_mve): Likewise.
642 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
643 Michael Collison <michael.collison@arm.com>
645 * arm-dis.c (enum mve_instructions): Add new instructions.
646 (enum mve_undefined): Add new reasons.
647 (insns): Add new instructions.
648 (is_mve_encoding_conflict):
649 (print_mve_vld_str_addr): New print function.
650 (is_mve_undefined): Handle new instructions.
651 (is_mve_unpredictable): Likewise.
652 (print_mve_undefined): Likewise.
653 (print_mve_size): Likewise.
654 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
655 (print_insn_mve): Handle new operands.
657 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
658 Michael Collison <michael.collison@arm.com>
660 * arm-dis.c (enum mve_instructions): Add new instructions.
661 (enum mve_unpredictable): Add new reasons.
662 (is_mve_encoding_conflict): Handle new instructions.
663 (is_mve_unpredictable): Likewise.
664 (mve_opcodes): Add new instructions.
665 (print_mve_unpredictable): Handle new reasons.
666 (print_mve_register_blocks): New print function.
667 (print_mve_size): Handle new instructions.
668 (print_insn_mve): Likewise.
670 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
671 Michael Collison <michael.collison@arm.com>
673 * arm-dis.c (enum mve_instructions): Add new instructions.
674 (enum mve_unpredictable): Add new reasons.
675 (enum mve_undefined): Likewise.
676 (is_mve_encoding_conflict): Handle new instructions.
677 (is_mve_undefined): Likewise.
678 (is_mve_unpredictable): Likewise.
679 (coprocessor_opcodes): Move NEON VDUP from here...
680 (neon_opcodes): ... to here.
681 (mve_opcodes): Add new instructions.
682 (print_mve_undefined): Handle new reasons.
683 (print_mve_unpredictable): Likewise.
684 (print_mve_size): Handle new instructions.
685 (print_insn_neon): Handle vdup.
686 (print_insn_mve): Handle new operands.
688 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
689 Michael Collison <michael.collison@arm.com>
691 * arm-dis.c (enum mve_instructions): Add new instructions.
692 (enum mve_unpredictable): Add new values.
693 (mve_opcodes): Add new instructions.
694 (vec_condnames): New array with vector conditions.
695 (mve_predicatenames): New array with predicate suffixes.
696 (mve_vec_sizename): New array with vector sizes.
697 (enum vpt_pred_state): New enum with vector predication states.
698 (struct vpt_block): New struct type for vpt blocks.
699 (vpt_block_state): Global struct to keep track of state.
700 (mve_extract_pred_mask): New helper function.
701 (num_instructions_vpt_block): Likewise.
702 (mark_outside_vpt_block): Likewise.
703 (mark_inside_vpt_block): Likewise.
704 (invert_next_predicate_state): Likewise.
705 (update_next_predicate_state): Likewise.
706 (update_vpt_block_state): Likewise.
707 (is_vpt_instruction): Likewise.
708 (is_mve_encoding_conflict): Add entries for new instructions.
709 (is_mve_unpredictable): Likewise.
710 (print_mve_unpredictable): Handle new cases.
711 (print_instruction_predicate): Likewise.
712 (print_mve_size): New function.
713 (print_vec_condition): New function.
714 (print_insn_mve): Handle vpt blocks and new print operands.
716 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
718 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
719 8, 14 and 15 for Armv8.1-M Mainline.
721 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
722 Michael Collison <michael.collison@arm.com>
724 * arm-dis.c (enum mve_instructions): New enum.
725 (enum mve_unpredictable): Likewise.
726 (enum mve_undefined): Likewise.
727 (struct mopcode32): New struct.
728 (is_mve_okay_in_it): New function.
729 (is_mve_architecture): Likewise.
730 (arm_decode_field): Likewise.
731 (arm_decode_field_multiple): Likewise.
732 (is_mve_encoding_conflict): Likewise.
733 (is_mve_undefined): Likewise.
734 (is_mve_unpredictable): Likewise.
735 (print_mve_undefined): Likewise.
736 (print_mve_unpredictable): Likewise.
737 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
738 (print_insn_mve): New function.
739 (print_insn_thumb32): Handle MVE architecture.
740 (select_arm_features): Force thumb for Armv8.1-m Mainline.
742 2019-05-10 Nick Clifton <nickc@redhat.com>
745 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
746 end of the table prematurely.
748 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
750 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
753 2019-05-11 Alan Modra <amodra@gmail.com>
755 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
756 when -Mraw is in effect.
758 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
760 * aarch64-dis-2.c: Regenerate.
761 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
762 (OP_SVE_BBB): New variant set.
763 (OP_SVE_DDDD): New variant set.
764 (OP_SVE_HHH): New variant set.
765 (OP_SVE_HHHU): New variant set.
766 (OP_SVE_SSS): New variant set.
767 (OP_SVE_SSSU): New variant set.
768 (OP_SVE_SHH): New variant set.
769 (OP_SVE_SBBU): New variant set.
770 (OP_SVE_DSS): New variant set.
771 (OP_SVE_DHHU): New variant set.
772 (OP_SVE_VMV_HSD_BHS): New variant set.
773 (OP_SVE_VVU_HSD_BHS): New variant set.
774 (OP_SVE_VVVU_SD_BH): New variant set.
775 (OP_SVE_VVVU_BHSD): New variant set.
776 (OP_SVE_VVV_QHD_DBS): New variant set.
777 (OP_SVE_VVV_HSD_BHS): New variant set.
778 (OP_SVE_VVV_HSD_BHS2): New variant set.
779 (OP_SVE_VVV_BHS_HSD): New variant set.
780 (OP_SVE_VV_BHS_HSD): New variant set.
781 (OP_SVE_VVV_SD): New variant set.
782 (OP_SVE_VVU_BHS_HSD): New variant set.
783 (OP_SVE_VZVV_SD): New variant set.
784 (OP_SVE_VZVV_BH): New variant set.
785 (OP_SVE_VZV_SD): New variant set.
786 (aarch64_opcode_table): Add sve2 instructions.
788 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
790 * aarch64-asm-2.c: Regenerated.
791 * aarch64-dis-2.c: Regenerated.
792 * aarch64-opc-2.c: Regenerated.
793 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
794 for SVE_SHLIMM_UNPRED_22.
795 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
796 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
799 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
801 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
802 sve_size_tsz_bhs iclass encode.
803 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
804 sve_size_tsz_bhs iclass decode.
806 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
808 * aarch64-asm-2.c: Regenerated.
809 * aarch64-dis-2.c: Regenerated.
810 * aarch64-opc-2.c: Regenerated.
811 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
812 for SVE_Zm4_11_INDEX.
813 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
814 (fields): Handle SVE_i2h field.
815 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
816 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
818 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
820 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
821 sve_shift_tsz_bhsd iclass encode.
822 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
823 sve_shift_tsz_bhsd iclass decode.
825 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
827 * aarch64-asm-2.c: Regenerated.
828 * aarch64-dis-2.c: Regenerated.
829 * aarch64-opc-2.c: Regenerated.
830 * aarch64-asm.c (aarch64_ins_sve_shrimm):
831 (aarch64_encode_variant_using_iclass): Handle
832 sve_shift_tsz_hsd iclass encode.
833 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
834 sve_shift_tsz_hsd iclass decode.
835 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
836 for SVE_SHRIMM_UNPRED_22.
837 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
838 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
841 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
843 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
844 sve_size_013 iclass encode.
845 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
846 sve_size_013 iclass decode.
848 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
850 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
851 sve_size_bh iclass encode.
852 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
853 sve_size_bh iclass decode.
855 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
857 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
858 sve_size_sd2 iclass encode.
859 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
860 sve_size_sd2 iclass decode.
861 * aarch64-opc.c (fields): Handle SVE_sz2 field.
862 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
864 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
866 * aarch64-asm-2.c: Regenerated.
867 * aarch64-dis-2.c: Regenerated.
868 * aarch64-opc-2.c: Regenerated.
869 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
871 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
872 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
874 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
876 * aarch64-asm-2.c: Regenerated.
877 * aarch64-dis-2.c: Regenerated.
878 * aarch64-opc-2.c: Regenerated.
879 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
880 for SVE_Zm3_11_INDEX.
881 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
882 (fields): Handle SVE_i3l and SVE_i3h2 fields.
883 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
885 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
887 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
889 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
890 sve_size_hsd2 iclass encode.
891 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
892 sve_size_hsd2 iclass decode.
893 * aarch64-opc.c (fields): Handle SVE_size field.
894 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
896 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
898 * aarch64-asm-2.c: Regenerated.
899 * aarch64-dis-2.c: Regenerated.
900 * aarch64-opc-2.c: Regenerated.
901 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
903 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
904 (fields): Handle SVE_rot3 field.
905 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
906 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
908 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
910 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
913 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
916 (aarch64_feature_sve2, aarch64_feature_sve2aes,
917 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
918 aarch64_feature_sve2bitperm): New feature sets.
919 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
920 for feature set addresses.
921 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
922 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
924 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
925 Faraz Shahbazker <fshahbazker@wavecomp.com>
927 * mips-dis.c (mips_calculate_combination_ases): Add ISA
928 argument and set ASE_EVA_R6 appropriately.
929 (set_default_mips_dis_options): Pass ISA to above.
930 (parse_mips_dis_option): Likewise.
931 * mips-opc.c (EVAR6): New macro.
932 (mips_builtin_opcodes): Add llwpe, scwpe.
934 2019-05-01 Sudakshina Das <sudi.das@arm.com>
936 * aarch64-asm-2.c: Regenerated.
937 * aarch64-dis-2.c: Regenerated.
938 * aarch64-opc-2.c: Regenerated.
939 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
940 AARCH64_OPND_TME_UIMM16.
941 (aarch64_print_operand): Likewise.
942 * aarch64-tbl.h (QL_IMM_NIL): New.
945 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
947 2019-04-29 John Darrington <john@darrington.wattle.id.au>
949 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
951 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
952 Faraz Shahbazker <fshahbazker@wavecomp.com>
954 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
956 2019-04-24 John Darrington <john@darrington.wattle.id.au>
958 * s12z-opc.h: Add extern "C" bracketing to help
959 users who wish to use this interface in c++ code.
961 2019-04-24 John Darrington <john@darrington.wattle.id.au>
963 * s12z-opc.c (bm_decode): Handle bit map operations with the
966 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
968 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
969 specifier. Add entries for VLDR and VSTR of system registers.
970 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
971 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
972 of %J and %K format specifier.
974 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
976 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
977 Add new entries for VSCCLRM instruction.
978 (print_insn_coprocessor): Handle new %C format control code.
980 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
982 * arm-dis.c (enum isa): New enum.
983 (struct sopcode32): New structure.
984 (coprocessor_opcodes): change type of entries to struct sopcode32 and
985 set isa field of all current entries to ANY.
986 (print_insn_coprocessor): Change type of insn to struct sopcode32.
987 Only match an entry if its isa field allows the current mode.
989 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
991 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
993 (print_insn_thumb32): Add logic to print %n CLRM register list.
995 2019-04-15 Sudakshina Das <sudi.das@arm.com>
997 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1000 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1002 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1003 (print_insn_thumb32): Edit the switch case for %Z.
1005 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1007 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1009 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1011 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1013 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1015 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1017 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1019 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1020 Arm register with r13 and r15 unpredictable.
1021 (thumb32_opcodes): New instructions for bfx and bflx.
1023 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1025 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1027 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1029 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1031 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1033 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1035 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1037 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1039 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1041 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1042 "optr". ("operator" is a reserved word in c++).
1044 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1046 * aarch64-opc.c (aarch64_print_operand): Add case for
1048 (verify_constraints): Likewise.
1049 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1050 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1051 to accept Rt|SP as first operand.
1052 (AARCH64_OPERANDS): Add new Rt_SP.
1053 * aarch64-asm-2.c: Regenerated.
1054 * aarch64-dis-2.c: Regenerated.
1055 * aarch64-opc-2.c: Regenerated.
1057 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1059 * aarch64-asm-2.c: Regenerated.
1060 * aarch64-dis-2.c: Likewise.
1061 * aarch64-opc-2.c: Likewise.
1062 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1064 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1066 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1068 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1070 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1071 * i386-init.h: Regenerated.
1073 2019-04-07 Alan Modra <amodra@gmail.com>
1075 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1076 op_separator to control printing of spaces, comma and parens
1077 rather than need_comma, need_paren and spaces vars.
1079 2019-04-07 Alan Modra <amodra@gmail.com>
1082 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1083 (print_insn_neon, print_insn_arm): Likewise.
1085 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1087 * i386-dis-evex.h (evex_table): Updated to support BF16
1089 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1090 and EVEX_W_0F3872_P_3.
1091 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1092 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1093 * i386-opc.h (enum): Add CpuAVX512_BF16.
1094 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1095 * i386-opc.tbl: Add AVX512 BF16 instructions.
1096 * i386-init.h: Regenerated.
1097 * i386-tbl.h: Likewise.
1099 2019-04-05 Alan Modra <amodra@gmail.com>
1101 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1102 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1103 to favour printing of "-" branch hint when using the "y" bit.
1104 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1106 2019-04-05 Alan Modra <amodra@gmail.com>
1108 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1109 opcode until first operand is output.
1111 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1114 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1115 (valid_bo_post_v2): Add support for 'at' branch hints.
1116 (insert_bo): Only error on branch on ctr.
1117 (get_bo_hint_mask): New function.
1118 (insert_boe): Add new 'branch_taken' formal argument. Add support
1119 for inserting 'at' branch hints.
1120 (extract_boe): Add new 'branch_taken' formal argument. Add support
1121 for extracting 'at' branch hints.
1122 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1123 (BOE): Delete operand.
1124 (BOM, BOP): New operands.
1126 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1127 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1128 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1129 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1130 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1131 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1132 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1133 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1134 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1135 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1136 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1137 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1138 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1139 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1140 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1141 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1142 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1143 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1144 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1145 bttarl+>: New extended mnemonics.
1147 2019-03-28 Alan Modra <amodra@gmail.com>
1150 * ppc-opc.c (BTF): Define.
1151 (powerpc_opcodes): Use for mtfsb*.
1152 * ppc-dis.c (print_insn_powerpc): Print fields with both
1153 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1155 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1157 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1158 (mapping_symbol_for_insn): Implement new algorithm.
1159 (print_insn): Remove duplicate code.
1161 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1163 * aarch64-dis.c (print_insn_aarch64):
1166 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1168 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1171 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1173 * aarch64-dis.c (last_stop_offset): New.
1174 (print_insn_aarch64): Use stop_offset.
1176 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1179 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1181 * i386-init.h: Regenerated.
1183 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1186 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1187 vmovdqu16, vmovdqu32 and vmovdqu64.
1188 * i386-tbl.h: Regenerated.
1190 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1192 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1193 from vstrszb, vstrszh, and vstrszf.
1195 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1197 * s390-opc.txt: Add instruction descriptions.
1199 2019-02-08 Jim Wilson <jimw@sifive.com>
1201 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1204 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1206 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1208 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1211 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1212 * aarch64-opc.c (verify_elem_sd): New.
1213 (fields): Add FLD_sz entr.
1214 * aarch64-tbl.h (_SIMD_INSN): New.
1215 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1216 fmulx scalar and vector by element isns.
1218 2019-02-07 Nick Clifton <nickc@redhat.com>
1220 * po/sv.po: Updated Swedish translation.
1222 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1224 * s390-mkopc.c (main): Accept arch13 as cpu string.
1225 * s390-opc.c: Add new instruction formats and instruction opcode
1227 * s390-opc.txt: Add new arch13 instructions.
1229 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1231 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1232 (aarch64_opcode): Change encoding for stg, stzg
1234 * aarch64-asm-2.c: Regenerated.
1235 * aarch64-dis-2.c: Regenerated.
1236 * aarch64-opc-2.c: Regenerated.
1238 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1240 * aarch64-asm-2.c: Regenerated.
1241 * aarch64-dis-2.c: Likewise.
1242 * aarch64-opc-2.c: Likewise.
1243 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1245 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1246 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1248 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1249 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1250 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1251 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1252 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1253 case for ldstgv_indexed.
1254 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1255 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1256 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1257 * aarch64-asm-2.c: Regenerated.
1258 * aarch64-dis-2.c: Regenerated.
1259 * aarch64-opc-2.c: Regenerated.
1261 2019-01-23 Nick Clifton <nickc@redhat.com>
1263 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1265 2019-01-21 Nick Clifton <nickc@redhat.com>
1267 * po/de.po: Updated German translation.
1268 * po/uk.po: Updated Ukranian translation.
1270 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1271 * mips-dis.c (mips_arch_choices): Fix typo in
1272 gs464, gs464e and gs264e descriptors.
1274 2019-01-19 Nick Clifton <nickc@redhat.com>
1276 * configure: Regenerate.
1277 * po/opcodes.pot: Regenerate.
1279 2018-06-24 Nick Clifton <nickc@redhat.com>
1281 2.32 branch created.
1283 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1285 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1287 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1290 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1292 * configure: Regenerate.
1294 2019-01-07 Alan Modra <amodra@gmail.com>
1296 * configure: Regenerate.
1297 * po/POTFILES.in: Regenerate.
1299 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1301 * s12z-opc.c: New file.
1302 * s12z-opc.h: New file.
1303 * s12z-dis.c: Removed all code not directly related to display
1304 of instructions. Used the interface provided by the new files
1306 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1307 * Makefile.in: Regenerate.
1308 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1309 * configure: Regenerate.
1311 2019-01-01 Alan Modra <amodra@gmail.com>
1313 Update year range in copyright notice of all files.
1315 For older changes see ChangeLog-2018
1317 Copyright (C) 2019 Free Software Foundation, Inc.
1319 Copying and distribution of this file, with or without modification,
1320 are permitted in any medium without royalty provided the copyright
1321 notice and this notice are preserved.
1327 version-control: never