opcodes/ChangeLog

   1 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
   4         (X_IMM2): Define.
   5         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
   6         bfd_mach_sparc_v9m8.
   7         (print_insn_sparc): Handle new operand types.
   8         * sparc-opc.c (MASK_M8): Define.
   9         (v6): Add MASK_M8.
  10         (v6notlet): Likewise.
  11         (v7): Likewise.
  12         (v8): Likewise.
  13         (v9): Likewise.
  14         (v9a): Likewise.
  15         (v9b): Likewise.
  16         (v9c): Likewise.
  17         (v9d): Likewise.
  18         (v9e): Likewise.
  19         (v9v): Likewise.
  20         (v9m): Likewise.
  21         (v9andleon): Likewise.
  22         (m8): Define.
  23         (HWS_VM8): Define.
  24         (HWS2_VM8): Likewise.
  25         (sparc_opcode_archs): Add entry for "m8".
  26         (sparc_opcodes): Add OSA2017 and M8 instructions
  27         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
  28         fpx{ll,ra,rl}64x,
  29         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
  30         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
  31         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
  32         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
  33         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
  34         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
  35         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
  36         ASI_CORE_SELECT_COMMIT_NHT.
  37
  38 2017-05-18  Alan Modra  <amodra@gmail.com>
  39
  40         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
  41         * aarch64-dis.c: Likewise.
  42         * aarch64-gen.c: Likewise.
  43         * aarch64-opc.c: Likewise.
  44
  45 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
  46             Matthew Fortune  <matthew.fortune@imgtec.com>
  47
  48         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
  49         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
  50         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
  51         (print_insn_arg) <OP_REG28>: Add handler.
  52         (validate_insn_args) <OP_REG28>: Handle.
  53         (print_mips16_insn_arg): Handle MIPS16 instructions that require
  54         32-bit encoding and 9-bit immediates.
  55         (print_insn_mips16): Handle MIPS16 instructions that require
  56         32-bit encoding and MFC0/MTC0 operand decoding.
  57         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
  58         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
  59         (RD_C0, WR_C0, E2, E2MT): New macros.
  60         (mips16_opcodes): Add entries for MIPS16e2 instructions:
  61         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
  62         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
  63         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
  64         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
  65         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
  66         instructions, "swl", "swr", "sync" and its "sync_acquire",
  67         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
  68         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
  69         regular/extended entries for original MIPS16 ISA revision
  70         instructions whose extended forms are subdecoded in the MIPS16e2
  71         ISA revision: "li", "sll" and "srl".
  72
  73 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
  74
  75         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
  76         reference in CP0 move operand decoding.
  77
  78 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
  79
  80         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
  81         type to hexadecimal.
  82         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
  83
  84 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
  85
  86         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
  87         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
  88         "sync_rmb" and "sync_wmb" as aliases.
  89         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
  90         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
  91
  92 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
  93
  94         * arc-dis.c (parse_option): Update quarkse_em option..
  95         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
  96         QUARKSE1.
  97         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
  98
  99 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 100
 101         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 102
 103 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 104
 105         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 106         register.
 107
 108 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 109
 110         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 111         and branches and not synthetic data instructions.
 112
 113 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 114
 115         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 116
 117 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 118
 119         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 120         * arc-opc.c (insert_r13el): New function.
 121         (R13_EL): Define.
 122         * arc-tbl.h: Add new enter/leave variants.
 123
 124 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 125
 126         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 127
 128 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 129
 130         * mips-dis.c (print_mips_disassembler_options): Add
 131         `no-aliases'.
 132
 133 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 134
 135         * mips16-opc.c (AL): New macro.
 136         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 137         of "ld" and "lw" as aliases.
 138
 139 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 140
 141         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 142         arguments.
 143
 144 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 145             Alan Modra  <amodra@gmail.com>
 146
 147         * ppc-opc.c (ELEV): Define.
 148         (vle_opcodes): Add se_rfgi and e_sc.
 149         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 150         for E200Z4.
 151
 152 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 153
 154         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 155
 156 2017-04-21  Nick Clifton  <nickc@redhat.com>
 157
 158         PR binutils/21380
 159         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 160         LD3R and LD4R.
 161
 162 2017-04-13  Alan Modra  <amodra@gmail.com>
 163
 164         * epiphany-desc.c: Regenerate.
 165         * fr30-desc.c: Regenerate.
 166         * frv-desc.c: Regenerate.
 167         * ip2k-desc.c: Regenerate.
 168         * iq2000-desc.c: Regenerate.
 169         * lm32-desc.c: Regenerate.
 170         * m32c-desc.c: Regenerate.
 171         * m32r-desc.c: Regenerate.
 172         * mep-desc.c: Regenerate.
 173         * mt-desc.c: Regenerate.
 174         * or1k-desc.c: Regenerate.
 175         * xc16x-desc.c: Regenerate.
 176         * xstormy16-desc.c: Regenerate.
 177
 178 2017-04-11  Alan Modra  <amodra@gmail.com>
 179
 180         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 181         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 182         PPC_OPCODE_TMR for e6500.
 183         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 184         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 185         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 186         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 187         (PPCHTM): Define as PPC_OPCODE_POWER8.
 188         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 189
 190 2017-04-10  Alan Modra  <amodra@gmail.com>
 191
 192         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 193         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 194         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 195         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 196
 197 2017-04-09  Pip Cet  <pipcet@gmail.com>
 198
 199         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 200         appropriate floating-point precision directly.
 201
 202 2017-04-07  Alan Modra  <amodra@gmail.com>
 203
 204         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 205         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 206         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 207         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 208         vector instructions with E6500 not PPCVEC2.
 209
 210 2017-04-06  Pip Cet  <pipcet@gmail.com>
 211
 212         * Makefile.am: Add wasm32-dis.c.
 213         * configure.ac: Add wasm32-dis.c to wasm32 target.
 214         * disassemble.c: Add wasm32 disassembler code.
 215         * wasm32-dis.c: New file.
 216         * Makefile.in: Regenerate.
 217         * configure: Regenerate.
 218         * po/POTFILES.in: Regenerate.
 219         * po/opcodes.pot: Regenerate.
 220
 221 2017-04-05  Pedro Alves  <palves@redhat.com>
 222
 223         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 224         * arm-dis.c (parse_arm_disassembler_options): Constify.
 225         * ppc-dis.c (powerpc_init_dialect): Constify local.
 226         * vax-dis.c (parse_disassembler_options): Constify.
 227
 228 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 229
 230         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 231         RISCV_GP_SYMBOL.
 232
 233 2017-03-30  Pip Cet  <pipcet@gmail.com>
 234
 235         * configure.ac: Add (empty) bfd_wasm32_arch target.
 236         * configure: Regenerate
 237         * po/opcodes.pot: Regenerate.
 238
 239 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 240
 241         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 242         OSA2015.
 243         * opcodes/sparc-opc.c (asi_table): New ASIs.
 244
 245 2017-03-29  Alan Modra  <amodra@gmail.com>
 246
 247         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 248         "raw" option.
 249         (lookup_powerpc): Don't special case -1 dialect.  Handle
 250         PPC_OPCODE_RAW.
 251         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 252         lookup_powerpc call, pass it on second.
 253
 254 2017-03-27  Alan Modra  <amodra@gmail.com>
 255
 256         PR 21303
 257         * ppc-dis.c (struct ppc_mopt): Comment.
 258         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 259
 260 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 261
 262         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 263         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 264         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 265         (insert_nps_misc_imm_offset): New function.
 266         (extract_nps_misc imm_offset): New function.
 267         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 268         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 269
 270 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 271
 272         * s390-mkopc.c (main): Remove vx2 check.
 273         * s390-opc.txt: Remove vx2 instruction flags.
 274
 275 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 276
 277         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 278         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 279         (insert_nps_imm_offset): New function.
 280         (extract_nps_imm_offset): New function.
 281         (insert_nps_imm_entry): New function.
 282         (extract_nps_imm_entry): New function.
 283
 284 2017-03-17  Alan Modra  <amodra@gmail.com>
 285
 286         PR 21248
 287         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 288         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 289         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 290
 291 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 292
 293         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 294         <c.andi>: Likewise.
 295         <c.addiw> Likewise.
 296
 297 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 298
 299         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 300
 301 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 302
 303         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 304         <srl> Likewise.
 305         <srai> Likewise.
 306         <sra> Likewise.
 307
 308 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 309
 310         * i386-gen.c (opcode_modifiers): Replace S with Load.
 311         * i386-opc.h (S): Removed.
 312         (Load): New.
 313         (i386_opcode_modifier): Replace s with load.
 314         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 315         and {evex}.  Replace S with Load.
 316         * i386-tbl.h: Regenerated.
 317
 318 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386-opc.tbl: Use CpuCET on rdsspq.
 321         * i386-tbl.h: Regenerated.
 322
 323 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 324
 325         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 326         <vsx>: Do not use PPC_OPCODE_VSX3;
 327
 328 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 329
 330         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 331
 332 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 335         (MOD_0F1E_PREFIX_1): Likewise.
 336         (MOD_0F38F5_PREFIX_2): Likewise.
 337         (MOD_0F38F6_PREFIX_0): Likewise.
 338         (RM_0F1E_MOD_3_REG_7): Likewise.
 339         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 340         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 341         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 342         (PREFIX_0F1E): Likewise.
 343         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 344         (PREFIX_0F38F5): Likewise.
 345         (dis386_twobyte): Use PREFIX_0F1E.
 346         (reg_table): Add REG_0F1E_MOD_3.
 347         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 348         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 349         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 350         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 351         (three_byte_table): Use PREFIX_0F38F5.
 352         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 353         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 354         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 355         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 356         PREFIX_MOD_3_0F01_REG_5_RM_2.
 357         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 358         (cpu_flags): Add CpuCET.
 359         * i386-opc.h (CpuCET): New enum.
 360         (CpuUnused): Commented out.
 361         (i386_cpu_flags): Add cpucet.
 362         * i386-opc.tbl: Add Intel CET instructions.
 363         * i386-init.h: Regenerated.
 364         * i386-tbl.h: Likewise.
 365
 366 2017-03-06  Alan Modra  <amodra@gmail.com>
 367
 368         PR 21124
 369         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 370         (extract_raq, extract_ras, extract_rbx): New functions.
 371         (powerpc_operands): Use opposite corresponding insert function.
 372         (Q_MASK): Define.
 373         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 374         register restriction.
 375
 376 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 377
 378         * disassemble.c Include "safe-ctype.h".
 379         (disassemble_init_for_target): Handle s390 init.
 380         (remove_whitespace_and_extra_commas): New function.
 381         (disassembler_options_cmp): Likewise.
 382         * arm-dis.c: Include "libiberty.h".
 383         (NUM_ELEM): Delete.
 384         (regnames): Use long disassembler style names.
 385         Add force-thumb and no-force-thumb options.
 386         (NUM_ARM_REGNAMES): Rename from this...
 387         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 388         (get_arm_regname_num_options): Delete.
 389         (set_arm_regname_option): Likewise.
 390         (get_arm_regnames): Likewise.
 391         (parse_disassembler_options): Likewise.
 392         (parse_arm_disassembler_option): Rename from this...
 393         (parse_arm_disassembler_options): ...to this.  Make static.
 394         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 395         (print_insn): Use parse_arm_disassembler_options.
 396         (disassembler_options_arm): New function.
 397         (print_arm_disassembler_options): Handle updated regnames.
 398         * ppc-dis.c: Include "libiberty.h".
 399         (ppc_opts): Add "32" and "64" entries.
 400         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 401         (powerpc_init_dialect): Add break to switch statement.
 402         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 403         (disassembler_options_powerpc): New function.
 404         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 405         Remove printing of "32" and "64".
 406         * s390-dis.c: Include "libiberty.h".
 407         (init_flag): Remove unneeded variable.
 408         (struct s390_options_t): New structure type.
 409         (options): New structure.
 410         (init_disasm): Rename from this...
 411         (disassemble_init_s390): ...to this.  Add initializations for
 412         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 413         (print_insn_s390): Delete call to init_disasm.
 414         (disassembler_options_s390): New function.
 415         (print_s390_disassembler_options): Print using information from
 416         struct 'options'.
 417         * po/opcodes.pot: Regenerate.
 418
 419 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-dis.c (PCMPESTR_Fixup): New.
 422         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 423         (prefix_table): Use PCMPESTR_Fixup.
 424         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 425         PCMPESTR_Fixup.
 426         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 427         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 428         Split 64-bit and non-64-bit variants.
 429         * opcodes/i386-tbl.h: Re-generate.
 430
 431 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 432
 433         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 434         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 435         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 436         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 437         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 438         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 439         (OP_SVE_V_HSD): New macros.
 440         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 441         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 442         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 443         (aarch64_opcode_table): Add new SVE instructions.
 444         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 445         for rotation operands.  Add new SVE operands.
 446         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 447         (ins_sve_quad_index): Likewise.
 448         (ins_imm_rotate): Split into...
 449         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 450         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 451         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 452         functions.
 453         (aarch64_ins_sve_addr_ri_s4): New function.
 454         (aarch64_ins_sve_quad_index): Likewise.
 455         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 456         * aarch64-asm-2.c: Regenerate.
 457         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 458         (ext_sve_quad_index): Likewise.
 459         (ext_imm_rotate): Split into...
 460         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 461         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 462         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 463         functions.
 464         (aarch64_ext_sve_addr_ri_s4): New function.
 465         (aarch64_ext_sve_quad_index): Likewise.
 466         (aarch64_ext_sve_index): Allow quad indices.
 467         (do_misc_decoding): Likewise.
 468         * aarch64-dis-2.c: Regenerate.
 469         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 470         aarch64_field_kinds.
 471         (OPD_F_OD_MASK): Widen by one bit.
 472         (OPD_F_NO_ZR): Bump accordingly.
 473         (get_operand_field_width): New function.
 474         * aarch64-opc.c (fields): Add new SVE fields.
 475         (operand_general_constraint_met_p): Handle new SVE operands.
 476         (aarch64_print_operand): Likewise.
 477         * aarch64-opc-2.c: Regenerate.
 478
 479 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 480
 481         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 482         (aarch64_feature_compnum): ...this.
 483         (SIMD_V8_3): Replace with...
 484         (COMPNUM): ...this.
 485         (CNUM_INSN): New macro.
 486         (aarch64_opcode_table): Use it for the complex number instructions.
 487
 488 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 491
 492 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 493
 494         Add support for associating SPARC ASIs with an architecture level.
 495         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 496         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 497         decoding of SPARC ASIs.
 498
 499 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 502         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 503
 504 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 505
 506         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 507         1 (instead of to itself). Correct typo.
 508
 509 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 510
 511         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 512         pseudoinstructions.
 513
 514 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 515
 516         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 517         (aarch64_sys_reg_supported_p): Handle them.
 518
 519 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 520
 521         * arc-opc.c (UIMM6_20R): Define.
 522         (SIMM12_20): Use above.
 523         (SIMM12_20R): Define.
 524         (SIMM3_5_S): Use above.
 525         (UIMM7_A32_11R_S): Define.
 526         (UIMM7_9_S): Use above.
 527         (UIMM3_13R_S): Define.
 528         (SIMM11_A32_7_S): Use above.
 529         (SIMM9_8R): Define.
 530         (UIMM10_A32_8_S): Use above.
 531         (UIMM8_8R_S): Define.
 532         (W6): Use above.
 533         (arc_relax_opcodes): Use all above defines.
 534
 535 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 536
 537         * arc-regs.h: Distinguish some of the registers different on
 538         ARC700 and HS38 cpus.
 539
 540 2017-02-14  Alan Modra  <amodra@gmail.com>
 541
 542         PR 21118
 543         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 544         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 545
 546 2017-02-11  Stafford Horne  <shorne@gmail.com>
 547             Alan Modra  <amodra@gmail.com>
 548
 549         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 550         Use insn_bytes_value and insn_int_value directly instead.  Don't
 551         free allocated memory until function exit.
 552
 553 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 554
 555         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 556
 557 2017-02-03  Nick Clifton  <nickc@redhat.com>
 558
 559         PR 21096
 560         * aarch64-opc.c (print_register_list): Ensure that the register
 561         list index will fir into the tb buffer.
 562         (print_register_offset_address): Likewise.
 563         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 564
 565 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 566
 567         PR 21056
 568         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 569         instructions when the previous fetch packet ends with a 32-bit
 570         instruction.
 571
 572 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 573
 574         * pru-opc.c: Remove vague reference to a future GDB port.
 575
 576 2017-01-20  Nick Clifton  <nickc@redhat.com>
 577
 578         * po/ga.po: Updated Irish translation.
 579
 580 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 581
 582         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 583
 584 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 585
 586         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 587         if FETCH_DATA returns 0.
 588         (m68k_scan_mask): Likewise.
 589         (print_insn_m68k): Update code to handle -1 return value.
 590
 591 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 592
 593         * m68k-dis.c (enum print_insn_arg_error): New.
 594         (NEXTBYTE): Replace -3 with
 595         PRINT_INSN_ARG_MEMORY_ERROR.
 596         (NEXTULONG): Likewise.
 597         (NEXTSINGLE): Likewise.
 598         (NEXTDOUBLE): Likewise.
 599         (NEXTDOUBLE): Likewise.
 600         (NEXTPACKED): Likewise.
 601         (FETCH_ARG): Likewise.
 602         (FETCH_DATA): Update comments.
 603         (print_insn_arg): Update comments. Replace magic numbers with
 604         enum.
 605         (match_insn_m68k): Likewise.
 606
 607 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 608
 609         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 610         * i386-dis-evex.h (evex_table): Updated.
 611         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 612         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 613         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 614         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 615         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 616         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 617         * i386-init.h: Regenerate.
 618         * i386-tbl.h: Ditto.
 619
 620 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 621
 622         * msp430-dis.c (msp430_singleoperand): Return -1 if
 623         msp430dis_opcode_signed returns false.
 624         (msp430_doubleoperand): Likewise.
 625         (msp430_branchinstr): Return -1 if
 626         msp430dis_opcode_unsigned returns false.
 627         (msp430x_calla_instr): Likewise.
 628         (print_insn_msp430): Likewise.
 629
 630 2017-01-05  Nick Clifton  <nickc@redhat.com>
 631
 632         PR 20946
 633         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 634         could not be matched.
 635         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 636         NULL.
 637
 638 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 639
 640         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 641         (aarch64_opcode_table): Use RCPC_INSN.
 642
 643 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 644
 645         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 646         extension.
 647         * riscv-opcodes/all-opcodes: Likewise.
 648
 649 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 650
 651         * riscv-dis.c (print_insn_args): Add fall through comment.
 652
 653 2017-01-03  Nick Clifton  <nickc@redhat.com>
 654
 655         * po/sr.po: New Serbian translation.
 656         * configure.ac (ALL_LINGUAS): Add sr.
 657         * configure: Regenerate.
 658
 659 2017-01-02  Alan Modra  <amodra@gmail.com>
 660
 661         * epiphany-desc.h: Regenerate.
 662         * epiphany-opc.h: Regenerate.
 663         * fr30-desc.h: Regenerate.
 664         * fr30-opc.h: Regenerate.
 665         * frv-desc.h: Regenerate.
 666         * frv-opc.h: Regenerate.
 667         * ip2k-desc.h: Regenerate.
 668         * ip2k-opc.h: Regenerate.
 669         * iq2000-desc.h: Regenerate.
 670         * iq2000-opc.h: Regenerate.
 671         * lm32-desc.h: Regenerate.
 672         * lm32-opc.h: Regenerate.
 673         * m32c-desc.h: Regenerate.
 674         * m32c-opc.h: Regenerate.
 675         * m32r-desc.h: Regenerate.
 676         * m32r-opc.h: Regenerate.
 677         * mep-desc.h: Regenerate.
 678         * mep-opc.h: Regenerate.
 679         * mt-desc.h: Regenerate.
 680         * mt-opc.h: Regenerate.
 681         * or1k-desc.h: Regenerate.
 682         * or1k-opc.h: Regenerate.
 683         * xc16x-desc.h: Regenerate.
 684         * xc16x-opc.h: Regenerate.
 685         * xstormy16-desc.h: Regenerate.
 686         * xstormy16-opc.h: Regenerate.
 687
 688 2017-01-02  Alan Modra  <amodra@gmail.com>
 689
 690         Update year range in copyright notice of all files.
 691
 692 For older changes see ChangeLog-2016
 693 \f
 694 Copyright (C) 2017 Free Software Foundation, Inc.
 695
 696 Copying and distribution of this file, with or without modification,
 697 are permitted in any medium without royalty provided the copyright
 698 notice and this notice are preserved.
 699
 700 Local Variables:
 701 mode: change-log
 702 left-margin: 8
 703 fill-column: 74
 704 version-control: never
 705 End: