opcodes/ChangeLog

   1 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
   2
   3         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
   4         architecuture defining the insn.
   5         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
   6         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
   7         field.
   8         Also include opcode/arm.h.
   9         * Makefile.am (arm-dis.lo): Update dependency list.
  10         * Makefile.in: Regenerate.
  11
  12 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
  13
  14         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
  15         reflect the change to the short immediate syntax.
  16
  17 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  18
  19         * or32-opc.c (debug): Warning fix.
  20         * po/POTFILES.in: Regenerate.
  21
  22         * maxq-dis.c: Formatting.
  23         (print_insn): Warning fix.
  24
  25 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
  26
  27         * arm-dis.c (WORD_ADDRESS): Define.
  28         (print_insn): Use it.  Correct big-endian end-of-section handling.
  29
  30 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  31             Vineet Sharma      <vineets@noida.hcltech.com>
  32
  33         * maxq-dis.c: New file.
  34         * disassemble.c (ARCH_maxq): Define.
  35         (disassembler): Add 'print_insn_maxq_little' for handling maxq
  36         instructions..
  37         * configure.in: Add case for bfd_maxq_arch.
  38         * configure: Regenerate.
  39         * Makefile.am: Add support for maxq-dis.c
  40         * Makefile.in: Regenerate.
  41         * aclocal.m4: Regenerate.
  42
  43 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  44
  45         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
  46         mode.
  47         * crx-dis.c: Likewise.
  48
  49 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  50
  51         Generally, handle CRISv32.
  52         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
  53         (struct cris_disasm_data): New type.
  54         (format_reg, format_hex, cris_constraint, print_flags)
  55         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
  56         callers changed.
  57         (format_sup_reg, print_insn_crisv32_with_register_prefix)
  58         (print_insn_crisv32_without_register_prefix)
  59         (print_insn_crisv10_v32_with_register_prefix)
  60         (print_insn_crisv10_v32_without_register_prefix)
  61         (cris_parse_disassembler_options): New functions.
  62         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
  63         parameter.  All callers changed.
  64         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
  65         failure.
  66         (cris_constraint) <case 'Y', 'U'>: New cases.
  67         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
  68         for constraint 'n'.
  69         (print_with_operands) <case 'Y'>: New case.
  70         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
  71         <case 'N', 'Y', 'Q'>: New cases.
  72         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
  73         (print_insn_cris_with_register_prefix)
  74         (print_insn_cris_without_register_prefix): Call
  75         cris_parse_disassembler_options.
  76         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
  77         for CRISv32 and the size of immediate operands.  New v32-only
  78         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
  79         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
  80         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
  81         Change brp to be v3..v10.
  82         (cris_support_regs): New vector.
  83         (cris_opcodes): Update head comment.  New format characters '[',
  84         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
  85         Add new opcodes for v32 and adjust existing opcodes to accommodate
  86         differences to earlier variants.
  87         (cris_cond15s): New vector.
  88
  89 2004-11-04 Jan Beulich <jbeulich@novell.com>
  90
  91         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
  92         (indirEb): Remove.
  93         (Mp): Use f_mode rather than none at all.
  94         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
  95         replaces what previously was x_mode; x_mode now means 128-bit SSE
  96         operands.
  97         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
  98         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
  99         pinsrw's second operand is Edqw.
 100         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 101         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 102         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 103         mode when an operand size override is present or always suffixing.
 104         More instructions will need to be added to this group.
 105         (putop): Handle new macro chars 'C' (short/long suffix selector),
 106         'I' (Intel mode override for following macro char), and 'J' (for
 107         adding the 'l' prefix to far branches in AT&T mode). When an
 108         alternative was specified in the template, honor macro character when
 109         specified for Intel mode.
 110         (OP_E): Handle new *_mode values. Correct pointer specifications for
 111         memory operands. Consolidate output of index register.
 112         (OP_G): Handle new *_mode values.
 113         (OP_I): Handle const_1_mode.
 114         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 115         respective opcode prefix bits have been consumed.
 116         (OP_EM, OP_EX): Provide some default handling for generating pointer
 117         specifications.
 118
 119 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 120
 121         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 122         COP_INST macro.
 123
 124 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 125
 126         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 127         (getregliststring): Support HI/LO and user registers.
 128         * crx-opc.c (crx_instruction): Update data structure according to the
 129         rearrangement done in CRX opcode header file.
 130         (crx_regtab):  Likewise.
 131         (crx_optab):  Likewise.
 132         (crx_instruction): Reorder load/stor instructions, remove unsupported
 133         formats.
 134         support new Co-Processor instruction 'cpi'.
 135
 136 2004-10-27  Nick Clifton  <nickc@redhat.com>
 137
 138         * opcodes/iq2000-asm.c: Regenerate.
 139         * opcodes/iq2000-desc.c: Regenerate.
 140         * opcodes/iq2000-desc.h: Regenerate.
 141         * opcodes/iq2000-dis.c: Regenerate.
 142         * opcodes/iq2000-ibld.c: Regenerate.
 143         * opcodes/iq2000-opc.c: Regenerate.
 144         * opcodes/iq2000-opc.h: Regenerate.
 145
 146 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 147
 148         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 149         us4, us5 (respectively).
 150         Remove unsupported 'popa' instruction.
 151         Reverse operands order in store co-processor instructions.
 152
 153 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 154
 155         * Makefile.am: Run "make dep-am"
 156         * Makefile.in: Regenerate.
 157
 158 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 159
 160         * xtensa-dis.c: Use ISO C90 formatting.
 161
 162 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 163
 164         * ppc-opc.c: Revert 2004-09-09 change.
 165
 166 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 167
 168         * xtensa-dis.c (state_names): Delete.
 169         (fetch_data): Use xtensa_isa_maxlength.
 170         (print_xtensa_operand): Replace operand parameter with opcode/operand
 171         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 172         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 173         instruction bundles.  Use xmalloc instead of malloc.
 174
 175 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 176
 177         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 178         initializers.
 179
 180 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 181
 182         * crx-opc.c (crx_instruction): Support Co-processor insns.
 183         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 184         (getregliststring): Change function to use the above enum.
 185         (print_arg): Handle CO-Processor insns.
 186         (crx_cinvs): Add 'b' option to invalidate the branch-target
 187         cache.
 188
 189 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 190
 191         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 192         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 193         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 194         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 195         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 196
 197 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 198
 199         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 200         rather than add it.
 201
 202 2004-09-30  Paul Brook  <paul@codesourcery.com>
 203
 204         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 205         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 206
 207 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 210         (CONFIG_STATUS_DEPENDENCIES): New.
 211         (Makefile): Removed.
 212         (config.status): Likewise.
 213         * Makefile.in: Regenerated.
 214
 215 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 216
 217         * Makefile.am: Run "make dep-am".
 218         * Makefile.in: Regenerate.
 219         * aclocal.m4: Regenerate.
 220         * configure: Regenerate.
 221         * po/POTFILES.in: Regenerate.
 222         * po/opcodes.pot: Regenerate.
 223
 224 2004-09-11  Andreas Schwab  <schwab@suse.de>
 225
 226         * configure: Rebuild.
 227
 228 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 229
 230         * ppc-opc.c (L): Make this field not optional.
 231
 232 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 233
 234         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 235         Fix parameter to 'm[t|f]csr' insns.
 236
 237 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 238
 239         * configure.in: Autoupdate to autoconf 2.59.
 240         * aclocal.m4: Rebuild with aclocal 1.4p6.
 241         * configure: Rebuild with autoconf 2.59.
 242         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 243         bfd changes for autoconf 2.59 on the way).
 244         * config.in: Rebuild with autoheader 2.59.
 245
 246 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 247
 248         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 249
 250 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 251
 252         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 253         (GRPPADLCK2): New define.
 254         (twobyte_has_modrm): True for 0xA6.
 255         (grps): GRPPADLCK2 for opcode 0xA6.
 256
 257 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 258
 259         Introduce SH2a support.
 260         * sh-opc.h (arch_sh2a_base): Renumber.
 261         (arch_sh2a_nofpu_base): Remove.
 262         (arch_sh_base_mask): Adjust.
 263         (arch_opann_mask): New.
 264         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 265         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 266         (sh_table): Adjust whitespace.
 267         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 268         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 269         instruction list throughout.
 270         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 271         of arch_sh2a in instruction list throughout.
 272         (arch_sh2e_up): Accomodate above changes.
 273         (arch_sh2_up): Ditto.
 274         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 275         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 276         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 277         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 278         * sh-opc.h (arch_sh2a_nofpu): New.
 279         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 280         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 281         instruction.
 282         2004-01-20  DJ Delorie  <dj@redhat.com>
 283         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 284         2003-12-29  DJ Delorie  <dj@redhat.com>
 285         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 286         sh_opcode_info, sh_table): Add sh2a support.
 287         (arch_op32): New, to tag 32-bit opcodes.
 288         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 289         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 290         * sh-opc.h (arch_sh2a): Add.
 291         * sh-dis.c (arch_sh2a): Handle.
 292         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 293
 294 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 295
 296         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 297
 298 2004-07-22  Nick Clifton  <nickc@redhat.com>
 299
 300         PR/280
 301         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 302         insns - this is done by objdump itself.
 303         * h8500-dis.c (print_insn_h8500): Likewise.
 304
 305 2004-07-21  Jan Beulich <jbeulich@novell.com>
 306
 307         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 308         regardless of address size prefix in effect.
 309         (ptr_reg): Size or address registers does not depend on rex64, but
 310         on the presence of an address size override.
 311         (OP_MMX): Use rex.x only for xmm registers.
 312         (OP_EM): Use rex.z only for xmm registers.
 313
 314 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 315
 316         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 317         move/branch operations to the bottom so that VR5400 multimedia
 318         instructions take precedence in disassembly.
 319
 320 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 321
 322         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 323         ISA-specific "break" encoding.
 324
 325 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 326
 327         * arm-opc.h: Fix typo in comment.
 328
 329 2004-07-11  Andreas Schwab  <schwab@suse.de>
 330
 331         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 332
 333 2004-07-09  Andreas Schwab  <schwab@suse.de>
 334
 335         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 336
 337 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 338
 339         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 340         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 341         (crx-dis.lo): New target.
 342         (crx-opc.lo): Likewise.
 343         * Makefile.in: Regenerate.
 344         * configure.in: Handle bfd_crx_arch.
 345         * configure: Regenerate.
 346         * crx-dis.c: New file.
 347         * crx-opc.c: New file.
 348         * disassemble.c (ARCH_crx): Define.
 349         (disassembler): Handle ARCH_crx.
 350
 351 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 352
 353         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 354         * ia64-asmtab.c: Regnerate.
 355
 356 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 357
 358         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 359         (extract_fxm): Don't test dialect.
 360         (XFXFXM_MASK): Include the power4 bit.
 361         (XFXM): Add p4 param.
 362         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 363
 364 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 365
 366         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 367         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 368
 369 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 370
 371         * ppc-opc.c (BH, XLBH_MASK): Define.
 372         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 373
 374 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 375
 376         * i386-dis.c (x_mode): Comment.
 377         (two_source_ops): File scope.
 378         (float_mem): Correct fisttpll and fistpll.
 379         (float_mem_mode): New table.
 380         (dofloat): Use it.
 381         (OP_E): Correct intel mode PTR output.
 382         (ptr_reg): Use open_char and close_char.
 383         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 384         operands.  Set two_source_ops.
 385
 386 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 387
 388         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 389         instead of _raw_size.
 390
 391 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 392
 393         * ia64-gen.c (in_iclass): Handle more postinc st
 394         and ld variants.
 395         * ia64-asmtab.c: Rebuilt.
 396
 397 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 398
 399         * s390-opc.txt: Correct architecture mask for some opcodes.
 400         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 401         in the esa mode as well.
 402
 403 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 404
 405         * sh-dis.c (target_arch): Make unsigned.
 406         (print_insn_sh): Replace (most of) switch with a call to
 407         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 408         * sh-opc.h: Redefine architecture flags values.
 409         Add sh3-nommu architecture.
 410         Reorganise <arch>_up macros so they make more visual sense.
 411         (SH_MERGE_ARCH_SET): Define new macro.
 412         (SH_VALID_BASE_ARCH_SET): Likewise.
 413         (SH_VALID_MMU_ARCH_SET): Likewise.
 414         (SH_VALID_CO_ARCH_SET): Likewise.
 415         (SH_VALID_ARCH_SET): Likewise.
 416         (SH_MERGE_ARCH_SET_VALID): Likewise.
 417         (SH_ARCH_SET_HAS_FPU): Likewise.
 418         (SH_ARCH_SET_HAS_DSP): Likewise.
 419         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 420         (sh_get_arch_from_bfd_mach): Add prototype.
 421         (sh_get_arch_up_from_bfd_mach): Likewise.
 422         (sh_get_bfd_mach_from_arch_set): Likewise.
 423         (sh_merge_bfd_arc): Likewise.
 424
 425 2004-05-24  Peter Barada  <peter@the-baradas.com>
 426
 427         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 428         into new match_insn_m68k function.  Loop over canidate
 429         matches and select first that completely matches.
 430         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 431         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 432         to verify addressing for MAC/EMAC.
 433         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 434         reigster halves since 'fpu' and 'spl' look misleading.
 435         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 436         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 437         first, tighten up match masks.
 438         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 439         'size' from special case code in print_insn_m68k to
 440         determine decode size of insns.
 441
 442 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 443
 444         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 445         well as when -mpower4.
 446
 447 2004-05-13  Nick Clifton  <nickc@redhat.com>
 448
 449         * po/fr.po: Updated French translation.
 450
 451 2004-05-05  Peter Barada  <peter@the-baradas.com>
 452
 453         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 454         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 455         * m68k-op.c: Switch from ColdFire chips to core variants.
 456
 457 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 458
 459         PR 147.
 460         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 461
 462 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 463
 464         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 465         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 466
 467 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 468
 469         * sh-dis.c (print_insn_sh): Print the value in constant pool
 470         as a symbol if it looks like a symbol.
 471
 472 2004-04-22  Peter Barada <peter@the-baradas.com>
 473
 474         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 475         appropriate ColdFire architectures.
 476         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 477         mask addressing.
 478         Add EMAC instructions, fix MAC instructions. Remove
 479         macmw/macml/msacmw/msacml instructions since mask addressing now
 480         supported.
 481
 482 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 483
 484         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 485         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 486         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 487         macro.  Adjust all users.
 488
 489 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 490
 491         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 492         separately.
 493
 494 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 495
 496         * m32r-asm.c: Regenerate.
 497
 498 2004-03-29  Stan Shebs  <shebs@apple.com>
 499
 500         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 501         used.
 502
 503 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 504
 505         * aclocal.m4: Regenerate.
 506         * config.in: Regenerate.
 507         * configure: Regenerate.
 508         * po/POTFILES.in: Regenerate.
 509         * po/opcodes.pot: Regenerate.
 510
 511 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 512
 513         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 514         PPC_OPERANDS_GPR_0.
 515         * ppc-opc.c (RA0): Define.
 516         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 517         (RAOPT): Rename from RAO.  Update all uses.
 518         (powerpc_opcodes): Use RA0 as appropriate.
 519
 520 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 521
 522         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 523
 524 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 525
 526         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 527
 528 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 529
 530         * i386-dis.c (GRPPLOCK): Delete.
 531         (grps): Delete GRPPLOCK entry.
 532
 533 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 534
 535         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 536         (M, Mp): Use OP_M.
 537         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 538         (GRPPADLCK): Define.
 539         (dis386): Use NOP_Fixup on "nop".
 540         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 541         (twobyte_has_modrm): Set for 0xa7.
 542         (padlock_table): Delete.  Move to..
 543         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 544         and clflush.
 545         (print_insn): Revert PADLOCK_SPECIAL code.
 546         (OP_E): Delete sfence, lfence, mfence checks.
 547
 548 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 549
 550         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 551         (INVLPG_Fixup): New function.
 552         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 553
 554 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 555
 556         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 557         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 558         (padlock_table): New struct with PadLock instructions.
 559         (print_insn): Handle PADLOCK_SPECIAL.
 560
 561 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 562
 563         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 564         (OP_E): Twiddle clflush to sfence here.
 565
 566 2004-03-08  Nick Clifton  <nickc@redhat.com>
 567
 568         * po/de.po: Updated German translation.
 569
 570 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 571
 572         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 573         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 574         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 575         accordingly.
 576
 577 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 578
 579         * frv-asm.c: Regenerate.
 580         * frv-desc.c: Regenerate.
 581         * frv-desc.h: Regenerate.
 582         * frv-dis.c: Regenerate.
 583         * frv-ibld.c: Regenerate.
 584         * frv-opc.c: Regenerate.
 585         * frv-opc.h: Regenerate.
 586
 587 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 588
 589         * frv-desc.c, frv-opc.c: Regenerate.
 590
 591 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 592
 593         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 594
 595 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 596
 597         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 598         Also correct mistake in the comment.
 599
 600 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 601
 602         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 603         ensure that double registers have even numbers.
 604         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 605         that reserved instruction 0xfffd does not decode the same
 606         as 0xfdfd (ftrv).
 607         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 608         REG_N refers to a double register.
 609         Add REG_N_B01 nibble type and use it instead of REG_NM
 610         in ftrv.
 611         Adjust the bit patterns in a few comments.
 612
 613 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 614
 615         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 616
 617 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 618
 619         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 620
 621 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 622
 623         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 624
 625 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 626
 627         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 628         mtivor32, mtivor33, mtivor34.
 629
 630 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 631
 632         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 633
 634 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 635
 636         * arm-opc.h Maverick accumulator register opcode fixes.
 637
 638 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 639
 640         * m32r-dis.c: Regenerate.
 641
 642 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 643
 644         * sh-opc.h (sh_table): "fsrra", not "fssra".
 645
 646 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 647
 648         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 649         contraints.
 650
 651 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 652
 653         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 654
 655 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 656
 657         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 658         1.  Don't print scale factor on AT&T mode when index missing.
 659
 660 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 661
 662         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 663         when loaded into XR registers.
 664
 665 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 666
 667         * frv-desc.h: Regenerate.
 668         * frv-desc.c: Regenerate.
 669         * frv-opc.c: Regenerate.
 670
 671 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 672
 673         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 674
 675 2004-01-09  Paul Brook  <paul@codesourcery.com>
 676
 677         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 678         specific opcodes.
 679
 680 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 681
 682         * Makefile.am (libopcodes_la_DEPENDENCIES)
 683         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 684         comment about the problem.
 685         * Makefile.in: Regenerate.
 686
 687 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 688
 689         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 690         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 691         cut&paste errors in shifting/truncating numerical operands.
 692         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 693         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 694         (parse_uslo16): Likewise.
 695         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 696         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 697         (parse_s12): Likewise.
 698         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 699         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 700         (parse_uslo16): Likewise.
 701         (parse_uhi16): Parse gothi and gotfuncdeschi.
 702         (parse_d12): Parse got12 and gotfuncdesc12.
 703         (parse_s12): Likewise.
 704
 705 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 706
 707         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 708         instruction which looks similar to an 'rla' instruction.
 709
 710 For older changes see ChangeLog-0203
 711 \f
 712 Local Variables:
 713 mode: change-log
 714 left-margin: 8
 715 fill-column: 74
 716 version-control: never
 717 End: