opcodes/ChangeLog

   1 2013-01-14  Will Newton <will.newton@imgtec.com>
   2
   3         * metag-dis.c (REG_WIDTH): Increase to 64.
   4
   5 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
   6
   7         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
   8         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
   9         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
  10         (SH6): Update.
  11         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
  12         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
  13         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
  14         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
  15
  16 2013-01-10  Will Newton <will.newton@imgtec.com>
  17
  18         * Makefile.am: Add Meta.
  19         * configure.in: Add Meta.
  20         * disassemble.c: Add Meta support.
  21         * metag-dis.c: New file.
  22         * Makefile.in: Regenerate.
  23         * configure: Regenerate.
  24
  25 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  26
  27         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
  28         (match_opcode): Rename to cr16_match_opcode.
  29
  30 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
  31
  32         * mips-dis.c: Add names for CP0 registers of r5900.
  33         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
  34         instructions sq and lq.
  35         Add support for MIPS r5900 CPU.
  36         Add support for 128 bit MMI (Multimedia Instructions).
  37         Add support for EE instructions (Emotion Engine).
  38         Disable unsupported floating point instructions (64 bit and
  39         undefined compare operations).
  40         Enable instructions of MIPS ISA IV which are supported by r5900.
  41         Disable 64 bit co processor instructions.
  42         Disable 64 bit multiplication and division instructions.
  43         Disable instructions for co-processor 2 and 3, because these are
  44         not supported (preparation for later VU0 support (Vector Unit)).
  45         Disable cvt.w.s because this behaves like trunc.w.s and the
  46         correct execution can't be ensured on r5900.
  47         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
  48         will confuse less developers and compilers.
  49
  50 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
  51
  52         * aarch64-opc.c (aarch64_print_operand): Change to print
  53         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
  54         in comment.
  55         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
  56         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
  57         OP_MOV_IMM_WIDE.
  58
  59 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
  60
  61         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
  62         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
  63
  64 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         * i386-gen.c (process_copyright): Update copyright year to 2013.
  67
  68 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  69
  70         * cr16-dis.c (match_opcode,make_instruction): Remove static
  71         declaration.
  72         (dwordU,wordU): Moved typedefs to opcode/cr16.h
  73         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
  74
  75 For older changes see ChangeLog-2012
  76 \f
  77 Copyright (C) 2013 Free Software Foundation, Inc.
  78
  79 Copying and distribution of this file, with or without modification,
  80 are permitted in any medium without royalty provided the copyright
  81 notice and this notice are preserved.
  82
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