1 2011-12-08 Andrew Pinski <apinski@cavium.com>
2 Adam Nemet <anemet@caviumnetworks.com>
4 * mips-dis.c (mips_arch_choices): Add Octeon2.
5 For "octeon+", just include OcteonP for the insn.
6 * mips-opc.c (IOCT): Include Octeon2.
7 (IOCTP): Include Octeon2.
9 (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
10 "ladd", "lai", "laid", "las", "lasd", "law", "lawd".
11 Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
12 loads are, and add IOCT2 to them.
14 Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
15 "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
18 2011-11-29 Andrew Pinski <apinski@cavium.com>
20 * mips-dis.c (mips_arch_choices): Add Octeon+.
21 * mips-opc.c (IOCT): Include Octeon+.
23 (mips_builtin_opcodes): Add "saa" and "saad".
25 2011-11-25 Pierre Muller <muller@ics.u-strasbg.fr>
27 * mips-dis.c (print_insn_micromips): Rename local variable iprintf
28 to infprintf to avoid shadow warning.
30 2011-11-25 Nick Clifton <nickc@redhat.com>
32 * po/it.po: Updated Italian translation.
34 2011-11-16 Maciej W. Rozycki <macro@codesourcery.com>
36 * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
39 2011-11-02 Nick Clifton <nickc@redhat.com>
41 * po/it.po: New Italian translation.
42 * configure.in (ALL_LINGUAS): Add it.
43 * configure: Regenerate.
44 * po/opcodes.pot: Regenerate.
46 2011-11-01 DJ Delorie <dj@redhat.com>
48 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
50 (MAINTAINERCLEANFILES): Add rl78-decode.c.
51 (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
52 * Makefile.in: Regenerate.
53 * configure.in: Add bfd_rl78_arch case.
54 * configure: Regenerate.
55 * disassemble.c: Define ARCH_rl78.
56 (disassembler): Add ARCH_rl78 case.
57 * rl78-decode.c: New file.
58 * rl78-decode.opc: New file.
59 * rl78-dis.c: New file.
61 2011-10-27 Peter Bergner <bergner@vnet.ibm.com>
63 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
64 dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
65 diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
68 2011-10-26 Nick Clifton <nickc@redhat.com>
71 * i386-dis.c (print_insn): Fix testing of array subscript.
73 2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
75 * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
76 * epiphany-asm.c, epiphany-opc.h: Regenerate.
78 2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
80 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
81 (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
82 epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
83 (CLEANFILES): Add stamp-epiphany.
84 (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
85 (stamp-epiphany): New rule.
86 * configure.in: Handle bfd_epiphany_arch.
87 * disassemble.c (ARCH_epiphany): Define.
88 (disassembler): Handle bfd_arch_epiphany.
89 * epiphany-asm.c: New file.
90 * epiphany-desc.c: New file.
91 * epiphany-desc.h: New file.
92 * epiphany-dis.c: New file.
93 * epiphany-ibld.c: New file.
94 * epiphany-opc.c: New file.
95 * epiphany-opc.h: New file.
96 * Makefile.in: Regenerate.
97 * configure: Regenerate.
98 * po/POTFILES.in: Regenerate.
99 * po/opcodes.pot: Regenerate.
101 2011-10-24 Julian Brown <julian@codesourcery.com>
103 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
105 2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
107 * s390-opc.txt: Add CPUMF instructions.
109 2011-10-18 Jie Zhang <jie@codesourcery.com>
110 Julian Brown <julian@codesourcery.com>
112 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
114 2011-10-10 Nick Clifton <nickc@redhat.com>
116 * po/es.po: Updated Spanish translation.
117 * po/fi.po: Updated Finnish translation.
119 2011-09-28 Jan Beulich <jbeulich@suse.com>
121 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
123 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
124 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
125 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
126 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
127 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
128 on DFP quad instructions.
130 2011-09-27 David S. Miller <davem@davemloft.net>
132 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
133 to a float instead of an integer register.
135 2011-09-26 David S. Miller <davem@davemloft.net>
137 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
140 2011-09-21 David S. Miller <davem@davemloft.net>
142 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
143 bits. Fix "fchksm16" mnemonic.
145 2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
147 The changes below bring 'mov' and 'ticc' instructions into line
148 with the V8 SPARC Architecture Manual.
149 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
150 * sparc-opc.c (sparc_opcodes): Add alias entries for
151 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
152 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
153 * sparc-opc.c (sparc_opcodes): Move/Change entries for
154 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
156 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
159 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
160 This has been reported as being accepted by the Sun assmebler.
162 2011-09-08 David S. Miller <davem@davemloft.net>
164 * sparc-opc.c (pdistn): Destination is integer not float register.
166 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
169 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
171 2011-08-26 Nick Clifton <nickc@redhat.com>
173 * po/es.po: Updated Spanish translation.
175 2011-08-22 Nick Clifton <nickc@redhat.com>
177 * Makefile.am (CPUDIR): Redfine to point to top level cpu
179 (stamp-frv): Use CPUDIR.
180 (stamp-iq2000): Likewise.
181 (stamp-lm32): Likewise.
182 (stamp-m32c): Likewise.
183 (stamp-mt): Likewise.
184 (stamp-xc16x): Likewise.
185 * Makefile.in: Regenerate.
187 2011-08-09 Chao-ying Fu <fu@mips.com>
188 Maciej W. Rozycki <macro@codesourcery.com>
190 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
192 (print_insn_args, print_insn_micromips): Handle MCU.
193 * micromips-opc.c (MC): New macro.
194 (micromips_opcodes): Add "aclr", "aset" and "iret".
195 * mips-opc.c (MC): New macro.
196 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
198 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
200 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
201 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
202 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
203 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
204 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
205 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
206 (WR_s): Update macro.
207 (micromips_opcodes): Update register use flags of: "addiu",
208 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
209 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
210 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
211 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
212 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
213 "swm" and "xor" instructions.
215 2011-08-05 David S. Miller <davem@davemloft.net>
217 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
219 (print_insn_sparc): Handle '4', '5', and '(' format codes.
220 Accept %asr numbers below 28.
221 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
224 2011-08-02 Quentin Neill <quentin.neill@amd.com>
226 * i386-dis.c (xop_table): Remove spurious bextr insn.
228 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
231 * i386-dis.c (print_insn): Optimize info->mach check.
233 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
236 * i386-opc.tbl: Add Disp32S to 64bit call.
237 * i386-tbl.h: Regenerated.
239 2011-07-24 Chao-ying Fu <fu@mips.com>
240 Maciej W. Rozycki <macro@codesourcery.com>
242 * micromips-opc.c: New file.
243 * mips-dis.c (micromips_to_32_reg_b_map): New array.
244 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
245 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
246 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
247 (micromips_to_32_reg_q_map): Likewise.
248 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
249 (micromips_ase): New variable.
250 (is_micromips): New function.
251 (set_default_mips_dis_options): Handle microMIPS ASE.
252 (print_insn_micromips): New function.
253 (is_compressed_mode_p): Likewise.
254 (_print_insn_mips): Handle microMIPS instructions.
255 * Makefile.am (CFILES): Add micromips-opc.c.
256 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
257 * Makefile.in: Regenerate.
258 * configure: Regenerate.
260 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
261 (micromips_to_32_reg_i_map): Likewise.
262 (micromips_to_32_reg_m_map): Likewise.
263 (micromips_to_32_reg_n_map): New macro.
265 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
267 * mips-opc.c (NODS): New macro.
268 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
269 (DSP_VOLA): Likewise.
270 (mips_builtin_opcodes): Add NODS annotation to "deret" and
271 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
272 place of TRAP for "wait", "waiti" and "yield".
273 * mips16-opc.c (NODS): New macro.
274 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
275 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
276 "restore" and "save".
278 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
280 * configure.in: Handle bfd_k1om_arch.
281 * configure: Regenerated.
283 * disassemble.c (disassembler): Handle bfd_k1om_arch.
285 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
286 bfd_mach_k1om_intel_syntax.
288 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
289 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
290 (cpu_flags): Add CpuK1OM.
292 * i386-opc.h (CpuK1OM): New.
293 (i386_cpu_flags): Add cpuk1om.
295 * i386-init.h: Regenerated.
296 * i386-tbl.h: Likewise.
298 2011-07-12 Nick Clifton <nickc@redhat.com>
300 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
303 2011-07-01 Nick Clifton <nickc@redhat.com>
306 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
307 insns using post-increment addressing.
309 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
311 * i386-dis.c (vex_len_table): Update rorxS.
313 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
315 AVX Programming Reference (June, 2011)
316 * i386-dis.c (vex_len_table): Correct rorxS.
318 * i386-opc.tbl: Correct rorx.
319 * i386-tbl.h: Regenerated.
321 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
323 * tilegx-opc.c (find_opcode): Replace "index" with "i".
324 * tilepro-opc.c (find_opcode): Likewise.
326 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
328 * mips16-opc.c (jalrc, jrc): Move earlier in file.
330 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
332 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
335 2011-06-17 Andreas Schwab <schwab@redhat.com>
337 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
338 (MOSTLYCLEANFILES): ... here.
339 * Makefile.in: Regenerate.
341 2011-06-14 Alan Modra <amodra@gmail.com>
343 * Makefile.in: Regenerate.
345 2011-06-13 Walter Lee <walt@tilera.com>
347 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
348 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
349 * Makefile.in: Regenerate.
350 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
351 * configure: Regenerate.
352 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
353 * po/POTFILES.in: Regenerate.
354 * tilegx-dis.c: New file.
355 * tilegx-opc.c: New file.
356 * tilepro-dis.c: New file.
357 * tilepro-opc.c: New file.
359 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
361 AVX Programming Reference (June, 2011)
362 * i386-dis.c (XMGatherQ): New.
363 * i386-dis.c (EXxmm_mb): New.
364 (EXxmm_mb): Likewise.
365 (EXxmm_mw): Likewise.
366 (EXxmm_md): Likewise.
367 (EXxmm_mq): Likewise.
370 (VexGatherQ): Likewise.
371 (MVexVSIBDWpX): Likewise.
372 (MVexVSIBQWpX): Likewise.
373 (xmm_mb_mode): Likewise.
374 (xmm_mw_mode): Likewise.
375 (xmm_md_mode): Likewise.
376 (xmm_mq_mode): Likewise.
377 (xmmdw_mode): Likewise.
378 (xmmqd_mode): Likewise.
379 (ymmxmm_mode): Likewise.
380 (vex_vsib_d_w_dq_mode): Likewise.
381 (vex_vsib_q_w_dq_mode): Likewise.
382 (MOD_VEX_0F385A_PREFIX_2): Likewise.
383 (MOD_VEX_0F388C_PREFIX_2): Likewise.
384 (MOD_VEX_0F388E_PREFIX_2): Likewise.
385 (PREFIX_0F3882): Likewise.
386 (PREFIX_VEX_0F3816): Likewise.
387 (PREFIX_VEX_0F3836): Likewise.
388 (PREFIX_VEX_0F3845): Likewise.
389 (PREFIX_VEX_0F3846): Likewise.
390 (PREFIX_VEX_0F3847): Likewise.
391 (PREFIX_VEX_0F3858): Likewise.
392 (PREFIX_VEX_0F3859): Likewise.
393 (PREFIX_VEX_0F385A): Likewise.
394 (PREFIX_VEX_0F3878): Likewise.
395 (PREFIX_VEX_0F3879): Likewise.
396 (PREFIX_VEX_0F388C): Likewise.
397 (PREFIX_VEX_0F388E): Likewise.
398 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
399 (PREFIX_VEX_0F38F5): Likewise.
400 (PREFIX_VEX_0F38F6): Likewise.
401 (PREFIX_VEX_0F3A00): Likewise.
402 (PREFIX_VEX_0F3A01): Likewise.
403 (PREFIX_VEX_0F3A02): Likewise.
404 (PREFIX_VEX_0F3A38): Likewise.
405 (PREFIX_VEX_0F3A39): Likewise.
406 (PREFIX_VEX_0F3A46): Likewise.
407 (PREFIX_VEX_0F3AF0): Likewise.
408 (VEX_LEN_0F3816_P_2): Likewise.
409 (VEX_LEN_0F3819_P_2): Likewise.
410 (VEX_LEN_0F3836_P_2): Likewise.
411 (VEX_LEN_0F385A_P_2_M_0): Likewise.
412 (VEX_LEN_0F38F5_P_0): Likewise.
413 (VEX_LEN_0F38F5_P_1): Likewise.
414 (VEX_LEN_0F38F5_P_3): Likewise.
415 (VEX_LEN_0F38F6_P_3): Likewise.
416 (VEX_LEN_0F38F7_P_1): Likewise.
417 (VEX_LEN_0F38F7_P_2): Likewise.
418 (VEX_LEN_0F38F7_P_3): Likewise.
419 (VEX_LEN_0F3A00_P_2): Likewise.
420 (VEX_LEN_0F3A01_P_2): Likewise.
421 (VEX_LEN_0F3A38_P_2): Likewise.
422 (VEX_LEN_0F3A39_P_2): Likewise.
423 (VEX_LEN_0F3A46_P_2): Likewise.
424 (VEX_LEN_0F3AF0_P_3): Likewise.
425 (VEX_W_0F3816_P_2): Likewise.
426 (VEX_W_0F3818_P_2): Likewise.
427 (VEX_W_0F3819_P_2): Likewise.
428 (VEX_W_0F3836_P_2): Likewise.
429 (VEX_W_0F3846_P_2): Likewise.
430 (VEX_W_0F3858_P_2): Likewise.
431 (VEX_W_0F3859_P_2): Likewise.
432 (VEX_W_0F385A_P_2_M_0): Likewise.
433 (VEX_W_0F3878_P_2): Likewise.
434 (VEX_W_0F3879_P_2): Likewise.
435 (VEX_W_0F3A00_P_2): Likewise.
436 (VEX_W_0F3A01_P_2): Likewise.
437 (VEX_W_0F3A02_P_2): Likewise.
438 (VEX_W_0F3A38_P_2): Likewise.
439 (VEX_W_0F3A39_P_2): Likewise.
440 (VEX_W_0F3A46_P_2): Likewise.
441 (MOD_VEX_0F3818_PREFIX_2): Removed.
442 (MOD_VEX_0F3819_PREFIX_2): Likewise.
443 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
444 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
445 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
446 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
447 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
448 (VEX_LEN_0F3A0E_P_2): Likewise.
449 (VEX_LEN_0F3A0F_P_2): Likewise.
450 (VEX_LEN_0F3A42_P_2): Likewise.
451 (VEX_LEN_0F3A4C_P_2): Likewise.
452 (VEX_W_0F3818_P_2_M_0): Likewise.
453 (VEX_W_0F3819_P_2_M_0): Likewise.
454 (prefix_table): Updated.
455 (three_byte_table): Likewise.
456 (vex_table): Likewise.
457 (vex_len_table): Likewise.
458 (vex_w_table): Likewise.
459 (mod_table): Likewise.
460 (putop): Handle "LW".
461 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
462 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
463 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
465 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
466 vex_vsib_q_w_dq_mode.
467 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
470 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
471 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
472 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
473 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
474 (opcode_modifiers): Add VecSIB.
476 * i386-opc.h (CpuAVX2): New.
478 (CpuLZCNT): Likewise.
479 (CpuINVPCID): Likewise.
480 (VecSIB128): Likewise.
481 (VecSIB256): Likewise.
483 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
484 (i386_opcode_modifier): Add vecsib.
486 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
487 * i386-init.h: Regenerated.
488 * i386-tbl.h: Likewise.
490 2011-06-03 Quentin Neill <quentin.neill@amd.com>
492 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
493 * i386-init.h: Regenerated.
495 2011-06-03 Nick Clifton <nickc@redhat.com>
498 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
499 computing address offsets.
500 (print_arm_address): Likewise.
501 (print_insn_arm): Likewise.
502 (print_insn_thumb16): Likewise.
503 (print_insn_thumb32): Likewise.
505 2011-06-02 Jie Zhang <jie@codesourcery.com>
506 Nathan Sidwell <nathan@codesourcery.com>
507 Maciej Rozycki <macro@codesourcery.com>
509 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
511 (print_arm_address): Likewise. Elide positive #0 appropriately.
512 (print_insn_arm): Likewise.
514 2011-06-02 Nick Clifton <nickc@redhat.com>
517 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
518 passed to print_address_func.
520 2011-06-02 Nick Clifton <nickc@redhat.com>
522 * arm-dis.c: Fix spelling mistakes.
523 * op/opcodes.pot: Regenerate.
525 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
527 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
528 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
529 * s390-opc.txt: Fix cxr instruction type.
531 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
533 * s390-opc.c: Add new instruction types marking register pair
535 * s390-opc.txt: Match instructions having register pair operands
536 to the new instruction types.
538 2011-05-19 Nick Clifton <nickc@redhat.com>
540 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
543 2011-05-10 Quentin Neill <quentin.neill@amd.com>
545 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
546 * i386-init.h: Regenerated.
548 2011-04-27 Nick Clifton <nickc@redhat.com>
550 * po/da.po: Updated Danish translation.
552 2011-04-26 Anton Blanchard <anton@samba.org>
554 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
556 2011-04-21 DJ Delorie <dj@redhat.com>
558 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
559 * rx-decode.c: Regenerate.
561 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
563 * i386-init.h: Regenerated.
565 2011-04-19 Quentin Neill <quentin.neill@amd.com>
567 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
570 2011-04-13 Nick Clifton <nickc@redhat.com>
572 * v850-dis.c (disassemble): Always print a closing square brace if
573 an opening square brace was printed.
575 2011-04-12 Nick Clifton <nickc@redhat.com>
578 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
580 (print_insn_thumb32): Handle %L.
582 2011-04-11 Julian Brown <julian@codesourcery.com>
584 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
585 (print_insn_thumb32): Add APSR bitmask support.
587 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
589 * arm-dis.c (print_insn): init vars moved into private_data structure.
591 2011-03-24 Mike Frysinger <vapier@gentoo.org>
593 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
595 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
597 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
598 post-increment to support LPM Z+ instruction. Add support for 'E'
599 constraint for DES instruction.
600 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
602 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
604 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
606 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
608 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
609 Use branch types instead.
610 (print_insn): Likewise.
612 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
614 * mips-opc.c (mips_builtin_opcodes): Correct register use
615 annotation of "alnv.ps".
617 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
619 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
621 2011-02-22 Mike Frysinger <vapier@gentoo.org>
623 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
625 2011-02-22 Mike Frysinger <vapier@gentoo.org>
627 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
629 2011-02-19 Mike Frysinger <vapier@gentoo.org>
631 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
632 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
633 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
634 exception, end_of_registers, msize, memory, bfd_mach.
635 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
636 LB0REG, LC1REG, LT1REG, LB1REG): Delete
637 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
638 (get_allreg): Change to new defines. Fallback to abort().
640 2011-02-14 Mike Frysinger <vapier@gentoo.org>
642 * bfin-dis.c: Add whitespace/parenthesis where needed.
644 2011-02-14 Mike Frysinger <vapier@gentoo.org>
646 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
649 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
651 * configure: Regenerate.
653 2011-02-13 Mike Frysinger <vapier@gentoo.org>
655 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
657 2011-02-13 Mike Frysinger <vapier@gentoo.org>
659 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
660 dregs only when P is set, and dregs_lo otherwise.
662 2011-02-13 Mike Frysinger <vapier@gentoo.org>
664 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
666 2011-02-12 Mike Frysinger <vapier@gentoo.org>
668 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
670 2011-02-12 Mike Frysinger <vapier@gentoo.org>
672 * bfin-dis.c (machine_registers): Delete REG_GP.
673 (reg_names): Delete "GP".
674 (decode_allregs): Change REG_GP to REG_LASTREG.
676 2011-02-12 Mike Frysinger <vapier@gentoo.org>
678 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
681 2011-02-11 Mike Frysinger <vapier@gentoo.org>
683 * bfin-dis.c (reg_names): Add const.
684 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
685 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
686 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
687 decode_counters, decode_allregs): Likewise.
689 2011-02-09 Michael Snyder <msnyder@vmware.com>
691 * i386-dis.c (OP_J): Parenthesize expression to prevent
693 (print_insn): Fix indentation off-by-one.
695 2011-02-01 Nick Clifton <nickc@redhat.com>
697 * po/da.po: Updated Danish translation.
699 2011-01-21 Dave Murphy <davem@devkitpro.org>
701 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
703 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
705 * i386-dis.c (sIbT): New.
706 (b_T_mode): Likewise.
707 (dis386): Replace sIb with sIbT on "pushT".
708 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
709 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
711 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
713 * i386-init.h: Regenerated.
714 * i386-tbl.h: Regenerated
716 2011-01-17 Quentin Neill <quentin.neill@amd.com>
718 * i386-dis.c (REG_XOP_TBM_01): New.
719 (REG_XOP_TBM_02): New.
720 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
721 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
722 entries, and add bextr instruction.
724 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
725 (cpu_flags): Add CpuTBM.
727 * i386-opc.h (CpuTBM) New.
728 (i386_cpu_flags): Add bit cputbm.
730 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
731 blcs, blsfill, blsic, t1mskc, and tzmsk.
733 2011-01-12 DJ Delorie <dj@redhat.com>
735 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
737 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
739 * mips-dis.c (print_insn_args): Adjust the value to print the real
740 offset for "+c" argument.
742 2011-01-10 Nick Clifton <nickc@redhat.com>
744 * po/da.po: Updated Danish translation.
746 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
748 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
750 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
752 * i386-dis.c (REG_VEX_38F3): New.
753 (PREFIX_0FBC): Likewise.
754 (PREFIX_VEX_38F2): Likewise.
755 (PREFIX_VEX_38F3_REG_1): Likewise.
756 (PREFIX_VEX_38F3_REG_2): Likewise.
757 (PREFIX_VEX_38F3_REG_3): Likewise.
758 (PREFIX_VEX_38F7): Likewise.
759 (VEX_LEN_38F2_P_0): Likewise.
760 (VEX_LEN_38F3_R_1_P_0): Likewise.
761 (VEX_LEN_38F3_R_2_P_0): Likewise.
762 (VEX_LEN_38F3_R_3_P_0): Likewise.
763 (VEX_LEN_38F7_P_0): Likewise.
764 (dis386_twobyte): Use PREFIX_0FBC.
765 (reg_table): Add REG_VEX_38F3.
766 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
767 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
768 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
769 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
771 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
772 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
775 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
776 (cpu_flags): Add CpuBMI.
778 * i386-opc.h (CpuBMI): New.
779 (i386_cpu_flags): Add cpubmi.
781 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
782 * i386-init.h: Regenerated.
783 * i386-tbl.h: Likewise.
785 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
787 * i386-dis.c (VexGdq): New.
788 (OP_VEX): Handle dq_mode.
790 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
792 * i386-gen.c (process_copyright): Update copyright to 2011.
794 For older changes see ChangeLog-2010
800 version-control: never