opcodes/ChangeLog

   1 2017-11-29  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
   4         entry.
   5         (operand_types): Remove Vec_Disp8 entry.
   6         * i386-opc.h (Vec_Disp8): Delete.
   7         (union i386_operand_type): Remove vec_disp8.
   8         (i386-opc.tbl): Remove Vec_Disp8.
   9         * i386-init.h, i386-tbl.h: Re-generate.
  10
  11 2017-11-29  Stefan Stroe  <stroestefan@gmail.com>
  12
  13         * po/Make-in (datadir): Define as @datadir@.
  14         (localedir): Define as @localedir@.
  15         (gnulocaledir, gettextsrcdir): Use @datarootdir@.
  16
  17 2017-11-27  Nick Clifton  <nickc@redhat.com>
  18
  19         * po/zh_CN.po: Updated simplified Chinese translation.
  20
  21 2017-11-24  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
  24         "df" groups.
  25
  26 2017-11-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  27
  28         * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
  29         * i386-tbl.h: Regenerate.
  30
  31 2017-11-23  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
  34         the 16-bit addressing case.
  35
  36 2017-11-23  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
  39         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
  40         * i386-opc.tbl (ud1, ud2b): Add operands.
  41         (ud0): New.
  42         * i386-tbl.h: Re-generate.
  43
  44 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  45
  46         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
  47         * i386-tbl.h: Regenerate.
  48
  49 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  50
  51         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
  52         * i386-tbl.h: Regenerate.
  53
  54 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  55
  56         *arc-opc (insert_rhv2): Check h-regs range.
  57
  58 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
  59
  60         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
  61         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
  62
  63 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  64
  65         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
  66         and AARCH64_FEATURE_F16.
  67
  68 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  69
  70         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
  71         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
  72         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
  73         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
  74         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
  75         (ldapur, ldapursw, stlur): New.
  76         * aarch64-dis-2.c: Regenerate.
  77
  78 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  79
  80         (get_valid_dis386): Never flag bad opcode when
  81         vex.register_specifier is beyond 7. Always store all four
  82         bits of it. Move 16-/32-bit override in EVEX handling after
  83         all to be overridden bits have been set.
  84         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  85         Use rex to determine GPR register set.
  86         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  87         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  88
  89 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  92         determine GPR register set.
  93
  94 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  95
  96         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  97         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  98         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  99         pass.
 100         (OP_REG_VexI4): Drop low 4 bits check.
 101
 102 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-reg.tbl (axl): Remove Acc and Byte.
 105         * i386-tbl.h: Re-generate.
 106
 107 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
 110         (vex_len_table): Use VPCOM.
 111
 112 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
 115         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
 116         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
 117         vpcmpw): Move up.
 118         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
 119         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
 120         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
 121         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
 122         vpcmpnltuw): New.
 123         * i386-tbl.h: Re-generate.
 124
 125 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
 128         smov, ssca, stos, ssto, xlat): Drop Disp*.
 129         * i386-tbl.h: Re-generate.
 130
 131 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
 134         xsaveopt64): Add No_qSuf.
 135         * i386-tbl.h: Re-generate.
 136
 137 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 138
 139         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
 140         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
 141         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
 142         sder32_el2, vncr_el2.
 143         (aarch64_sys_reg_supported_p): Likewise.
 144         (aarch64_pstatefields): Add dit register.
 145         (aarch64_pstatefield_supported_p): Likewise.
 146         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 147         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 148         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 149         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 150         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 151         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 152         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 153
 154 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 155
 156         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 157         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 158         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 159         (QL_STLW, QL_STLX): New.
 160
 161 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 162
 163         * aarch64-asm.h (ins_addr_offset): New.
 164         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 165         (aarch64_ins_addr_offset): New.
 166         * aarch64-asm-2.c: Regenerate.
 167         * aarch64-dis.h (ext_addr_offset): New.
 168         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 169         (aarch64_ext_addr_offset): New.
 170         * aarch64-dis-2.c: Regenerate.
 171         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 172         FLD_imm4_2 and FLD_SM3_imm2.
 173         * aarch64-opc.c (fields): Add FLD_imm6_2,
 174         FLD_imm4_2 and FLD_SM3_imm2.
 175         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 176         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 177         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 178         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 179         * aarch64-tbl.h
 180         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 181
 182 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 183
 184         * aarch64-tbl.h
 185         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 186         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 187         (aarch64_feature_fp_16_v8_2): New.
 188         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 189         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 190         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 191
 192 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 193
 194         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 195         (aarch64_feature_sha2, aarch64_feature_aes): New.
 196         (SHA2, AES): New.
 197         (AES_INSN, SHA2_INSN): New.
 198         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 199         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 200          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 201         Change to SHA2_INS.
 202
 203 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 204             Tamar Christina <tamar.christina@arm.com>
 205
 206         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 207         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 208
 209 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 210
 211         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 212
 213 2017-11-07  Alan Modra  <amodra@gmail.com>
 214
 215         * opintl.h: Formatting, comment fixes.
 216         (gettext, ngettext): Redefine when ENABLE_NLS.
 217         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 218         (_): Define using gettext.
 219         (textdomain, bindtextdomain): Use safer "do nothing".
 220
 221 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 222
 223         * arc-dis.c (print_hex): New variable.
 224         (parse_option): Check for hex option.
 225         (print_insn_arc): Use hexadecimal representation for short
 226         immediate values when requested.
 227         (print_arc_disassembler_options): Add hex option to the list.
 228
 229 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 230
 231         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 232         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 233         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 234         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 235         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 236         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 237         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 238         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 239         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 240         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 241         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 242         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 243         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 244         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 245         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 246         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 247         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 248         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 249         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 250         Changed opcodes.
 251         (prealloc, prefetch*): Place them before ld instruction.
 252         * arc-opc.c (skip_this_opcode): Add ARITH class.
 253
 254 2017-10-25  Alan Modra  <amodra@gmail.com>
 255
 256         PR 22348
 257         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 258         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 259         (imm4flag, size_changed): Likewise.
 260         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 261         (words, allWords, processing_argument_number): Likewise.
 262         (cst4flag, size_changed): Likewise.
 263         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 264         (crx_cst4_maps): Rename from cst4_maps.
 265         (crx_no_op_insn): Rename from no_op_insn.
 266
 267 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 268
 269         * riscv-opc.c (match_c_addi16sp) : New function.
 270         (match_c_addi4spn): New function.
 271         (match_c_lui): Don't allow 0-immediate encodings.
 272         (riscv_opcodes) <addi>: Use the above functions.
 273         <add>: Likewise.
 274         <c.addi4spn>: Likewise.
 275         <c.addi16sp>: Likewise.
 276
 277 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 278
 279         * i386-init.h: Regenerate
 280         * i386-tbl.h: Likewise
 281
 282 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 283
 284         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 285         (enum): Add EVEX_W_0F3854_P_2.
 286         * i386-dis-evex.h (evex_table): Updated.
 287         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 288         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 289         (cpu_flags): Add CpuAVX512_BITALG.
 290         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 291         (i386_cpu_flags): Add cpuavx512_bitalg..
 292         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 293         * i386-init.h: Regenerate.
 294         * i386-tbl.h: Likewise.
 295
 296 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 297
 298         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 299         * i386-dis-evex.h (evex_table): Updated.
 300         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 301         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 302         (cpu_flags): Add CpuAVX512_VNNI.
 303         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 304         (i386_cpu_flags): Add cpuavx512_vnni.
 305         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 306         * i386-init.h: Regenerate.
 307         * i386-tbl.h: Likewise.
 308
 309 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 310
 311         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 312         (enum): Remove VEX_LEN_0F3A44_P_2.
 313         (vex_len_table): Ditto.
 314         (enum): Remove VEX_W_0F3A44_P_2.
 315         (vew_w_table): Ditto.
 316         (prefix_table): Adjust instructions (see prefixes above).
 317         * i386-dis-evex.h (evex_table):
 318         Add new instructions (see prefixes above).
 319         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 320         (bitfield_cpu_flags): Ditto.
 321         * i386-opc.h (enum): Ditto.
 322         (i386_cpu_flags): Ditto.
 323         (CpuUnused): Comment out to avoid zero-width field problem.
 324         * i386-opc.tbl (vpclmulqdq): New instruction.
 325         * i386-init.h: Regenerate.
 326         * i386-tbl.h: Ditto.
 327
 328 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 329
 330         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 331         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 332         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 333         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 334         (vex_len_table): Ditto.
 335         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 336         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 337         (vew_w_table): Ditto.
 338         (prefix_table): Adjust instructions (see prefixes above).
 339         * i386-dis-evex.h (evex_table):
 340         Add new instructions (see prefixes above).
 341         * i386-gen.c (cpu_flag_init): Add VAES.
 342         (bitfield_cpu_flags): Ditto.
 343         * i386-opc.h (enum): Ditto.
 344         (i386_cpu_flags): Ditto.
 345         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 346         * i386-init.h: Regenerate.
 347         * i386-tbl.h: Ditto.
 348
 349 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 350
 351         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 352         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 353         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 354         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 355         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 356         (prefix_table): Updated (see prefixes above).
 357         (three_byte_table): Likewise.
 358         (vex_w_table): Likewise.
 359         * i386-dis-evex.h: Likewise.
 360         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 361         (cpu_flags): Add CpuGFNI.
 362         * i386-opc.h (enum): Add CpuGFNI.
 363         (i386_cpu_flags): Add cpugfni.
 364         * i386-opc.tbl: Add Intel GFNI instructions.
 365         * i386-init.h: Regenerate.
 366         * i386-tbl.h: Likewise.
 367
 368 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 369
 370         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 371         Define EXbScalar and EXwScalar for OP_EX.
 372         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 373         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 374         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 375         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 376         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 377         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 378         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 379         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 380         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 381         (OP_E_memory): Likewise.
 382         * i386-dis-evex.h: Updated.
 383         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 384         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 385         (cpu_flags): Add CpuAVX512_VBMI2.
 386         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 387         (i386_cpu_flags): Add cpuavx512_vbmi2.
 388         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 389         * i386-init.h: Regenerate.
 390         * i386-tbl.h: Likewise.
 391
 392 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 393
 394         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 395
 396 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 397
 398         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 399         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 400         K15. Add jmpix pattern.
 401
 402 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 403
 404         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 405
 406 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 407
 408         * s390-opc.c (INSTR_SI_RD): New macro.
 409         (INSTR_S_RD): Adjust example instruction.
 410         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 411         SI_RD.
 412
 413 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 414
 415         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 416         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 417         VLE multimple load/store instructions. Old e_ldm* variants are
 418         kept as aliases.
 419         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 420
 421 2017-09-27  Nick Clifton  <nickc@redhat.com>
 422
 423         PR 22179
 424         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 425         names for the fmv.x.s and fmv.s.x instructions respectively.
 426
 427 2017-09-26  do  <do@nerilex.org>
 428
 429         PR 22123
 430         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 431         be used on CPUs that have emacs support.
 432
 433 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 434
 435         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 436
 437 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 438
 439         * nds32-asm.c: Rename __BIT() to N32_BIT().
 440         * nds32-asm.h: Likewise.
 441         * nds32-dis.c: Likewise.
 442
 443 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         * i386-dis.c (last_active_prefix): Removed.
 446         (ckprefix): Don't set last_active_prefix.
 447         (NOTRACK_Fixup): Don't check last_active_prefix.
 448
 449 2017-08-31  Nick Clifton  <nickc@redhat.com>
 450
 451         * po/fr.po: Updated French translation.
 452
 453 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 454
 455         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 456         fields.
 457
 458 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 459             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 460
 461         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 462         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 463         New entries efs2 and spe2.
 464         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 465         (SPE2_OPCD_SEGS): New macro.
 466         (spe2_opcd_indices): New.
 467         (disassemble_init_powerpc): Handle SPE2 opcodes.
 468         (lookup_spe2): New function.
 469         (print_insn_powerpc): call lookup_spe2.
 470         * ppc-opc.c (insert_evuimm1_ex0): New function.
 471         (extract_evuimm1_ex0): Likewise.
 472         (insert_evuimm_lt8): Likewise.
 473         (extract_evuimm_lt8): Likewise.
 474         (insert_off_spe2): Likewise.
 475         (extract_off_spe2): Likewise.
 476         (insert_Ddd): Likewise.
 477         (extract_Ddd): Likewise.
 478         (DD): New operand.
 479         (EVUIMM_LT8): Likewise.
 480         (EVUIMM_LT16): Adjust.
 481         (MMMM): New operand.
 482         (EVUIMM_1): Likewise.
 483         (EVUIMM_1_EX0): Likewise.
 484         (EVUIMM_2): Adjust.
 485         (NNN): New operand.
 486         (VX_OFF_SPE2): Likewise.
 487         (BBB): Likewise.
 488         (DDD): Likewise.
 489         (VX_MASK_DDD): New mask.
 490         (HH): New operand.
 491         (VX_RA_CONST): New macro.
 492         (VX_RA_CONST_MASK): Likewise.
 493         (VX_RB_CONST): Likewise.
 494         (VX_RB_CONST_MASK): Likewise.
 495         (VX_OFF_SPE2_MASK): Likewise.
 496         (VX_SPE_CRFD): Likewise.
 497         (VX_SPE_CRFD_MASK VX): Likewise.
 498         (VX_SPE2_CLR): Likewise.
 499         (VX_SPE2_CLR_MASK): Likewise.
 500         (VX_SPE2_SPLATB): Likewise.
 501         (VX_SPE2_SPLATB_MASK): Likewise.
 502         (VX_SPE2_OCTET): Likewise.
 503         (VX_SPE2_OCTET_MASK): Likewise.
 504         (VX_SPE2_DDHH): Likewise.
 505         (VX_SPE2_DDHH_MASK): Likewise.
 506         (VX_SPE2_HH): Likewise.
 507         (VX_SPE2_HH_MASK): Likewise.
 508         (VX_SPE2_EVMAR): Likewise.
 509         (VX_SPE2_EVMAR_MASK): Likewise.
 510         (PPCSPE2): Likewise.
 511         (PPCEFS2): Likewise.
 512         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 513         (powerpc_macros): Map old SPE instructions have new names
 514         with the same opcodes. Add SPE2 instructions which just are
 515         mapped to SPE2.
 516         (spe2_opcodes): Add SPE2 opcodes.
 517
 518 2017-08-23  Alan Modra  <amodra@gmail.com>
 519
 520         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 521         extract functions earlier, deleting forward declarations.
 522         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 523         RA_MASK.
 524
 525 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 526
 527         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 528
 529 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 530             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 531
 532         * ppc-opc.c (insert_evuimm2_ex0): New function.
 533         (extract_evuimm2_ex0): Likewise.
 534         (insert_evuimm4_ex0): Likewise.
 535         (extract_evuimm4_ex0): Likewise.
 536         (insert_evuimm8_ex0): Likewise.
 537         (extract_evuimm8_ex0): Likewise.
 538         (insert_evuimm_lt16): Likewise.
 539         (extract_evuimm_lt16): Likewise.
 540         (insert_rD_rS_even): Likewise.
 541         (extract_rD_rS_even): Likewise.
 542         (insert_off_lsp): Likewise.
 543         (extract_off_lsp): Likewise.
 544         (RD_EVEN): New operand.
 545         (RS_EVEN): Likewise.
 546         (RSQ): Adjust.
 547         (EVUIMM_LT16): New operand.
 548         (HTM_SI): Adjust.
 549         (EVUIMM_2_EX0): New operand.
 550         (EVUIMM_4): Adjust.
 551         (EVUIMM_4_EX0): New operand.
 552         (EVUIMM_8): Adjust.
 553         (EVUIMM_8_EX0): New operand.
 554         (WS): Adjust.
 555         (VX_OFF): New operand.
 556         (VX_LSP): New macro.
 557         (VX_LSP_MASK): Likewise.
 558         (VX_LSP_OFF_MASK): Likewise.
 559         (PPC_OPCODE_LSP): Likewise.
 560         (vle_opcodes): Add LSP opcodes.
 561         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 562
 563 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 564
 565         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 566         register operands in CRC instructions.
 567         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 568         comments.
 569
 570 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 571
 572         * disassemble.c (disassembler): Mark big and mach with
 573         ATTRIBUTE_UNUSED.
 574
 575 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 576
 577         * disassemble.c (disassembler): Remove arch/mach/endian
 578         assertions.
 579
 580 2017-07-25  Nick Clifton  <nickc@redhat.com>
 581
 582         PR 21739
 583         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 584         message.
 585         (insert_r0): Likewise.
 586         (insert_r1): Likewise.
 587         (insert_r2): Likewise.
 588         (insert_r3): Likewise.
 589         (insert_sp): Likewise.
 590         (insert_gp): Likewise.
 591         (insert_pcl): Likewise.
 592         (insert_blink): Likewise.
 593         (insert_ilink1): Likewise.
 594         (insert_ilink2): Likewise.
 595         (insert_ras): Likewise.
 596         (insert_rbs): Likewise.
 597         (insert_rcs): Likewise.
 598         (insert_simm3s): Likewise.
 599         (insert_rrange): Likewise.
 600         (insert_r13el): Likewise.
 601         (insert_fpel): Likewise.
 602         (insert_blinkel): Likewise.
 603         (insert_pclel): Likewise.
 604         (insert_nps_bitop_size_2b): Likewise.
 605         (insert_nps_imm_offset): Likewise.
 606         (insert_nps_imm_entry): Likewise.
 607         (insert_nps_size_16bit): Likewise.
 608         (insert_nps_##NAME##_pos): Likewise.
 609         (insert_nps_##NAME): Likewise.
 610         (insert_nps_bitop_ins_ext): Likewise.
 611         (insert_nps_##NAME): Likewise.
 612         (insert_nps_min_hofs): Likewise.
 613         (insert_nps_##NAME): Likewise.
 614         (insert_nps_rbdouble_64): Likewise.
 615         (insert_nps_misc_imm_offset): Likewise.
 616         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 617         option description.
 618
 619 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 620             Jiong Wang  <jiong.wang@arm.com>
 621
 622         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 623         correct the print.
 624         * aarch64-dis-2.c: Regenerated.
 625
 626 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 627
 628         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 629         table.
 630
 631 2017-07-20  Nick Clifton  <nickc@redhat.com>
 632
 633         * po/de.po: Updated German translation.
 634
 635 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 636
 637         * arc-regs.h (sec_stat): New aux register.
 638         (aux_kernel_sp): Likewise.
 639         (aux_sec_u_sp): Likewise.
 640         (aux_sec_k_sp): Likewise.
 641         (sec_vecbase_build): Likewise.
 642         (nsc_table_top): Likewise.
 643         (nsc_table_base): Likewise.
 644         (ersec_stat): Likewise.
 645         (aux_sec_except): Likewise.
 646
 647 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 648
 649         * arc-opc.c (extract_uimm12_20): New function.
 650         (UIMM12_20): New operand.
 651         (SIMM3_5_S): Adjust.
 652         * arc-tbl.h (sjli): Add new instruction.
 653
 654 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 655             John Eric Martin  <John.Martin@emmicro-us.com>
 656
 657         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 658         (UIMM3_23): Adjust accordingly.
 659         * arc-regs.h: Add/correct jli_base register.
 660         * arc-tbl.h (jli_s): Likewise.
 661
 662 2017-07-18  Nick Clifton  <nickc@redhat.com>
 663
 664         PR 21775
 665         * aarch64-opc.c: Fix spelling typos.
 666         * i386-dis.c: Likewise.
 667
 668 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 669
 670         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 671         max_addr_offset and octets variables to size_t.
 672
 673 2017-07-12  Alan Modra  <amodra@gmail.com>
 674
 675         * po/da.po: Update from translationproject.org/latest/opcodes/.
 676         * po/de.po: Likewise.
 677         * po/es.po: Likewise.
 678         * po/fi.po: Likewise.
 679         * po/fr.po: Likewise.
 680         * po/id.po: Likewise.
 681         * po/it.po: Likewise.
 682         * po/nl.po: Likewise.
 683         * po/pt_BR.po: Likewise.
 684         * po/ro.po: Likewise.
 685         * po/sv.po: Likewise.
 686         * po/tr.po: Likewise.
 687         * po/uk.po: Likewise.
 688         * po/vi.po: Likewise.
 689         * po/zh_CN.po: Likewise.
 690
 691 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 692             Alan Modra  <amodra@gmail.com>
 693
 694         * cgen.sh: Mark generated files read-only.
 695         * epiphany-asm.c: Regenerate.
 696         * epiphany-desc.c: Regenerate.
 697         * epiphany-desc.h: Regenerate.
 698         * epiphany-dis.c: Regenerate.
 699         * epiphany-ibld.c: Regenerate.
 700         * epiphany-opc.c: Regenerate.
 701         * epiphany-opc.h: Regenerate.
 702         * fr30-asm.c: Regenerate.
 703         * fr30-desc.c: Regenerate.
 704         * fr30-desc.h: Regenerate.
 705         * fr30-dis.c: Regenerate.
 706         * fr30-ibld.c: Regenerate.
 707         * fr30-opc.c: Regenerate.
 708         * fr30-opc.h: Regenerate.
 709         * frv-asm.c: Regenerate.
 710         * frv-desc.c: Regenerate.
 711         * frv-desc.h: Regenerate.
 712         * frv-dis.c: Regenerate.
 713         * frv-ibld.c: Regenerate.
 714         * frv-opc.c: Regenerate.
 715         * frv-opc.h: Regenerate.
 716         * ip2k-asm.c: Regenerate.
 717         * ip2k-desc.c: Regenerate.
 718         * ip2k-desc.h: Regenerate.
 719         * ip2k-dis.c: Regenerate.
 720         * ip2k-ibld.c: Regenerate.
 721         * ip2k-opc.c: Regenerate.
 722         * ip2k-opc.h: Regenerate.
 723         * iq2000-asm.c: Regenerate.
 724         * iq2000-desc.c: Regenerate.
 725         * iq2000-desc.h: Regenerate.
 726         * iq2000-dis.c: Regenerate.
 727         * iq2000-ibld.c: Regenerate.
 728         * iq2000-opc.c: Regenerate.
 729         * iq2000-opc.h: Regenerate.
 730         * lm32-asm.c: Regenerate.
 731         * lm32-desc.c: Regenerate.
 732         * lm32-desc.h: Regenerate.
 733         * lm32-dis.c: Regenerate.
 734         * lm32-ibld.c: Regenerate.
 735         * lm32-opc.c: Regenerate.
 736         * lm32-opc.h: Regenerate.
 737         * lm32-opinst.c: Regenerate.
 738         * m32c-asm.c: Regenerate.
 739         * m32c-desc.c: Regenerate.
 740         * m32c-desc.h: Regenerate.
 741         * m32c-dis.c: Regenerate.
 742         * m32c-ibld.c: Regenerate.
 743         * m32c-opc.c: Regenerate.
 744         * m32c-opc.h: Regenerate.
 745         * m32r-asm.c: Regenerate.
 746         * m32r-desc.c: Regenerate.
 747         * m32r-desc.h: Regenerate.
 748         * m32r-dis.c: Regenerate.
 749         * m32r-ibld.c: Regenerate.
 750         * m32r-opc.c: Regenerate.
 751         * m32r-opc.h: Regenerate.
 752         * m32r-opinst.c: Regenerate.
 753         * mep-asm.c: Regenerate.
 754         * mep-desc.c: Regenerate.
 755         * mep-desc.h: Regenerate.
 756         * mep-dis.c: Regenerate.
 757         * mep-ibld.c: Regenerate.
 758         * mep-opc.c: Regenerate.
 759         * mep-opc.h: Regenerate.
 760         * mt-asm.c: Regenerate.
 761         * mt-desc.c: Regenerate.
 762         * mt-desc.h: Regenerate.
 763         * mt-dis.c: Regenerate.
 764         * mt-ibld.c: Regenerate.
 765         * mt-opc.c: Regenerate.
 766         * mt-opc.h: Regenerate.
 767         * or1k-asm.c: Regenerate.
 768         * or1k-desc.c: Regenerate.
 769         * or1k-desc.h: Regenerate.
 770         * or1k-dis.c: Regenerate.
 771         * or1k-ibld.c: Regenerate.
 772         * or1k-opc.c: Regenerate.
 773         * or1k-opc.h: Regenerate.
 774         * or1k-opinst.c: Regenerate.
 775         * xc16x-asm.c: Regenerate.
 776         * xc16x-desc.c: Regenerate.
 777         * xc16x-desc.h: Regenerate.
 778         * xc16x-dis.c: Regenerate.
 779         * xc16x-ibld.c: Regenerate.
 780         * xc16x-opc.c: Regenerate.
 781         * xc16x-opc.h: Regenerate.
 782         * xstormy16-asm.c: Regenerate.
 783         * xstormy16-desc.c: Regenerate.
 784         * xstormy16-desc.h: Regenerate.
 785         * xstormy16-dis.c: Regenerate.
 786         * xstormy16-ibld.c: Regenerate.
 787         * xstormy16-opc.c: Regenerate.
 788         * xstormy16-opc.h: Regenerate.
 789
 790 2017-07-07  Alan Modra  <amodra@gmail.com>
 791
 792         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 793         * m32c-dis.c: Regenerate.
 794         * mep-dis.c: Regenerate.
 795
 796 2017-07-05  Borislav Petkov  <bp@suse.de>
 797
 798         * i386-dis.c: Enable ModRM.reg /6 aliases.
 799
 800 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 801
 802         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 803         with vmrs and vmsr.
 804
 805 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 806
 807         * configure: Regenerate.
 808
 809 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 810
 811         * po/opcodes.pot: Regenerate.
 812
 813 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 814
 815         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 816         entries to the MSA ASE instruction block.
 817
 818 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 819             Maciej W. Rozycki  <macro@imgtec.com>
 820
 821         * micromips-opc.c (XPA, XPAVZ): New macros.
 822         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 823         "mthgc0".
 824
 825 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 826             Maciej W. Rozycki  <macro@imgtec.com>
 827
 828         * micromips-opc.c (I36): New macro.
 829         (micromips_opcodes): Add "eretnc".
 830
 831 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 832             Andrew Bennett  <andrew.bennett@imgtec.com>
 833
 834         * mips-dis.c (mips_calculate_combination_ases): Handle the
 835         ASE_XPA_VIRT flag.
 836         (parse_mips_ase_option): New function.
 837         (parse_mips_dis_option): Factor out ASE option handling to the
 838         new function.  Call `mips_calculate_combination_ases'.
 839         * mips-opc.c (XPAVZ): New macro.
 840         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 841         "mfhgc0", "mthc0" and "mthgc0".
 842
 843 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 844
 845         * mips-dis.c (mips_calculate_combination_ases): New function.
 846         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 847         calculation to the new function.
 848         (set_default_mips_dis_options): Call the new function.
 849
 850 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 851
 852         * arc-dis.c (parse_disassembler_options): Use
 853         FOR_EACH_DISASSEMBLER_OPTION.
 854
 855 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 856
 857         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 858         disassembler option strings.
 859         (parse_cpu_option): Likewise.
 860
 861 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 862
 863         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 864         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 865         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 866         (aarch64_feature_dotprod, DOT_INSN): New.
 867         (udot, sdot): New.
 868         * aarch64-dis-2.c: Regenerated.
 869
 870 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 871
 872         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 873
 874 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 875             Matthew Fortune  <matthew.fortune@imgtec.com>
 876             Andrew Bennett  <andrew.bennett@imgtec.com>
 877
 878         * mips-formats.h (INT_BIAS): New macro.
 879         (INT_ADJ): Redefine in INT_BIAS terms.
 880         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 881         (mips_print_save_restore): New function.
 882         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 883         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 884         call.
 885         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 886         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 887         OP_SAVE_RESTORE_LIST handling, factored out from here.
 888         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 889         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 890         (mips_builtin_opcodes): Add "restore" and "save" entries.
 891         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 892         (IAMR2): New macro.
 893         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 894
 895 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 896
 897         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 898         alias; do not mark SLTI instruction as an alias.
 899
 900 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 901
 902         * i386-dis.c (RM_0FAE_REG_5): Removed.
 903         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 904         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 905         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 906         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 907         PREFIX_MOD_3_0F01_REG_5_RM_0.
 908         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 909         PREFIX_MOD_3_0FAE_REG_5.
 910         (mod_table): Update MOD_0FAE_REG_5.
 911         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 912         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 913         * i386-tbl.h: Regenerated.
 914
 915 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 918         * i386-opc.tbl: Likewise.
 919         * i386-tbl.h: Regenerated.
 920
 921 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 924         and "jmp{&|}".
 925         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 926         prefix.
 927
 928 2017-06-19  Nick Clifton  <nickc@redhat.com>
 929
 930         PR binutils/21614
 931         * score-dis.c (score_opcodes): Add sentinel.
 932
 933 2017-06-16  Alan Modra  <amodra@gmail.com>
 934
 935         * rx-decode.c: Regenerate.
 936
 937 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 938
 939         PR binutils/21594
 940         * i386-dis.c (OP_E_register): Check valid bnd register.
 941         (OP_G): Likewise.
 942
 943 2017-06-15  Nick Clifton  <nickc@redhat.com>
 944
 945         PR binutils/21595
 946         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 947         range value.
 948
 949 2017-06-15  Nick Clifton  <nickc@redhat.com>
 950
 951         PR binutils/21588
 952         * rl78-decode.opc (OP_BUF_LEN): Define.
 953         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 954         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 955         array.
 956         * rl78-decode.c: Regenerate.
 957
 958 2017-06-15  Nick Clifton  <nickc@redhat.com>
 959
 960         PR binutils/21586
 961         * bfin-dis.c (gregs): Clip index to prevent overflow.
 962         (regs): Likewise.
 963         (regs_lo): Likewise.
 964         (regs_hi): Likewise.
 965
 966 2017-06-14  Nick Clifton  <nickc@redhat.com>
 967
 968         PR binutils/21576
 969         * score7-dis.c (score_opcodes): Add sentinel.
 970
 971 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 972
 973         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 974         * arm-dis.c: Likewise.
 975         * ia64-dis.c: Likewise.
 976         * mips-dis.c: Likewise.
 977         * spu-dis.c: Likewise.
 978         * disassemble.h (print_insn_aarch64): New declaration, moved from
 979         include/dis-asm.h.
 980         (print_insn_big_arm, print_insn_big_mips): Likewise.
 981         (print_insn_i386, print_insn_ia64): Likewise.
 982         (print_insn_little_arm, print_insn_little_mips): Likewise.
 983
 984 2017-06-14  Nick Clifton  <nickc@redhat.com>
 985
 986         PR binutils/21587
 987         * rx-decode.opc: Include libiberty.h
 988         (GET_SCALE): New macro - validates access to SCALE array.
 989         (GET_PSCALE): New macro - validates access to PSCALE array.
 990         (DIs, SIs, S2Is, rx_disp): Use new macros.
 991         * rx-decode.c: Regenerate.
 992
 993 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 994
 995         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 996
 997 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 998
 999         * arc-dis.c (enforced_isa_mask): Declare.
1000         (cpu_types): Likewise.
1001         (parse_cpu_option): New function.
1002         (parse_disassembler_options): Use it.
1003         (print_insn_arc): Use enforced_isa_mask.
1004         (print_arc_disassembler_options): Document new options.
1005
1006 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1007
1008         * alpha-dis.c: Include disassemble.h, don't include
1009         dis-asm.h.
1010         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1011         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1012         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1013         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1014         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1015         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1016         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1017         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1018         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1019         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1020         * moxie-dis.c, msp430-dis.c, mt-dis.c:
1021         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1022         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1023         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1024         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1025         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1026         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1027         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1028         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1029         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1030         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1031         * z80-dis.c, z8k-dis.c: Likewise.
1032         * disassemble.h: New file.
1033
1034 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1035
1036         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1037         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1038
1039 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1040
1041         * disassemble.c (disassembler): Add arguments a, big and mach.
1042         Use them.
1043
1044 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1045
1046         * i386-dis.c (NOTRACK_Fixup): New.
1047         (NOTRACK): Likewise.
1048         (NOTRACK_PREFIX): Likewise.
1049         (last_active_prefix): Likewise.
1050         (reg_table): Use NOTRACK on indirect call and jmp.
1051         (ckprefix): Set last_active_prefix.
1052         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1053         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1054         * i386-opc.h (NoTrackPrefixOk): New.
1055         (i386_opcode_modifier): Add notrackprefixok.
1056         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1057         Add notrack.
1058         * i386-tbl.h: Regenerated.
1059
1060 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1061
1062         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1063         (X_IMM2): Define.
1064         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1065         bfd_mach_sparc_v9m8.
1066         (print_insn_sparc): Handle new operand types.
1067         * sparc-opc.c (MASK_M8): Define.
1068         (v6): Add MASK_M8.
1069         (v6notlet): Likewise.
1070         (v7): Likewise.
1071         (v8): Likewise.
1072         (v9): Likewise.
1073         (v9a): Likewise.
1074         (v9b): Likewise.
1075         (v9c): Likewise.
1076         (v9d): Likewise.
1077         (v9e): Likewise.
1078         (v9v): Likewise.
1079         (v9m): Likewise.
1080         (v9andleon): Likewise.
1081         (m8): Define.
1082         (HWS_VM8): Define.
1083         (HWS2_VM8): Likewise.
1084         (sparc_opcode_archs): Add entry for "m8".
1085         (sparc_opcodes): Add OSA2017 and M8 instructions
1086         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1087         fpx{ll,ra,rl}64x,
1088         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1089         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1090         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1091         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1092         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1093         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1094         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1095         ASI_CORE_SELECT_COMMIT_NHT.
1096
1097 2017-05-18  Alan Modra  <amodra@gmail.com>
1098
1099         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1100         * aarch64-dis.c: Likewise.
1101         * aarch64-gen.c: Likewise.
1102         * aarch64-opc.c: Likewise.
1103
1104 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1105             Matthew Fortune  <matthew.fortune@imgtec.com>
1106
1107         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1108         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1109         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1110         (print_insn_arg) <OP_REG28>: Add handler.
1111         (validate_insn_args) <OP_REG28>: Handle.
1112         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1113         32-bit encoding and 9-bit immediates.
1114         (print_insn_mips16): Handle MIPS16 instructions that require
1115         32-bit encoding and MFC0/MTC0 operand decoding.
1116         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1117         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1118         (RD_C0, WR_C0, E2, E2MT): New macros.
1119         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1120         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1121         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1122         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1123         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1124         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1125         instructions, "swl", "swr", "sync" and its "sync_acquire",
1126         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1127         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1128         regular/extended entries for original MIPS16 ISA revision
1129         instructions whose extended forms are subdecoded in the MIPS16e2
1130         ISA revision: "li", "sll" and "srl".
1131
1132 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1133
1134         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1135         reference in CP0 move operand decoding.
1136
1137 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1138
1139         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1140         type to hexadecimal.
1141         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1142
1143 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1144
1145         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1146         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1147         "sync_rmb" and "sync_wmb" as aliases.
1148         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1149         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1150
1151 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1152
1153         * arc-dis.c (parse_option): Update quarkse_em option..
1154         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1155         QUARKSE1.
1156         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1157
1158 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1159
1160         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1161
1162 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1163
1164         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1165         register.
1166
1167 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1168
1169         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1170         and branches and not synthetic data instructions.
1171
1172 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1173
1174         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1175
1176 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1177
1178         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1179         * arc-opc.c (insert_r13el): New function.
1180         (R13_EL): Define.
1181         * arc-tbl.h: Add new enter/leave variants.
1182
1183 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1184
1185         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1186
1187 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1188
1189         * mips-dis.c (print_mips_disassembler_options): Add
1190         `no-aliases'.
1191
1192 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1193
1194         * mips16-opc.c (AL): New macro.
1195         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1196         of "ld" and "lw" as aliases.
1197
1198 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1199
1200         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1201         arguments.
1202
1203 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1204             Alan Modra  <amodra@gmail.com>
1205
1206         * ppc-opc.c (ELEV): Define.
1207         (vle_opcodes): Add se_rfgi and e_sc.
1208         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1209         for E200Z4.
1210
1211 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1212
1213         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1214
1215 2017-04-21  Nick Clifton  <nickc@redhat.com>
1216
1217         PR binutils/21380
1218         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1219         LD3R and LD4R.
1220
1221 2017-04-13  Alan Modra  <amodra@gmail.com>
1222
1223         * epiphany-desc.c: Regenerate.
1224         * fr30-desc.c: Regenerate.
1225         * frv-desc.c: Regenerate.
1226         * ip2k-desc.c: Regenerate.
1227         * iq2000-desc.c: Regenerate.
1228         * lm32-desc.c: Regenerate.
1229         * m32c-desc.c: Regenerate.
1230         * m32r-desc.c: Regenerate.
1231         * mep-desc.c: Regenerate.
1232         * mt-desc.c: Regenerate.
1233         * or1k-desc.c: Regenerate.
1234         * xc16x-desc.c: Regenerate.
1235         * xstormy16-desc.c: Regenerate.
1236
1237 2017-04-11  Alan Modra  <amodra@gmail.com>
1238
1239         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1240         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1241         PPC_OPCODE_TMR for e6500.
1242         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1243         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1244         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1245         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1246         (PPCHTM): Define as PPC_OPCODE_POWER8.
1247         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1248
1249 2017-04-10  Alan Modra  <amodra@gmail.com>
1250
1251         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1252         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1253         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1254         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1255
1256 2017-04-09  Pip Cet  <pipcet@gmail.com>
1257
1258         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1259         appropriate floating-point precision directly.
1260
1261 2017-04-07  Alan Modra  <amodra@gmail.com>
1262
1263         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1264         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1265         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1266         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1267         vector instructions with E6500 not PPCVEC2.
1268
1269 2017-04-06  Pip Cet  <pipcet@gmail.com>
1270
1271         * Makefile.am: Add wasm32-dis.c.
1272         * configure.ac: Add wasm32-dis.c to wasm32 target.
1273         * disassemble.c: Add wasm32 disassembler code.
1274         * wasm32-dis.c: New file.
1275         * Makefile.in: Regenerate.
1276         * configure: Regenerate.
1277         * po/POTFILES.in: Regenerate.
1278         * po/opcodes.pot: Regenerate.
1279
1280 2017-04-05  Pedro Alves  <palves@redhat.com>
1281
1282         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1283         * arm-dis.c (parse_arm_disassembler_options): Constify.
1284         * ppc-dis.c (powerpc_init_dialect): Constify local.
1285         * vax-dis.c (parse_disassembler_options): Constify.
1286
1287 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1288
1289         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1290         RISCV_GP_SYMBOL.
1291
1292 2017-03-30  Pip Cet  <pipcet@gmail.com>
1293
1294         * configure.ac: Add (empty) bfd_wasm32_arch target.
1295         * configure: Regenerate
1296         * po/opcodes.pot: Regenerate.
1297
1298 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1299
1300         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1301         OSA2015.
1302         * opcodes/sparc-opc.c (asi_table): New ASIs.
1303
1304 2017-03-29  Alan Modra  <amodra@gmail.com>
1305
1306         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1307         "raw" option.
1308         (lookup_powerpc): Don't special case -1 dialect.  Handle
1309         PPC_OPCODE_RAW.
1310         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1311         lookup_powerpc call, pass it on second.
1312
1313 2017-03-27  Alan Modra  <amodra@gmail.com>
1314
1315         PR 21303
1316         * ppc-dis.c (struct ppc_mopt): Comment.
1317         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1318
1319 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1320
1321         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1322         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1323         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1324         (insert_nps_misc_imm_offset): New function.
1325         (extract_nps_misc imm_offset): New function.
1326         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1327         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1328
1329 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1330
1331         * s390-mkopc.c (main): Remove vx2 check.
1332         * s390-opc.txt: Remove vx2 instruction flags.
1333
1334 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1335
1336         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1337         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1338         (insert_nps_imm_offset): New function.
1339         (extract_nps_imm_offset): New function.
1340         (insert_nps_imm_entry): New function.
1341         (extract_nps_imm_entry): New function.
1342
1343 2017-03-17  Alan Modra  <amodra@gmail.com>
1344
1345         PR 21248
1346         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1347         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1348         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1349
1350 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1351
1352         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1353         <c.andi>: Likewise.
1354         <c.addiw> Likewise.
1355
1356 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1357
1358         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1359
1360 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1361
1362         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1363         <srl> Likewise.
1364         <srai> Likewise.
1365         <sra> Likewise.
1366
1367 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1368
1369         * i386-gen.c (opcode_modifiers): Replace S with Load.
1370         * i386-opc.h (S): Removed.
1371         (Load): New.
1372         (i386_opcode_modifier): Replace s with load.
1373         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1374         and {evex}.  Replace S with Load.
1375         * i386-tbl.h: Regenerated.
1376
1377 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1378
1379         * i386-opc.tbl: Use CpuCET on rdsspq.
1380         * i386-tbl.h: Regenerated.
1381
1382 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1383
1384         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1385         <vsx>: Do not use PPC_OPCODE_VSX3;
1386
1387 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1388
1389         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1390
1391 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1392
1393         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1394         (MOD_0F1E_PREFIX_1): Likewise.
1395         (MOD_0F38F5_PREFIX_2): Likewise.
1396         (MOD_0F38F6_PREFIX_0): Likewise.
1397         (RM_0F1E_MOD_3_REG_7): Likewise.
1398         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1399         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1400         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1401         (PREFIX_0F1E): Likewise.
1402         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1403         (PREFIX_0F38F5): Likewise.
1404         (dis386_twobyte): Use PREFIX_0F1E.
1405         (reg_table): Add REG_0F1E_MOD_3.
1406         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1407         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1408         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1409         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1410         (three_byte_table): Use PREFIX_0F38F5.
1411         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1412         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1413         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1414         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1415         PREFIX_MOD_3_0F01_REG_5_RM_2.
1416         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1417         (cpu_flags): Add CpuCET.
1418         * i386-opc.h (CpuCET): New enum.
1419         (CpuUnused): Commented out.
1420         (i386_cpu_flags): Add cpucet.
1421         * i386-opc.tbl: Add Intel CET instructions.
1422         * i386-init.h: Regenerated.
1423         * i386-tbl.h: Likewise.
1424
1425 2017-03-06  Alan Modra  <amodra@gmail.com>
1426
1427         PR 21124
1428         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1429         (extract_raq, extract_ras, extract_rbx): New functions.
1430         (powerpc_operands): Use opposite corresponding insert function.
1431         (Q_MASK): Define.
1432         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1433         register restriction.
1434
1435 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1436
1437         * disassemble.c Include "safe-ctype.h".
1438         (disassemble_init_for_target): Handle s390 init.
1439         (remove_whitespace_and_extra_commas): New function.
1440         (disassembler_options_cmp): Likewise.
1441         * arm-dis.c: Include "libiberty.h".
1442         (NUM_ELEM): Delete.
1443         (regnames): Use long disassembler style names.
1444         Add force-thumb and no-force-thumb options.
1445         (NUM_ARM_REGNAMES): Rename from this...
1446         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1447         (get_arm_regname_num_options): Delete.
1448         (set_arm_regname_option): Likewise.
1449         (get_arm_regnames): Likewise.
1450         (parse_disassembler_options): Likewise.
1451         (parse_arm_disassembler_option): Rename from this...
1452         (parse_arm_disassembler_options): ...to this.  Make static.
1453         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1454         (print_insn): Use parse_arm_disassembler_options.
1455         (disassembler_options_arm): New function.
1456         (print_arm_disassembler_options): Handle updated regnames.
1457         * ppc-dis.c: Include "libiberty.h".
1458         (ppc_opts): Add "32" and "64" entries.
1459         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1460         (powerpc_init_dialect): Add break to switch statement.
1461         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1462         (disassembler_options_powerpc): New function.
1463         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1464         Remove printing of "32" and "64".
1465         * s390-dis.c: Include "libiberty.h".
1466         (init_flag): Remove unneeded variable.
1467         (struct s390_options_t): New structure type.
1468         (options): New structure.
1469         (init_disasm): Rename from this...
1470         (disassemble_init_s390): ...to this.  Add initializations for
1471         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1472         (print_insn_s390): Delete call to init_disasm.
1473         (disassembler_options_s390): New function.
1474         (print_s390_disassembler_options): Print using information from
1475         struct 'options'.
1476         * po/opcodes.pot: Regenerate.
1477
1478 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1479
1480         * i386-dis.c (PCMPESTR_Fixup): New.
1481         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1482         (prefix_table): Use PCMPESTR_Fixup.
1483         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1484         PCMPESTR_Fixup.
1485         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1486         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1487         Split 64-bit and non-64-bit variants.
1488         * opcodes/i386-tbl.h: Re-generate.
1489
1490 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1491
1492         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1493         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1494         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1495         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1496         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1497         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1498         (OP_SVE_V_HSD): New macros.
1499         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1500         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1501         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1502         (aarch64_opcode_table): Add new SVE instructions.
1503         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1504         for rotation operands.  Add new SVE operands.
1505         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1506         (ins_sve_quad_index): Likewise.
1507         (ins_imm_rotate): Split into...
1508         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1509         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1510         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1511         functions.
1512         (aarch64_ins_sve_addr_ri_s4): New function.
1513         (aarch64_ins_sve_quad_index): Likewise.
1514         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1515         * aarch64-asm-2.c: Regenerate.
1516         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1517         (ext_sve_quad_index): Likewise.
1518         (ext_imm_rotate): Split into...
1519         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1520         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1521         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1522         functions.
1523         (aarch64_ext_sve_addr_ri_s4): New function.
1524         (aarch64_ext_sve_quad_index): Likewise.
1525         (aarch64_ext_sve_index): Allow quad indices.
1526         (do_misc_decoding): Likewise.
1527         * aarch64-dis-2.c: Regenerate.
1528         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1529         aarch64_field_kinds.
1530         (OPD_F_OD_MASK): Widen by one bit.
1531         (OPD_F_NO_ZR): Bump accordingly.
1532         (get_operand_field_width): New function.
1533         * aarch64-opc.c (fields): Add new SVE fields.
1534         (operand_general_constraint_met_p): Handle new SVE operands.
1535         (aarch64_print_operand): Likewise.
1536         * aarch64-opc-2.c: Regenerate.
1537
1538 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1539
1540         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1541         (aarch64_feature_compnum): ...this.
1542         (SIMD_V8_3): Replace with...
1543         (COMPNUM): ...this.
1544         (CNUM_INSN): New macro.
1545         (aarch64_opcode_table): Use it for the complex number instructions.
1546
1547 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1548
1549         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1550
1551 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1552
1553         Add support for associating SPARC ASIs with an architecture level.
1554         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1555         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1556         decoding of SPARC ASIs.
1557
1558 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1559
1560         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1561         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1562
1563 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1564
1565         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1566         1 (instead of to itself). Correct typo.
1567
1568 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1569
1570         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1571         pseudoinstructions.
1572
1573 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1574
1575         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1576         (aarch64_sys_reg_supported_p): Handle them.
1577
1578 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1579
1580         * arc-opc.c (UIMM6_20R): Define.
1581         (SIMM12_20): Use above.
1582         (SIMM12_20R): Define.
1583         (SIMM3_5_S): Use above.
1584         (UIMM7_A32_11R_S): Define.
1585         (UIMM7_9_S): Use above.
1586         (UIMM3_13R_S): Define.
1587         (SIMM11_A32_7_S): Use above.
1588         (SIMM9_8R): Define.
1589         (UIMM10_A32_8_S): Use above.
1590         (UIMM8_8R_S): Define.
1591         (W6): Use above.
1592         (arc_relax_opcodes): Use all above defines.
1593
1594 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1595
1596         * arc-regs.h: Distinguish some of the registers different on
1597         ARC700 and HS38 cpus.
1598
1599 2017-02-14  Alan Modra  <amodra@gmail.com>
1600
1601         PR 21118
1602         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1603         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1604
1605 2017-02-11  Stafford Horne  <shorne@gmail.com>
1606             Alan Modra  <amodra@gmail.com>
1607
1608         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1609         Use insn_bytes_value and insn_int_value directly instead.  Don't
1610         free allocated memory until function exit.
1611
1612 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1613
1614         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1615
1616 2017-02-03  Nick Clifton  <nickc@redhat.com>
1617
1618         PR 21096
1619         * aarch64-opc.c (print_register_list): Ensure that the register
1620         list index will fir into the tb buffer.
1621         (print_register_offset_address): Likewise.
1622         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1623
1624 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1625
1626         PR 21056
1627         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1628         instructions when the previous fetch packet ends with a 32-bit
1629         instruction.
1630
1631 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1632
1633         * pru-opc.c: Remove vague reference to a future GDB port.
1634
1635 2017-01-20  Nick Clifton  <nickc@redhat.com>
1636
1637         * po/ga.po: Updated Irish translation.
1638
1639 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1640
1641         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1642
1643 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1644
1645         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1646         if FETCH_DATA returns 0.
1647         (m68k_scan_mask): Likewise.
1648         (print_insn_m68k): Update code to handle -1 return value.
1649
1650 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1651
1652         * m68k-dis.c (enum print_insn_arg_error): New.
1653         (NEXTBYTE): Replace -3 with
1654         PRINT_INSN_ARG_MEMORY_ERROR.
1655         (NEXTULONG): Likewise.
1656         (NEXTSINGLE): Likewise.
1657         (NEXTDOUBLE): Likewise.
1658         (NEXTDOUBLE): Likewise.
1659         (NEXTPACKED): Likewise.
1660         (FETCH_ARG): Likewise.
1661         (FETCH_DATA): Update comments.
1662         (print_insn_arg): Update comments. Replace magic numbers with
1663         enum.
1664         (match_insn_m68k): Likewise.
1665
1666 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1667
1668         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1669         * i386-dis-evex.h (evex_table): Updated.
1670         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1671         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1672         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1673         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1674         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1675         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1676         * i386-init.h: Regenerate.
1677         * i386-tbl.h: Ditto.
1678
1679 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1680
1681         * msp430-dis.c (msp430_singleoperand): Return -1 if
1682         msp430dis_opcode_signed returns false.
1683         (msp430_doubleoperand): Likewise.
1684         (msp430_branchinstr): Return -1 if
1685         msp430dis_opcode_unsigned returns false.
1686         (msp430x_calla_instr): Likewise.
1687         (print_insn_msp430): Likewise.
1688
1689 2017-01-05  Nick Clifton  <nickc@redhat.com>
1690
1691         PR 20946
1692         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1693         could not be matched.
1694         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1695         NULL.
1696
1697 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1698
1699         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1700         (aarch64_opcode_table): Use RCPC_INSN.
1701
1702 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1703
1704         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1705         extension.
1706         * riscv-opcodes/all-opcodes: Likewise.
1707
1708 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1709
1710         * riscv-dis.c (print_insn_args): Add fall through comment.
1711
1712 2017-01-03  Nick Clifton  <nickc@redhat.com>
1713
1714         * po/sr.po: New Serbian translation.
1715         * configure.ac (ALL_LINGUAS): Add sr.
1716         * configure: Regenerate.
1717
1718 2017-01-02  Alan Modra  <amodra@gmail.com>
1719
1720         * epiphany-desc.h: Regenerate.
1721         * epiphany-opc.h: Regenerate.
1722         * fr30-desc.h: Regenerate.
1723         * fr30-opc.h: Regenerate.
1724         * frv-desc.h: Regenerate.
1725         * frv-opc.h: Regenerate.
1726         * ip2k-desc.h: Regenerate.
1727         * ip2k-opc.h: Regenerate.
1728         * iq2000-desc.h: Regenerate.
1729         * iq2000-opc.h: Regenerate.
1730         * lm32-desc.h: Regenerate.
1731         * lm32-opc.h: Regenerate.
1732         * m32c-desc.h: Regenerate.
1733         * m32c-opc.h: Regenerate.
1734         * m32r-desc.h: Regenerate.
1735         * m32r-opc.h: Regenerate.
1736         * mep-desc.h: Regenerate.
1737         * mep-opc.h: Regenerate.
1738         * mt-desc.h: Regenerate.
1739         * mt-opc.h: Regenerate.
1740         * or1k-desc.h: Regenerate.
1741         * or1k-opc.h: Regenerate.
1742         * xc16x-desc.h: Regenerate.
1743         * xc16x-opc.h: Regenerate.
1744         * xstormy16-desc.h: Regenerate.
1745         * xstormy16-opc.h: Regenerate.
1746
1747 2017-01-02  Alan Modra  <amodra@gmail.com>
1748
1749         Update year range in copyright notice of all files.
1750
1751 For older changes see ChangeLog-2016
1752 \f
1753 Copyright (C) 2017 Free Software Foundation, Inc.
1754
1755 Copying and distribution of this file, with or without modification,
1756 are permitted in any medium without royalty provided the copyright
1757 notice and this notice are preserved.
1758
1759 Local Variables:
1760 mode: change-log
1761 left-margin: 8
1762 fill-column: 74
1763 version-control: never
1764 End: