opcodes/ChangeLog

   1 2013-02-27  Alan Modra  <amodra@gmail.com>
   2
   3         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
   4         * rl78-decode.c: Regenerate.
   5
   6 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
   7
   8         * rl78-decode.opc: Fix encoding of DIVWU insn.
   9         * rl78-decode.c: Regenerate.
  10
  11 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         PR gas/15159
  14         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
  15
  16         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
  17         (cpu_flags): Add CpuSMAP.
  18
  19         * i386-opc.h (CpuSMAP): New.
  20         (i386_cpu_flags): Add cpusmap.
  21
  22         * i386-opc.tbl: Add clac and stac.
  23
  24         * i386-init.h: Regenerated.
  25         * i386-tbl.h: Likewise.
  26
  27 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
  28
  29         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
  30         which also makes the disassembler output be in little
  31         endian like it should be.
  32
  33 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
  34
  35         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
  36         fields to NULL.
  37         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
  38
  39 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
  40
  41         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
  42         section disassembled.
  43
  44 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  45
  46         * arm-dis.c: Update strht pattern.
  47
  48 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
  49
  50         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
  51         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
  52         trunc.w.s macro for EE.
  53
  54 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
  55             Andrew Jenner <andrew@codesourcery.com>
  56
  57         Based on patches from Altera Corporation.
  58
  59         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
  60         nios2-opc.c.
  61         * Makefile.in: Regenerated.
  62         * configure.in: Add case for bfd_nios2_arch.
  63         * configure: Regenerated.
  64         * disassemble.c (ARCH_nios2): Define.
  65         (disassembler): Add case for bfd_arch_nios2.
  66         * nios2-dis.c: New file.
  67         * nios2-opc.c: New file.
  68
  69 2013-02-04  Alan Modra  <amodra@gmail.com>
  70
  71         * po/POTFILES.in: Regenerate.
  72         * rl78-decode.c: Regenerate.
  73         * rx-decode.c: Regenerate.
  74
  75 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
  76
  77         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
  78         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
  79         * aarch64-asm.c (convert_xtl_to_shll): New function.
  80         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  81         calling convert_xtl_to_shll.
  82         * aarch64-dis.c (convert_shll_to_xtl): New function.
  83         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  84         calling convert_shll_to_xtl.
  85         * aarch64-gen.c: Update copyright year.
  86         * aarch64-asm-2.c: Re-generate.
  87         * aarch64-dis-2.c: Re-generate.
  88         * aarch64-opc-2.c: Re-generate.
  89
  90 2013-01-24  Nick Clifton  <nickc@redhat.com>
  91
  92         * v850-dis.c: Add support for e3v5 architecture.
  93         * v850-opc.c: Likewise.
  94
  95 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  96
  97         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
  98         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
  99         * aarch64-opc.c (operand_general_constraint_met_p): For
 100         AARCH64_MOD_LSL, move the range check on the shift amount before the
 101         alignment check; change to call set_sft_amount_out_of_range_error
 102         instead of set_imm_out_of_range_error.
 103         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 104         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 105         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 106         SIMD_IMM_SFT.
 107
 108 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 111
 112         * i386-init.h: Regenerated.
 113         * i386-tbl.h: Likewise.
 114
 115 2013-01-15  Nick Clifton  <nickc@redhat.com>
 116
 117         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 118         values.
 119         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 120
 121 2013-01-14  Will Newton <will.newton@imgtec.com>
 122
 123         * metag-dis.c (REG_WIDTH): Increase to 64.
 124
 125 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 126
 127         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 128         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 129         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 130         (SH6): Update.
 131         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 132         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 133         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 134         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 135
 136 2013-01-10  Will Newton <will.newton@imgtec.com>
 137
 138         * Makefile.am: Add Meta.
 139         * configure.in: Add Meta.
 140         * disassemble.c: Add Meta support.
 141         * metag-dis.c: New file.
 142         * Makefile.in: Regenerate.
 143         * configure: Regenerate.
 144
 145 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 146
 147         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 148         (match_opcode): Rename to cr16_match_opcode.
 149
 150 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 151
 152         * mips-dis.c: Add names for CP0 registers of r5900.
 153         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 154         instructions sq and lq.
 155         Add support for MIPS r5900 CPU.
 156         Add support for 128 bit MMI (Multimedia Instructions).
 157         Add support for EE instructions (Emotion Engine).
 158         Disable unsupported floating point instructions (64 bit and
 159         undefined compare operations).
 160         Enable instructions of MIPS ISA IV which are supported by r5900.
 161         Disable 64 bit co processor instructions.
 162         Disable 64 bit multiplication and division instructions.
 163         Disable instructions for co-processor 2 and 3, because these are
 164         not supported (preparation for later VU0 support (Vector Unit)).
 165         Disable cvt.w.s because this behaves like trunc.w.s and the
 166         correct execution can't be ensured on r5900.
 167         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 168         will confuse less developers and compilers.
 169
 170 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 171
 172         * aarch64-opc.c (aarch64_print_operand): Change to print
 173         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 174         in comment.
 175         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 176         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 177         OP_MOV_IMM_WIDE.
 178
 179 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 180
 181         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 182         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 183
 184 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 185
 186         * i386-gen.c (process_copyright): Update copyright year to 2013.
 187
 188 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 189
 190         * cr16-dis.c (match_opcode,make_instruction): Remove static
 191         declaration.
 192         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 193         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 194
 195 For older changes see ChangeLog-2012
 196 \f
 197 Copyright (C) 2013 Free Software Foundation, Inc.
 198
 199 Copying and distribution of this file, with or without modification,
 200 are permitted in any medium without royalty provided the copyright
 201 notice and this notice are preserved.
 202
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