1 2015-06-04 Nick Clifton <nickc@redhat.com>
4 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
6 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
8 * arm-dis.c (arm_opcodes): Add "setpan".
9 (thumb_opcodes): Add "setpan".
11 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
13 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
16 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
18 * aarch64-tbl.h (aarch64_feature_rdma): New.
20 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
21 * aarch64-asm-2.c: Regenerate.
22 * aarch64-dis-2.c: Regenerate.
23 * aarch64-opc-2.c: Regenerate.
25 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
27 * aarch64-tbl.h (aarch64_feature_lor): New.
29 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
31 * aarch64-asm-2.c: Regenerate.
32 * aarch64-dis-2.c: Regenerate.
33 * aarch64-opc-2.c: Regenerate.
35 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
37 * aarch64-opc.c (F_ARCHEXT): New.
38 (aarch64_sys_regs): Add "pan".
39 (aarch64_sys_reg_supported_p): New.
40 (aarch64_pstatefields): Add "pan".
41 (aarch64_pstatefield_supported_p): New.
43 2015-06-01 Jan Beulich <jbeulich@suse.com>
45 * i386-tbl.h: Regenerate.
47 2015-06-01 Jan Beulich <jbeulich@suse.com>
49 * i386-dis.c (print_insn): Swap rounding mode specifier and
50 general purpose register in Intel mode.
52 2015-06-01 Jan Beulich <jbeulich@suse.com>
54 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
55 * i386-tbl.h: Regenerate.
57 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
59 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
60 * i386-init.h: Regenerated.
62 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
65 * i386-dis.c: Add comments for '@'.
66 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
67 (enum x86_64_isa): New.
69 (print_i386_disassembler_options): Add amd64 and intel64.
70 (print_insn): Handle amd64 and intel64.
72 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
73 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
74 * i386-opc.h (AMD64): New.
75 (CpuIntel64): Likewise.
76 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
77 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
78 Mark direct call/jmp without Disp16|Disp32 as Intel64.
79 * i386-init.h: Regenerated.
80 * i386-tbl.h: Likewise.
82 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
84 * ppc-opc.c (IH) New define.
85 (powerpc_opcodes) <wait>: Do not enable for POWER7.
86 <tlbie>: Add RS operand for POWER7.
87 <slbia>: Add IH operand for POWER6.
89 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
91 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
94 * i386-tbl.h: Regenerated.
96 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
98 * configure.ac: Support bfd_iamcu_arch.
99 * disassemble.c (disassembler): Support bfd_iamcu_arch.
100 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
101 CPU_IAMCU_COMPAT_FLAGS.
102 (cpu_flags): Add CpuIAMCU.
103 * i386-opc.h (CpuIAMCU): New.
104 (i386_cpu_flags): Add cpuiamcu.
105 * configure: Regenerated.
106 * i386-init.h: Likewise.
107 * i386-tbl.h: Likewise.
109 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
112 * i386-dis.c (X86_64_E8): New.
113 (X86_64_E9): Likewise.
114 Update comments on 'T', 'U', 'V'. Add comments for '^'.
115 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
116 (x86_64_table): Add X86_64_E8 and X86_64_E9.
117 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
119 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
122 2015-04-30 DJ Delorie <dj@redhat.com>
124 * disassemble.c (disassembler): Choose suitable disassembler based
126 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
127 it to decode mul/div insns.
128 * rl78-decode.c: Regenerate.
129 * rl78-dis.c (print_insn_rl78): Rename to...
130 (print_insn_rl78_common): ...this, take ISA parameter.
131 (print_insn_rl78): New.
132 (print_insn_rl78_g10): New.
133 (print_insn_rl78_g13): New.
134 (print_insn_rl78_g14): New.
135 (rl78_get_disassembler): New.
137 2015-04-29 Nick Clifton <nickc@redhat.com>
139 * po/fr.po: Updated French translation.
141 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
143 * ppc-opc.c (DCBT_EO): New define.
144 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
148 <waitrsv>: Do not enable for POWER7 and later.
149 <waitimpl>: Likewise.
150 <dcbt>: Default to the two operand form of the instruction for all
151 "old" cpus. For "new" cpus, use the operand ordering that matches
152 whether the cpu is server or embedded.
155 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
157 * s390-opc.c: New instruction type VV0UU2.
158 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
161 2015-04-23 Jan Beulich <jbeulich@suse.com>
163 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
164 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
165 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
166 (vfpclasspd, vfpclassps): Add %XZ.
168 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
170 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
171 (PREFIX_UD_REPZ): Likewise.
172 (PREFIX_UD_REPNZ): Likewise.
173 (PREFIX_UD_DATA): Likewise.
174 (PREFIX_UD_ADDR): Likewise.
175 (PREFIX_UD_LOCK): Likewise.
177 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
179 * i386-dis.c (prefix_requirement): Removed.
180 (print_insn): Don't set prefix_requirement. Check
181 dp->prefix_requirement instead of prefix_requirement.
183 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
186 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
187 (PREFIX_MOD_0_0FC7_REG_6): This.
188 (PREFIX_MOD_3_0FC7_REG_6): New.
189 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
190 (prefix_table): Replace PREFIX_0FC7_REG_6 with
191 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
192 PREFIX_MOD_3_0FC7_REG_7.
193 (mod_table): Replace PREFIX_0FC7_REG_6 with
194 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
195 PREFIX_MOD_3_0FC7_REG_7.
197 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
199 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
200 (PREFIX_MANDATORY_REPNZ): Likewise.
201 (PREFIX_MANDATORY_DATA): Likewise.
202 (PREFIX_MANDATORY_ADDR): Likewise.
203 (PREFIX_MANDATORY_LOCK): Likewise.
204 (PREFIX_MANDATORY): Likewise.
205 (PREFIX_UD_SHIFT): Set to 8
206 (PREFIX_UD_REPZ): Updated.
207 (PREFIX_UD_REPNZ): Likewise.
208 (PREFIX_UD_DATA): Likewise.
209 (PREFIX_UD_ADDR): Likewise.
210 (PREFIX_UD_LOCK): Likewise.
211 (PREFIX_IGNORED_SHIFT): New.
212 (PREFIX_IGNORED_REPZ): Likewise.
213 (PREFIX_IGNORED_REPNZ): Likewise.
214 (PREFIX_IGNORED_DATA): Likewise.
215 (PREFIX_IGNORED_ADDR): Likewise.
216 (PREFIX_IGNORED_LOCK): Likewise.
217 (PREFIX_OPCODE): Likewise.
218 (PREFIX_IGNORED): Likewise.
219 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
220 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
221 (three_byte_table): Likewise.
222 (mod_table): Likewise.
223 (mandatory_prefix): Renamed to ...
224 (prefix_requirement): This.
225 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
226 Update PREFIX_90 entry.
227 (get_valid_dis386): Check prefix_requirement to see if a prefix
229 (print_insn): Replace mandatory_prefix with prefix_requirement.
231 2015-04-15 Renlin Li <renlin.li@arm.com>
233 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
234 use it for ssat and ssat16.
235 (print_insn_thumb32): Add handle case for 'D' control code.
237 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
238 H.J. Lu <hongjiu.lu@intel.com>
240 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
241 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
242 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
243 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
244 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
245 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
246 Fill prefix_requirement field.
247 (struct dis386): Add prefix_requirement field.
248 (dis386): Fill prefix_requirement field.
249 (dis386_twobyte): Ditto.
250 (twobyte_has_mandatory_prefix_: Remove.
251 (reg_table): Fill prefix_requirement field.
252 (prefix_table): Ditto.
253 (x86_64_table): Ditto.
254 (three_byte_table): Ditto.
257 (vex_len_table): Ditto.
258 (vex_w_table): Ditto.
261 (print_insn): Use prefix_requirement.
262 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
263 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
266 2015-03-30 Mike Frysinger <vapier@gentoo.org>
268 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
270 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
272 * Makefile.in: Regenerated.
274 2015-03-25 Anton Blanchard <anton@samba.org>
276 * ppc-dis.c (disassemble_init_powerpc): Only initialise
277 powerpc_opcd_indices and vle_opcd_indices once.
279 2015-03-25 Anton Blanchard <anton@samba.org>
281 * ppc-opc.c (powerpc_opcodes): Add slbfee.
283 2015-03-24 Terry Guo <terry.guo@arm.com>
285 * arm-dis.c (opcode32): Updated to use new arm feature struct.
286 (opcode16): Likewise.
287 (coprocessor_opcodes): Replace bit with feature struct.
288 (neon_opcodes): Likewise.
289 (arm_opcodes): Likewise.
290 (thumb_opcodes): Likewise.
291 (thumb32_opcodes): Likewise.
292 (print_insn_coprocessor): Likewise.
293 (print_insn_arm): Likewise.
294 (select_arm_features): Follow new feature struct.
296 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
298 * i386-dis.c (rm_table): Add clzero.
299 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
300 Add CPU_CLZERO_FLAGS.
301 (cpu_flags): Add CpuCLZERO.
302 * i386-opc.h: Add CpuCLZERO.
303 * i386-opc.tbl: Add clzero.
304 * i386-init.h: Re-generated.
305 * i386-tbl.h: Re-generated.
307 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
309 * mips-opc.c (decode_mips_operand): Fix constraint issues
310 with u and y operands.
312 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
314 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
316 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
318 * s390-opc.c: Add new IBM z13 instructions.
319 * s390-opc.txt: Likewise.
321 2015-03-10 Renlin Li <renlin.li@arm.com>
323 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
324 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
326 * aarch64-asm-2.c: Regenerate.
327 * aarch64-dis-2.c: Likewise.
328 * aarch64-opc-2.c: Likewise.
330 2015-03-03 Jiong Wang <jiong.wang@arm.com>
332 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
334 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
336 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
338 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
339 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
341 2015-02-23 Vinay <Vinay.G@kpit.com>
343 * rl78-decode.opc (MOV): Added space between two operands for
344 'mov' instruction in index addressing mode.
345 * rl78-decode.c: Regenerate.
347 2015-02-19 Pedro Alves <palves@redhat.com>
349 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
351 2015-02-10 Pedro Alves <palves@redhat.com>
352 Tom Tromey <tromey@redhat.com>
354 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
355 microblaze_and, microblaze_xor.
356 * microblaze-opc.h (opcodes): Adjust.
358 2015-01-28 James Bowman <james.bowman@ftdichip.com>
360 * Makefile.am: Add FT32 files.
361 * configure.ac: Handle FT32.
362 * disassemble.c (disassembler): Call print_insn_ft32.
363 * ft32-dis.c: New file.
364 * ft32-opc.c: New file.
365 * Makefile.in: Regenerate.
366 * configure: Regenerate.
367 * po/POTFILES.in: Regenerate.
369 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
371 * nds32-asm.c (keyword_sr): Add new system registers.
373 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
375 * s390-dis.c (s390_extract_operand): Support vector register
377 (s390_print_insn_with_opcode): Support new operands types and add
378 new handling of optional operands.
379 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
380 and include opcode/s390.h instead.
381 (struct op_struct): New field `flags'.
382 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
383 (dumpTable): Dump flags.
384 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
386 * s390-opc.c: Add new operands types, instruction formats, and
388 (s390_opformats): Add new formats for .insn.
389 * s390-opc.txt: Add new instructions.
391 2015-01-01 Alan Modra <amodra@gmail.com>
393 Update year range in copyright notice of all files.
395 For older changes see ChangeLog-2014
397 Copyright (C) 2015 Free Software Foundation, Inc.
399 Copying and distribution of this file, with or without modification,
400 are permitted in any medium without royalty provided the copyright
401 notice and this notice are preserved.
407 version-control: never