1 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
3 * nds32-asm.c (operand_fields): Remove the unused fields.
4 (nds32_opcodes): Remove the unused instructions.
5 * nds32-dis.c (nds32_ex9_info): Removed.
6 (nds32_parse_opcode): Updated.
7 (print_insn_nds32): Likewise.
8 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
9 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
10 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
11 build_opcode_hash_table): New functions.
12 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
13 nds32_opcode_table): New.
14 (hw_ktabs): Declare it to a pointer rather than an array.
15 (build_hash_table): Removed.
16 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
17 SYN_ROPT and upadte HW_GPR and HW_INT.
18 * nds32-dis.c (keywords): Remove const.
19 (match_field): New function.
20 (nds32_parse_opcode): Updated.
21 * disassemble.c (disassemble_init_for_target):
22 Add disassemble_init_nds32.
23 * nds32-dis.c (eum map_type): New.
24 (nds32_private_data): Likewise.
25 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
26 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
27 (print_insn_nds32): Updated.
28 * nds32-asm.c (parse_aext_reg): Add new parameter.
29 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
32 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
33 (operand_fields): Add new fields.
34 (nds32_opcodes): Add new instructions.
35 (keyword_aridxi_mx): New keyword.
36 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
38 (ALU2_1, ALU2_2, ALU2_3): New macros.
39 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
41 2018-09-17 Kito Cheng <kito@andestech.com>
43 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
45 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
48 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
49 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
50 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
51 (EVEX_LEN_0F7E_P_1): Likewise.
52 (EVEX_LEN_0F7E_P_2): Likewise.
53 (EVEX_LEN_0FD6_P_2): Likewise.
54 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
55 (EVEX_LEN_TABLE): Likewise.
56 (EVEX_LEN_0F6E_P_2): New enum.
57 (EVEX_LEN_0F7E_P_1): Likewise.
58 (EVEX_LEN_0F7E_P_2): Likewise.
59 (EVEX_LEN_0FD6_P_2): Likewise.
60 (evex_len_table): New.
61 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
62 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
63 * i386-tbl.h: Regenerated.
65 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
68 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
69 VEX_LEN_0F7E_P_2 entries.
70 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
71 * i386-tbl.h: Regenerated.
73 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
75 * i386-dis.c (VZERO_Fixup): Removed.
77 (VEX_LEN_0F10_P_1): Likewise.
78 (VEX_LEN_0F10_P_3): Likewise.
79 (VEX_LEN_0F11_P_1): Likewise.
80 (VEX_LEN_0F11_P_3): Likewise.
81 (VEX_LEN_0F2E_P_0): Likewise.
82 (VEX_LEN_0F2E_P_2): Likewise.
83 (VEX_LEN_0F2F_P_0): Likewise.
84 (VEX_LEN_0F2F_P_2): Likewise.
85 (VEX_LEN_0F51_P_1): Likewise.
86 (VEX_LEN_0F51_P_3): Likewise.
87 (VEX_LEN_0F52_P_1): Likewise.
88 (VEX_LEN_0F53_P_1): Likewise.
89 (VEX_LEN_0F58_P_1): Likewise.
90 (VEX_LEN_0F58_P_3): Likewise.
91 (VEX_LEN_0F59_P_1): Likewise.
92 (VEX_LEN_0F59_P_3): Likewise.
93 (VEX_LEN_0F5A_P_1): Likewise.
94 (VEX_LEN_0F5A_P_3): Likewise.
95 (VEX_LEN_0F5C_P_1): Likewise.
96 (VEX_LEN_0F5C_P_3): Likewise.
97 (VEX_LEN_0F5D_P_1): Likewise.
98 (VEX_LEN_0F5D_P_3): Likewise.
99 (VEX_LEN_0F5E_P_1): Likewise.
100 (VEX_LEN_0F5E_P_3): Likewise.
101 (VEX_LEN_0F5F_P_1): Likewise.
102 (VEX_LEN_0F5F_P_3): Likewise.
103 (VEX_LEN_0FC2_P_1): Likewise.
104 (VEX_LEN_0FC2_P_3): Likewise.
105 (VEX_LEN_0F3A0A_P_2): Likewise.
106 (VEX_LEN_0F3A0B_P_2): Likewise.
107 (VEX_W_0F10_P_0): Likewise.
108 (VEX_W_0F10_P_1): Likewise.
109 (VEX_W_0F10_P_2): Likewise.
110 (VEX_W_0F10_P_3): Likewise.
111 (VEX_W_0F11_P_0): Likewise.
112 (VEX_W_0F11_P_1): Likewise.
113 (VEX_W_0F11_P_2): Likewise.
114 (VEX_W_0F11_P_3): Likewise.
115 (VEX_W_0F12_P_0_M_0): Likewise.
116 (VEX_W_0F12_P_0_M_1): Likewise.
117 (VEX_W_0F12_P_1): Likewise.
118 (VEX_W_0F12_P_2): Likewise.
119 (VEX_W_0F12_P_3): Likewise.
120 (VEX_W_0F13_M_0): Likewise.
121 (VEX_W_0F14): Likewise.
122 (VEX_W_0F15): Likewise.
123 (VEX_W_0F16_P_0_M_0): Likewise.
124 (VEX_W_0F16_P_0_M_1): Likewise.
125 (VEX_W_0F16_P_1): Likewise.
126 (VEX_W_0F16_P_2): Likewise.
127 (VEX_W_0F17_M_0): Likewise.
128 (VEX_W_0F28): Likewise.
129 (VEX_W_0F29): Likewise.
130 (VEX_W_0F2B_M_0): Likewise.
131 (VEX_W_0F2E_P_0): Likewise.
132 (VEX_W_0F2E_P_2): Likewise.
133 (VEX_W_0F2F_P_0): Likewise.
134 (VEX_W_0F2F_P_2): Likewise.
135 (VEX_W_0F50_M_0): Likewise.
136 (VEX_W_0F51_P_0): Likewise.
137 (VEX_W_0F51_P_1): Likewise.
138 (VEX_W_0F51_P_2): Likewise.
139 (VEX_W_0F51_P_3): Likewise.
140 (VEX_W_0F52_P_0): Likewise.
141 (VEX_W_0F52_P_1): Likewise.
142 (VEX_W_0F53_P_0): Likewise.
143 (VEX_W_0F53_P_1): Likewise.
144 (VEX_W_0F58_P_0): Likewise.
145 (VEX_W_0F58_P_1): Likewise.
146 (VEX_W_0F58_P_2): Likewise.
147 (VEX_W_0F58_P_3): Likewise.
148 (VEX_W_0F59_P_0): Likewise.
149 (VEX_W_0F59_P_1): Likewise.
150 (VEX_W_0F59_P_2): Likewise.
151 (VEX_W_0F59_P_3): Likewise.
152 (VEX_W_0F5A_P_0): Likewise.
153 (VEX_W_0F5A_P_1): Likewise.
154 (VEX_W_0F5A_P_3): Likewise.
155 (VEX_W_0F5B_P_0): Likewise.
156 (VEX_W_0F5B_P_1): Likewise.
157 (VEX_W_0F5B_P_2): Likewise.
158 (VEX_W_0F5C_P_0): Likewise.
159 (VEX_W_0F5C_P_1): Likewise.
160 (VEX_W_0F5C_P_2): Likewise.
161 (VEX_W_0F5C_P_3): Likewise.
162 (VEX_W_0F5D_P_0): Likewise.
163 (VEX_W_0F5D_P_1): Likewise.
164 (VEX_W_0F5D_P_2): Likewise.
165 (VEX_W_0F5D_P_3): Likewise.
166 (VEX_W_0F5E_P_0): Likewise.
167 (VEX_W_0F5E_P_1): Likewise.
168 (VEX_W_0F5E_P_2): Likewise.
169 (VEX_W_0F5E_P_3): Likewise.
170 (VEX_W_0F5F_P_0): Likewise.
171 (VEX_W_0F5F_P_1): Likewise.
172 (VEX_W_0F5F_P_2): Likewise.
173 (VEX_W_0F5F_P_3): Likewise.
174 (VEX_W_0F60_P_2): Likewise.
175 (VEX_W_0F61_P_2): Likewise.
176 (VEX_W_0F62_P_2): Likewise.
177 (VEX_W_0F63_P_2): Likewise.
178 (VEX_W_0F64_P_2): Likewise.
179 (VEX_W_0F65_P_2): Likewise.
180 (VEX_W_0F66_P_2): Likewise.
181 (VEX_W_0F67_P_2): Likewise.
182 (VEX_W_0F68_P_2): Likewise.
183 (VEX_W_0F69_P_2): Likewise.
184 (VEX_W_0F6A_P_2): Likewise.
185 (VEX_W_0F6B_P_2): Likewise.
186 (VEX_W_0F6C_P_2): Likewise.
187 (VEX_W_0F6D_P_2): Likewise.
188 (VEX_W_0F6F_P_1): Likewise.
189 (VEX_W_0F6F_P_2): Likewise.
190 (VEX_W_0F70_P_1): Likewise.
191 (VEX_W_0F70_P_2): Likewise.
192 (VEX_W_0F70_P_3): Likewise.
193 (VEX_W_0F71_R_2_P_2): Likewise.
194 (VEX_W_0F71_R_4_P_2): Likewise.
195 (VEX_W_0F71_R_6_P_2): Likewise.
196 (VEX_W_0F72_R_2_P_2): Likewise.
197 (VEX_W_0F72_R_4_P_2): Likewise.
198 (VEX_W_0F72_R_6_P_2): Likewise.
199 (VEX_W_0F73_R_2_P_2): Likewise.
200 (VEX_W_0F73_R_3_P_2): Likewise.
201 (VEX_W_0F73_R_6_P_2): Likewise.
202 (VEX_W_0F73_R_7_P_2): Likewise.
203 (VEX_W_0F74_P_2): Likewise.
204 (VEX_W_0F75_P_2): Likewise.
205 (VEX_W_0F76_P_2): Likewise.
206 (VEX_W_0F77_P_0): Likewise.
207 (VEX_W_0F7C_P_2): Likewise.
208 (VEX_W_0F7C_P_3): Likewise.
209 (VEX_W_0F7D_P_2): Likewise.
210 (VEX_W_0F7D_P_3): Likewise.
211 (VEX_W_0F7E_P_1): Likewise.
212 (VEX_W_0F7F_P_1): Likewise.
213 (VEX_W_0F7F_P_2): Likewise.
214 (VEX_W_0FAE_R_2_M_0): Likewise.
215 (VEX_W_0FAE_R_3_M_0): Likewise.
216 (VEX_W_0FC2_P_0): Likewise.
217 (VEX_W_0FC2_P_1): Likewise.
218 (VEX_W_0FC2_P_2): Likewise.
219 (VEX_W_0FC2_P_3): Likewise.
220 (VEX_W_0FD0_P_2): Likewise.
221 (VEX_W_0FD0_P_3): Likewise.
222 (VEX_W_0FD1_P_2): Likewise.
223 (VEX_W_0FD2_P_2): Likewise.
224 (VEX_W_0FD3_P_2): Likewise.
225 (VEX_W_0FD4_P_2): Likewise.
226 (VEX_W_0FD5_P_2): Likewise.
227 (VEX_W_0FD6_P_2): Likewise.
228 (VEX_W_0FD7_P_2_M_1): Likewise.
229 (VEX_W_0FD8_P_2): Likewise.
230 (VEX_W_0FD9_P_2): Likewise.
231 (VEX_W_0FDA_P_2): Likewise.
232 (VEX_W_0FDB_P_2): Likewise.
233 (VEX_W_0FDC_P_2): Likewise.
234 (VEX_W_0FDD_P_2): Likewise.
235 (VEX_W_0FDE_P_2): Likewise.
236 (VEX_W_0FDF_P_2): Likewise.
237 (VEX_W_0FE0_P_2): Likewise.
238 (VEX_W_0FE1_P_2): Likewise.
239 (VEX_W_0FE2_P_2): Likewise.
240 (VEX_W_0FE3_P_2): Likewise.
241 (VEX_W_0FE4_P_2): Likewise.
242 (VEX_W_0FE5_P_2): Likewise.
243 (VEX_W_0FE6_P_1): Likewise.
244 (VEX_W_0FE6_P_2): Likewise.
245 (VEX_W_0FE6_P_3): Likewise.
246 (VEX_W_0FE7_P_2_M_0): Likewise.
247 (VEX_W_0FE8_P_2): Likewise.
248 (VEX_W_0FE9_P_2): Likewise.
249 (VEX_W_0FEA_P_2): Likewise.
250 (VEX_W_0FEB_P_2): Likewise.
251 (VEX_W_0FEC_P_2): Likewise.
252 (VEX_W_0FED_P_2): Likewise.
253 (VEX_W_0FEE_P_2): Likewise.
254 (VEX_W_0FEF_P_2): Likewise.
255 (VEX_W_0FF0_P_3_M_0): Likewise.
256 (VEX_W_0FF1_P_2): Likewise.
257 (VEX_W_0FF2_P_2): Likewise.
258 (VEX_W_0FF3_P_2): Likewise.
259 (VEX_W_0FF4_P_2): Likewise.
260 (VEX_W_0FF5_P_2): Likewise.
261 (VEX_W_0FF6_P_2): Likewise.
262 (VEX_W_0FF7_P_2): Likewise.
263 (VEX_W_0FF8_P_2): Likewise.
264 (VEX_W_0FF9_P_2): Likewise.
265 (VEX_W_0FFA_P_2): Likewise.
266 (VEX_W_0FFB_P_2): Likewise.
267 (VEX_W_0FFC_P_2): Likewise.
268 (VEX_W_0FFD_P_2): Likewise.
269 (VEX_W_0FFE_P_2): Likewise.
270 (VEX_W_0F3800_P_2): Likewise.
271 (VEX_W_0F3801_P_2): Likewise.
272 (VEX_W_0F3802_P_2): Likewise.
273 (VEX_W_0F3803_P_2): Likewise.
274 (VEX_W_0F3804_P_2): Likewise.
275 (VEX_W_0F3805_P_2): Likewise.
276 (VEX_W_0F3806_P_2): Likewise.
277 (VEX_W_0F3807_P_2): Likewise.
278 (VEX_W_0F3808_P_2): Likewise.
279 (VEX_W_0F3809_P_2): Likewise.
280 (VEX_W_0F380A_P_2): Likewise.
281 (VEX_W_0F380B_P_2): Likewise.
282 (VEX_W_0F3817_P_2): Likewise.
283 (VEX_W_0F381C_P_2): Likewise.
284 (VEX_W_0F381D_P_2): Likewise.
285 (VEX_W_0F381E_P_2): Likewise.
286 (VEX_W_0F3820_P_2): Likewise.
287 (VEX_W_0F3821_P_2): Likewise.
288 (VEX_W_0F3822_P_2): Likewise.
289 (VEX_W_0F3823_P_2): Likewise.
290 (VEX_W_0F3824_P_2): Likewise.
291 (VEX_W_0F3825_P_2): Likewise.
292 (VEX_W_0F3828_P_2): Likewise.
293 (VEX_W_0F3829_P_2): Likewise.
294 (VEX_W_0F382A_P_2_M_0): Likewise.
295 (VEX_W_0F382B_P_2): Likewise.
296 (VEX_W_0F3830_P_2): Likewise.
297 (VEX_W_0F3831_P_2): Likewise.
298 (VEX_W_0F3832_P_2): Likewise.
299 (VEX_W_0F3833_P_2): Likewise.
300 (VEX_W_0F3834_P_2): Likewise.
301 (VEX_W_0F3835_P_2): Likewise.
302 (VEX_W_0F3837_P_2): Likewise.
303 (VEX_W_0F3838_P_2): Likewise.
304 (VEX_W_0F3839_P_2): Likewise.
305 (VEX_W_0F383A_P_2): Likewise.
306 (VEX_W_0F383B_P_2): Likewise.
307 (VEX_W_0F383C_P_2): Likewise.
308 (VEX_W_0F383D_P_2): Likewise.
309 (VEX_W_0F383E_P_2): Likewise.
310 (VEX_W_0F383F_P_2): Likewise.
311 (VEX_W_0F3840_P_2): Likewise.
312 (VEX_W_0F3841_P_2): Likewise.
313 (VEX_W_0F38DB_P_2): Likewise.
314 (VEX_W_0F3A08_P_2): Likewise.
315 (VEX_W_0F3A09_P_2): Likewise.
316 (VEX_W_0F3A0A_P_2): Likewise.
317 (VEX_W_0F3A0B_P_2): Likewise.
318 (VEX_W_0F3A0C_P_2): Likewise.
319 (VEX_W_0F3A0D_P_2): Likewise.
320 (VEX_W_0F3A0E_P_2): Likewise.
321 (VEX_W_0F3A0F_P_2): Likewise.
322 (VEX_W_0F3A21_P_2): Likewise.
323 (VEX_W_0F3A40_P_2): Likewise.
324 (VEX_W_0F3A41_P_2): Likewise.
325 (VEX_W_0F3A42_P_2): Likewise.
326 (VEX_W_0F3A62_P_2): Likewise.
327 (VEX_W_0F3A63_P_2): Likewise.
328 (VEX_W_0F3ADF_P_2): Likewise.
329 (VEX_LEN_0F77_P_0): New.
330 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
331 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
332 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
333 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
334 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
335 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
336 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
337 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
338 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
339 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
340 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
341 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
342 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
343 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
344 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
345 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
346 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
347 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
348 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
349 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
350 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
351 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
352 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
353 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
354 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
355 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
356 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
357 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
358 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
359 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
360 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
361 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
362 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
363 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
364 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
365 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
366 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
367 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
368 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
369 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
370 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
371 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
372 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
373 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
374 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
375 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
376 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
377 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
378 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
379 (vex_table): Update VEX 0F28 and 0F29 entries.
380 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
381 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
382 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
383 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
384 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
385 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
386 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
387 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
388 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
389 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
390 VEX_LEN_0F3A0B_P_2 entries.
391 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
392 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
393 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
394 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
395 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
396 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
397 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
398 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
399 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
400 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
401 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
402 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
403 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
404 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
405 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
406 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
407 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
408 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
409 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
410 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
411 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
412 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
413 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
414 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
415 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
416 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
417 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
418 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
419 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
420 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
421 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
422 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
423 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
424 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
425 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
426 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
427 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
428 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
429 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
430 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
431 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
432 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
433 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
434 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
435 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
436 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
437 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
438 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
439 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
440 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
441 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
442 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
443 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
444 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
445 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
446 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
447 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
448 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
449 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
450 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
451 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
452 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
453 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
454 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
455 VEX_W_0F3ADF_P_2 entries.
456 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
457 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
458 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
460 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
462 * i386-opc.tbl (VexWIG): New.
463 Replace VexW=3 with VexWIG.
465 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
467 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
468 * i386-tbl.h: Regenerated.
470 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
473 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
474 VEX_LEN_0FD6_P_2 entries.
475 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
476 * i386-tbl.h: Regenerated.
478 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
481 * i386-opc.h (VEXWIG): New.
482 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
483 * i386-tbl.h: Regenerated.
485 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
488 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
489 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
490 * i386-dis.c (EXxEVexR64): New.
491 (evex_rounding_64_mode): Likewise.
492 (OP_Rounding): Handle evex_rounding_64_mode.
494 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
497 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
498 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
499 * i386-dis.c (Edqa): New.
500 (dqa_mode): Likewise.
501 (intel_operand_size): Handle dqa_mode as m_mode.
502 (OP_E_register): Handle dqa_mode as dq_mode.
503 (OP_E_memory): Set shift for dqa_mode based on address_mode.
505 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
507 * i386-dis.c (OP_E_memory): Reformat.
509 2018-09-14 Jan Beulich <jbeulich@suse.com>
511 * i386-opc.tbl (crc32): Fold byte and word forms.
512 * i386-tbl.h: Re-generate.
514 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
516 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
517 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
518 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
519 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
520 * i386-tbl.h: Regenerated.
522 2018-09-13 Jan Beulich <jbeulich@suse.com>
524 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
526 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
527 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
528 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
529 * i386-tbl.h: Re-generate.
531 2018-09-13 Jan Beulich <jbeulich@suse.com>
533 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
535 * i386-tbl.h: Re-generate.
537 2018-09-13 Jan Beulich <jbeulich@suse.com>
539 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
541 * i386-tbl.h: Re-generate.
543 2018-09-13 Jan Beulich <jbeulich@suse.com>
545 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
547 * i386-tbl.h: Re-generate.
549 2018-09-13 Jan Beulich <jbeulich@suse.com>
551 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
553 * i386-tbl.h: Re-generate.
555 2018-09-13 Jan Beulich <jbeulich@suse.com>
557 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
559 * i386-tbl.h: Re-generate.
561 2018-09-13 Jan Beulich <jbeulich@suse.com>
563 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
565 * i386-tbl.h: Re-generate.
567 2018-09-13 Jan Beulich <jbeulich@suse.com>
569 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
570 * i386-tbl.h: Re-generate.
572 2018-09-13 Jan Beulich <jbeulich@suse.com>
574 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
575 * i386-tbl.h: Re-generate.
577 2018-09-13 Jan Beulich <jbeulich@suse.com>
579 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
581 * i386-tbl.h: Re-generate.
583 2018-09-13 Jan Beulich <jbeulich@suse.com>
585 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
587 * i386-tbl.h: Re-generate.
589 2018-09-13 Jan Beulich <jbeulich@suse.com>
591 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
592 * i386-tbl.h: Re-generate.
594 2018-09-13 Jan Beulich <jbeulich@suse.com>
596 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
597 * i386-tbl.h: Re-generate.
599 2018-09-13 Jan Beulich <jbeulich@suse.com>
601 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
602 * i386-tbl.h: Re-generate.
604 2018-09-13 Jan Beulich <jbeulich@suse.com>
606 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
608 * i386-tbl.h: Re-generate.
610 2018-09-13 Jan Beulich <jbeulich@suse.com>
612 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
614 * i386-tbl.h: Re-generate.
616 2018-09-13 Jan Beulich <jbeulich@suse.com>
618 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
620 * i386-tbl.h: Re-generate.
622 2018-09-13 Jan Beulich <jbeulich@suse.com>
624 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
625 * i386-tbl.h: Re-generate.
627 2018-09-13 Jan Beulich <jbeulich@suse.com>
629 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
630 * i386-tbl.h: Re-generate.
632 2018-09-13 Jan Beulich <jbeulich@suse.com>
634 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
635 * i386-tbl.h: Re-generate.
637 2018-09-13 Jan Beulich <jbeulich@suse.com>
639 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
640 (vpbroadcastw, rdpid): Drop NoRex64.
641 * i386-tbl.h: Re-generate.
643 2018-09-13 Jan Beulich <jbeulich@suse.com>
645 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
646 store templates, adding D.
647 * i386-tbl.h: Re-generate.
649 2018-09-13 Jan Beulich <jbeulich@suse.com>
651 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
652 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
653 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
654 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
655 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
656 Fold load and store templates where possible, adding D. Drop
657 IgnoreSize where it was pointlessly present. Drop redundant
659 * i386-tbl.h: Re-generate.
661 2018-09-13 Jan Beulich <jbeulich@suse.com>
663 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
664 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
665 (intel_operand_size): Handle v_bndmk_mode.
666 (OP_E_memory): Likewise. Produce (bad) when also riprel.
668 2018-09-08 John Darrington <john@darrington.wattle.id.au>
670 * disassemble.c (ARCH_s12z): Define if ARCH_all.
672 2018-08-31 Kito Cheng <kito@andestech.com>
674 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
675 compressed floating point instructions.
677 2018-08-30 Kito Cheng <kito@andestech.com>
679 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
680 riscv_opcode.xlen_requirement.
681 * riscv-opc.c (riscv_opcodes): Update for struct change.
683 2018-08-29 Martin Aberg <maberg@gaisler.com>
685 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
686 psr (PWRPSR) instruction.
688 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
690 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
692 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
694 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
696 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
698 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
699 loongson3a as an alias of gs464 for compatibility.
700 * mips-opc.c (mips_opcodes): Change Comments.
702 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
704 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
706 (print_mips_disassembler_options): Document -M loongson-ext.
707 * mips-opc.c (LEXT2): New macro.
708 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
710 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
712 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
714 (parse_mips_ase_option): Handle -M loongson-ext option.
715 (print_mips_disassembler_options): Document -M loongson-ext.
716 * mips-opc.c (IL3A): Delete.
717 * mips-opc.c (LEXT): New macro.
718 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
721 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
723 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
725 (parse_mips_ase_option): Handle -M loongson-cam option.
726 (print_mips_disassembler_options): Document -M loongson-cam.
727 * mips-opc.c (LCAM): New macro.
728 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
731 2018-08-21 Alan Modra <amodra@gmail.com>
733 * ppc-dis.c (operand_value_powerpc): Init "invalid".
734 (skip_optional_operands): Count optional operands, and update
735 ppc_optional_operand_value call.
736 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
737 (extract_vlensi): Likewise.
738 (extract_fxm): Return default value for missing optional operand.
739 (extract_ls, extract_raq, extract_tbr): Likewise.
740 (insert_sxl, extract_sxl): New functions.
741 (insert_esync, extract_esync): Remove Power9 handling and simplify.
742 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
743 flag and extra entry.
744 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
747 2018-08-20 Alan Modra <amodra@gmail.com>
749 * sh-opc.h (MASK): Simplify.
751 2018-08-18 John Darrington <john@darrington.wattle.id.au>
753 * s12z-dis.c (bm_decode): Deal with cases where the mode is
754 BM_RESERVED0 or BM_RESERVED1
755 (bm_rel_decode, bm_n_bytes): Ditto.
757 2018-08-18 John Darrington <john@darrington.wattle.id.au>
761 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
763 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
764 address with the addr32 prefix and without base nor index
767 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
769 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
770 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
771 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
772 (cpu_flags): Add CpuCMOV and CpuFXSR.
773 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
774 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
775 * i386-init.h: Regenerated.
776 * i386-tbl.h: Likewise.
778 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
780 * arc-regs.h: Update auxiliary registers.
782 2018-08-06 Jan Beulich <jbeulich@suse.com>
784 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
785 (RegIP, RegIZ): Define.
786 * i386-reg.tbl: Adjust comments.
787 (rip): Use Qword instead of BaseIndex. Use RegIP.
788 (eip): Use Dword instead of BaseIndex. Use RegIP.
789 (riz): Add Qword. Use RegIZ.
790 (eiz): Add Dword. Use RegIZ.
791 * i386-tbl.h: Re-generate.
793 2018-08-03 Jan Beulich <jbeulich@suse.com>
795 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
796 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
797 vpmovzxdq, vpmovzxwd): Remove NoRex64.
798 * i386-tbl.h: Re-generate.
800 2018-08-03 Jan Beulich <jbeulich@suse.com>
802 * i386-gen.c (operand_types): Remove Mem field.
803 * i386-opc.h (union i386_operand_type): Remove mem field.
804 * i386-init.h, i386-tbl.h: Re-generate.
806 2018-08-01 Alan Modra <amodra@gmail.com>
808 * po/POTFILES.in: Regenerate.
810 2018-07-31 Nick Clifton <nickc@redhat.com>
812 * po/sv.po: Updated Swedish translation.
814 2018-07-31 Jan Beulich <jbeulich@suse.com>
816 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
817 * i386-init.h, i386-tbl.h: Re-generate.
819 2018-07-31 Jan Beulich <jbeulich@suse.com>
821 * i386-opc.h (ZEROING_MASKING) Rename to ...
822 (DYNAMIC_MASKING): ... this. Adjust comment.
823 * i386-opc.tbl (MaskingMorZ): Define.
824 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
825 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
826 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
827 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
828 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
829 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
830 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
831 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
832 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
834 2018-07-31 Jan Beulich <jbeulich@suse.com>
836 * i386-opc.tbl: Use element rather than vector size for AVX512*
837 scatter/gather insns.
838 * i386-tbl.h: Re-generate.
840 2018-07-31 Jan Beulich <jbeulich@suse.com>
842 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
843 (cpu_flags): Drop CpuVREX.
844 * i386-opc.h (CpuVREX): Delete.
845 (union i386_cpu_flags): Remove cpuvrex.
846 * i386-init.h, i386-tbl.h: Re-generate.
848 2018-07-30 Jim Wilson <jimw@sifive.com>
850 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
852 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
854 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
856 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
857 * Makefile.in: Regenerated.
858 * configure.ac: Add C-SKY.
859 * configure: Regenerated.
860 * csky-dis.c: New file.
861 * csky-opc.h: New file.
862 * disassemble.c (ARCH_csky): Define.
863 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
864 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
866 2018-07-27 Alan Modra <amodra@gmail.com>
868 * ppc-opc.c (insert_sprbat): Correct function parameter and
870 (extract_sprbat): Likewise, variable too.
872 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
873 Alan Modra <amodra@gmail.com>
875 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
876 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
877 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
878 support disjointed BAT.
879 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
880 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
881 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
883 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
884 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
886 * i386-gen.c (adjust_broadcast_modifier): New function.
887 (process_i386_opcode_modifier): Add an argument for operands.
888 Adjust the Broadcast value based on operands.
889 (output_i386_opcode): Pass operand_types to
890 process_i386_opcode_modifier.
891 (process_i386_opcodes): Pass NULL as operands to
892 process_i386_opcode_modifier.
893 * i386-opc.h (BYTE_BROADCAST): New.
894 (WORD_BROADCAST): Likewise.
895 (DWORD_BROADCAST): Likewise.
896 (QWORD_BROADCAST): Likewise.
897 (i386_opcode_modifier): Expand broadcast to 3 bits.
898 * i386-tbl.h: Regenerated.
900 2018-07-24 Alan Modra <amodra@gmail.com>
903 * or1k-desc.h: Regenerate.
905 2018-07-24 Jan Beulich <jbeulich@suse.com>
907 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
908 vcvtusi2ss, and vcvtusi2sd.
909 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
910 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
911 * i386-tbl.h: Re-generate.
913 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
915 * arc-opc.c (extract_w6): Fix extending the sign.
917 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
919 * arc-tbl.h (vewt): Allow it for ARC EM family.
921 2018-07-23 Alan Modra <amodra@gmail.com>
924 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
925 opcode variants for mtspr/mfspr encodings.
927 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
928 Maciej W. Rozycki <macro@mips.com>
930 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
931 loongson3a descriptors.
932 (parse_mips_ase_option): Handle -M loongson-mmi option.
933 (print_mips_disassembler_options): Document -M loongson-mmi.
934 * mips-opc.c (LMMI): New macro.
935 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
938 2018-07-19 Jan Beulich <jbeulich@suse.com>
940 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
941 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
942 IgnoreSize and [XYZ]MMword where applicable.
943 * i386-tbl.h: Re-generate.
945 2018-07-19 Jan Beulich <jbeulich@suse.com>
947 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
948 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
949 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
950 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
951 * i386-tbl.h: Re-generate.
953 2018-07-19 Jan Beulich <jbeulich@suse.com>
955 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
956 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
957 VPCLMULQDQ templates into their respective AVX512VL counterparts
958 where possible, using Disp8ShiftVL and CheckRegSize instead of
959 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
960 * i386-tbl.h: Re-generate.
962 2018-07-19 Jan Beulich <jbeulich@suse.com>
964 * i386-opc.tbl: Fold AVX512DQ templates into their respective
965 AVX512VL counterparts where possible, using Disp8ShiftVL and
966 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
967 IgnoreSize) as appropriate.
968 * i386-tbl.h: Re-generate.
970 2018-07-19 Jan Beulich <jbeulich@suse.com>
972 * i386-opc.tbl: Fold AVX512BW templates into their respective
973 AVX512VL counterparts where possible, using Disp8ShiftVL and
974 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
975 IgnoreSize) as appropriate.
976 * i386-tbl.h: Re-generate.
978 2018-07-19 Jan Beulich <jbeulich@suse.com>
980 * i386-opc.tbl: Fold AVX512CD templates into their respective
981 AVX512VL counterparts where possible, using Disp8ShiftVL and
982 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
983 IgnoreSize) as appropriate.
984 * i386-tbl.h: Re-generate.
986 2018-07-19 Jan Beulich <jbeulich@suse.com>
988 * i386-opc.h (DISP8_SHIFT_VL): New.
989 * i386-opc.tbl (Disp8ShiftVL): Define.
990 (various): Fold AVX512VL templates into their respective
991 AVX512F counterparts where possible, using Disp8ShiftVL and
992 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
993 IgnoreSize) as appropriate.
994 * i386-tbl.h: Re-generate.
996 2018-07-19 Jan Beulich <jbeulich@suse.com>
998 * Makefile.am: Change dependencies and rule for
999 $(srcdir)/i386-init.h.
1000 * Makefile.in: Re-generate.
1001 * i386-gen.c (process_i386_opcodes): New local variable
1002 "marker". Drop opening of input file. Recognize marker and line
1004 * i386-opc.tbl (OPCODE_I386_H): Define.
1005 (i386-opc.h): Include it.
1008 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1011 * i386-opc.h (Byte): Update comments.
1017 (Xmmword): Likewise.
1018 (Ymmword): Likewise.
1019 (Zmmword): Likewise.
1020 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1022 * i386-tbl.h: Regenerated.
1024 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1026 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1027 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1028 * aarch64-asm-2.c: Regenerate.
1029 * aarch64-dis-2.c: Regenerate.
1030 * aarch64-opc-2.c: Regenerate.
1032 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1035 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1036 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1037 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1038 sqdmulh, sqrdmulh): Use Em16.
1040 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1042 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1043 csdb together with them.
1044 (thumb32_opcodes): Likewise.
1046 2018-07-11 Jan Beulich <jbeulich@suse.com>
1048 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1049 requiring 32-bit registers as operands 2 and 3. Improve
1051 (mwait, mwaitx): Fold templates. Improve comments.
1052 OPERAND_TYPE_INOUTPORTREG.
1053 * i386-tbl.h: Re-generate.
1055 2018-07-11 Jan Beulich <jbeulich@suse.com>
1057 * i386-gen.c (operand_type_init): Remove
1058 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1059 OPERAND_TYPE_INOUTPORTREG.
1060 * i386-init.h: Re-generate.
1062 2018-07-11 Jan Beulich <jbeulich@suse.com>
1064 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1065 (wrssq, wrussq): Add Qword.
1066 * i386-tbl.h: Re-generate.
1068 2018-07-11 Jan Beulich <jbeulich@suse.com>
1070 * i386-opc.h: Rename OTMax to OTNum.
1071 (OTNumOfUints): Adjust calculation.
1072 (OTUnused): Directly alias to OTNum.
1074 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1076 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1078 (lea_reg_xys): Likewise.
1079 (print_insn_loop_primitive): Rename `reg' local variable to
1082 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1085 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1087 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1090 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1091 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1093 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1096 * mips-dis.c (mips_option_arg_t): New enumeration.
1097 (mips_options): New variable.
1098 (disassembler_options_mips): New function.
1099 (print_mips_disassembler_options): Reimplement in terms of
1100 `disassembler_options_mips'.
1101 * arm-dis.c (disassembler_options_arm): Adapt to using the
1102 `disasm_options_and_args_t' structure.
1103 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1104 * s390-dis.c (disassembler_options_s390): Likewise.
1106 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1108 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1110 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1111 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1112 * testsuite/ld-arm/tls-longplt.d: Likewise.
1114 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1117 * aarch64-asm-2.c: Regenerate.
1118 * aarch64-dis-2.c: Likewise.
1119 * aarch64-opc-2.c: Likewise.
1120 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1121 * aarch64-opc.c (operand_general_constraint_met_p,
1122 aarch64_print_operand): Likewise.
1123 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1124 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1126 (AARCH64_OPERANDS): Add Em2.
1128 2018-06-26 Nick Clifton <nickc@redhat.com>
1130 * po/uk.po: Updated Ukranian translation.
1131 * po/de.po: Updated German translation.
1132 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1134 2018-06-26 Nick Clifton <nickc@redhat.com>
1136 * nfp-dis.c: Fix spelling mistake.
1138 2018-06-24 Nick Clifton <nickc@redhat.com>
1140 * configure: Regenerate.
1141 * po/opcodes.pot: Regenerate.
1143 2018-06-24 Nick Clifton <nickc@redhat.com>
1145 2.31 branch created.
1147 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1149 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1150 * aarch64-asm-2.c: Regenerate.
1151 * aarch64-dis-2.c: Likewise.
1153 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1155 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1156 `-M ginv' option description.
1158 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1161 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1164 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1166 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1167 * configure.ac: Remove AC_PREREQ.
1168 * Makefile.in: Re-generate.
1169 * aclocal.m4: Re-generate.
1170 * configure: Re-generate.
1172 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1174 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1175 mips64r6 descriptors.
1176 (parse_mips_ase_option): Handle -Mginv option.
1177 (print_mips_disassembler_options): Document -Mginv.
1178 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1180 (mips_opcodes): Define ginvi and ginvt.
1182 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1183 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1185 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1186 * mips-opc.c (CRC, CRC64): New macros.
1187 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1188 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1191 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1194 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1195 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1197 2018-06-06 Alan Modra <amodra@gmail.com>
1199 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1200 setjmp. Move init for some other vars later too.
1202 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1204 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1205 (dis_private): Add new fields for property section tracking.
1206 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1207 (xtensa_instruction_fits): New functions.
1208 (fetch_data): Bump minimal fetch size to 4.
1209 (print_insn_xtensa): Make struct dis_private static.
1210 Load and prepare property table on section change.
1211 Don't disassemble literals. Don't disassemble instructions that
1212 cross property table boundaries.
1214 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1216 * configure: Regenerated.
1218 2018-06-01 Jan Beulich <jbeulich@suse.com>
1220 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1221 * i386-tbl.h: Re-generate.
1223 2018-06-01 Jan Beulich <jbeulich@suse.com>
1225 * i386-opc.tbl (sldt, str): Add NoRex64.
1226 * i386-tbl.h: Re-generate.
1228 2018-06-01 Jan Beulich <jbeulich@suse.com>
1230 * i386-opc.tbl (invpcid): Add Oword.
1231 * i386-tbl.h: Re-generate.
1233 2018-06-01 Alan Modra <amodra@gmail.com>
1235 * sysdep.h (_bfd_error_handler): Don't declare.
1236 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1237 * rl78-decode.opc: Likewise.
1238 * msp430-decode.c: Regenerate.
1239 * rl78-decode.c: Regenerate.
1241 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1243 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1244 * i386-init.h : Regenerated.
1246 2018-05-25 Alan Modra <amodra@gmail.com>
1248 * Makefile.in: Regenerate.
1249 * po/POTFILES.in: Regenerate.
1251 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1253 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1254 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1255 (insert_bab, extract_bab, insert_btab, extract_btab,
1256 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1257 (BAT, BBA VBA RBS XB6S): Delete macros.
1258 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1259 (BB, BD, RBX, XC6): Update for new macros.
1260 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1261 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1262 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1263 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1265 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1267 * Makefile.am: Add support for s12z architecture.
1268 * configure.ac: Likewise.
1269 * disassemble.c: Likewise.
1270 * disassemble.h: Likewise.
1271 * Makefile.in: Regenerate.
1272 * configure: Regenerate.
1273 * s12z-dis.c: New file.
1276 2018-05-18 Alan Modra <amodra@gmail.com>
1278 * nfp-dis.c: Don't #include libbfd.h.
1279 (init_nfp3200_priv): Use bfd_get_section_contents.
1280 (nit_nfp6000_mecsr_sec): Likewise.
1282 2018-05-17 Nick Clifton <nickc@redhat.com>
1284 * po/zh_CN.po: Updated simplified Chinese translation.
1286 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1289 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1290 * aarch64-dis-2.c: Regenerate.
1292 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1295 * aarch64-asm.c (opintl.h): Include.
1296 (aarch64_ins_sysreg): Enforce read/write constraints.
1297 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1298 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1299 (F_REG_READ, F_REG_WRITE): New.
1300 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1301 AARCH64_OPND_SYSREG.
1302 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1303 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1304 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1305 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1306 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1307 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1308 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1309 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1310 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1311 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1312 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1313 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1314 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1315 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1316 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1317 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1318 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1320 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1323 * aarch64-dis.c (no_notes: New.
1324 (parse_aarch64_dis_option): Support notes.
1325 (aarch64_decode_insn, print_operands): Likewise.
1326 (print_aarch64_disassembler_options): Document notes.
1327 * aarch64-opc.c (aarch64_print_operand): Support notes.
1329 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1332 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1333 and take error struct.
1334 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1335 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1336 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1337 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1338 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1339 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1340 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1341 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1342 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1343 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1344 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1345 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1346 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1347 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1348 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1349 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1350 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1351 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1352 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1353 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1354 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1355 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1356 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1357 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1358 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1359 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1360 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1361 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1362 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1363 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1364 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1365 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1366 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1367 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1368 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1369 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1370 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1371 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1372 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1373 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1374 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1375 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1376 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1377 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1378 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1379 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1380 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1381 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1382 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1383 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1384 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1385 (determine_disassembling_preference, aarch64_decode_insn,
1386 print_insn_aarch64_word, print_insn_data): Take errors struct.
1387 (print_insn_aarch64): Use errors.
1388 * aarch64-asm-2.c: Regenerate.
1389 * aarch64-dis-2.c: Regenerate.
1390 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1391 boolean in aarch64_insert_operan.
1392 (print_operand_extractor): Likewise.
1393 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1395 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1397 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1399 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1401 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1403 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1405 * cr16-opc.c (cr16_instruction): Comment typo fix.
1406 * hppa-dis.c (print_insn_hppa): Likewise.
1408 2018-05-08 Jim Wilson <jimw@sifive.com>
1410 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1411 (match_c_slli64, match_srxi_as_c_srxi): New.
1412 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1413 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1414 <c.slli, c.srli, c.srai>: Use match_s_slli.
1415 <c.slli64, c.srli64, c.srai64>: New.
1417 2018-05-08 Alan Modra <amodra@gmail.com>
1419 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1420 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1421 partition opcode space for index lookup.
1423 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1425 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1426 <insn_length>: ...with this. Update usage.
1427 Remove duplicate call to *info->memory_error_func.
1429 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1430 H.J. Lu <hongjiu.lu@intel.com>
1432 * i386-dis.c (Gva): New.
1433 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1434 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1435 (prefix_table): New instructions (see prefix above).
1436 (mod_table): New instructions (see prefix above).
1437 (OP_G): Handle va_mode.
1438 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1439 CPU_MOVDIR64B_FLAGS.
1440 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1441 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1442 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1443 * i386-opc.tbl: Add movidir{i,64b}.
1444 * i386-init.h: Regenerated.
1445 * i386-tbl.h: Likewise.
1447 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1449 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1451 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1452 (AddrPrefixOpReg): This.
1453 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1454 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1456 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1458 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1459 (vle_num_opcodes): Likewise.
1460 (spe2_num_opcodes): Likewise.
1461 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1462 initialization loop.
1463 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1464 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1467 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1469 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1471 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1473 Makefile.am: Added nfp-dis.c.
1474 configure.ac: Added bfd_nfp_arch.
1475 disassemble.h: Added print_insn_nfp prototype.
1476 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1477 nfp-dis.c: New, for NFP support.
1478 po/POTFILES.in: Added nfp-dis.c to the list.
1479 Makefile.in: Regenerate.
1480 configure: Regenerate.
1482 2018-04-26 Jan Beulich <jbeulich@suse.com>
1484 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1485 templates into their base ones.
1486 * i386-tlb.h: Re-generate.
1488 2018-04-26 Jan Beulich <jbeulich@suse.com>
1490 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1491 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1492 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1493 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1494 * i386-init.h: Re-generate.
1496 2018-04-26 Jan Beulich <jbeulich@suse.com>
1498 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1499 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1500 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1501 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1503 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1505 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1507 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1508 cpuregzmm, and cpuregmask.
1509 * i386-init.h: Re-generate.
1510 * i386-tbl.h: Re-generate.
1512 2018-04-26 Jan Beulich <jbeulich@suse.com>
1514 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1515 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1516 * i386-init.h: Re-generate.
1518 2018-04-26 Jan Beulich <jbeulich@suse.com>
1520 * i386-gen.c (VexImmExt): Delete.
1521 * i386-opc.h (VexImmExt, veximmext): Delete.
1522 * i386-opc.tbl: Drop all VexImmExt uses.
1523 * i386-tlb.h: Re-generate.
1525 2018-04-25 Jan Beulich <jbeulich@suse.com>
1527 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1528 register-only forms.
1529 * i386-tlb.h: Re-generate.
1531 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1533 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1535 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1537 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1539 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1540 (cpu_flags): Add CpuCLDEMOTE.
1541 * i386-init.h: Regenerate.
1542 * i386-opc.h (enum): Add CpuCLDEMOTE,
1543 (i386_cpu_flags): Add cpucldemote.
1544 * i386-opc.tbl: Add cldemote.
1545 * i386-tbl.h: Regenerate.
1547 2018-04-16 Alan Modra <amodra@gmail.com>
1549 * Makefile.am: Remove sh5 and sh64 support.
1550 * configure.ac: Likewise.
1551 * disassemble.c: Likewise.
1552 * disassemble.h: Likewise.
1553 * sh-dis.c: Likewise.
1554 * sh64-dis.c: Delete.
1555 * sh64-opc.c: Delete.
1556 * sh64-opc.h: Delete.
1557 * Makefile.in: Regenerate.
1558 * configure: Regenerate.
1559 * po/POTFILES.in: Regenerate.
1561 2018-04-16 Alan Modra <amodra@gmail.com>
1563 * Makefile.am: Remove w65 support.
1564 * configure.ac: Likewise.
1565 * disassemble.c: Likewise.
1566 * disassemble.h: Likewise.
1567 * w65-dis.c: Delete.
1568 * w65-opc.h: Delete.
1569 * Makefile.in: Regenerate.
1570 * configure: Regenerate.
1571 * po/POTFILES.in: Regenerate.
1573 2018-04-16 Alan Modra <amodra@gmail.com>
1575 * configure.ac: Remove we32k support.
1576 * configure: Regenerate.
1578 2018-04-16 Alan Modra <amodra@gmail.com>
1580 * Makefile.am: Remove m88k support.
1581 * configure.ac: Likewise.
1582 * disassemble.c: Likewise.
1583 * disassemble.h: Likewise.
1584 * m88k-dis.c: Delete.
1585 * Makefile.in: Regenerate.
1586 * configure: Regenerate.
1587 * po/POTFILES.in: Regenerate.
1589 2018-04-16 Alan Modra <amodra@gmail.com>
1591 * Makefile.am: Remove i370 support.
1592 * configure.ac: Likewise.
1593 * disassemble.c: Likewise.
1594 * disassemble.h: Likewise.
1595 * i370-dis.c: Delete.
1596 * i370-opc.c: Delete.
1597 * Makefile.in: Regenerate.
1598 * configure: Regenerate.
1599 * po/POTFILES.in: Regenerate.
1601 2018-04-16 Alan Modra <amodra@gmail.com>
1603 * Makefile.am: Remove h8500 support.
1604 * configure.ac: Likewise.
1605 * disassemble.c: Likewise.
1606 * disassemble.h: Likewise.
1607 * h8500-dis.c: Delete.
1608 * h8500-opc.h: Delete.
1609 * Makefile.in: Regenerate.
1610 * configure: Regenerate.
1611 * po/POTFILES.in: Regenerate.
1613 2018-04-16 Alan Modra <amodra@gmail.com>
1615 * configure.ac: Remove tahoe support.
1616 * configure: Regenerate.
1618 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1620 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1622 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1624 * i386-tbl.h: Regenerated.
1626 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1628 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1629 PREFIX_MOD_1_0FAE_REG_6.
1631 (OP_E_register): Use va_mode.
1632 * i386-dis-evex.h (prefix_table):
1633 New instructions (see prefixes above).
1634 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1635 (cpu_flags): Likewise.
1636 * i386-opc.h (enum): Likewise.
1637 (i386_cpu_flags): Likewise.
1638 * i386-opc.tbl: Add umonitor, umwait, tpause.
1639 * i386-init.h: Regenerate.
1640 * i386-tbl.h: Likewise.
1642 2018-04-11 Alan Modra <amodra@gmail.com>
1644 * opcodes/i860-dis.c: Delete.
1645 * opcodes/i960-dis.c: Delete.
1646 * Makefile.am: Remove i860 and i960 support.
1647 * configure.ac: Likewise.
1648 * disassemble.c: Likewise.
1649 * disassemble.h: Likewise.
1650 * Makefile.in: Regenerate.
1651 * configure: Regenerate.
1652 * po/POTFILES.in: Regenerate.
1654 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1657 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1659 (print_insn): Clear vex instead of vex.evex.
1661 2018-04-04 Nick Clifton <nickc@redhat.com>
1663 * po/es.po: Updated Spanish translation.
1665 2018-03-28 Jan Beulich <jbeulich@suse.com>
1667 * i386-gen.c (opcode_modifiers): Delete VecESize.
1668 * i386-opc.h (VecESize): Delete.
1669 (struct i386_opcode_modifier): Delete vecesize.
1670 * i386-opc.tbl: Drop VecESize.
1671 * i386-tlb.h: Re-generate.
1673 2018-03-28 Jan Beulich <jbeulich@suse.com>
1675 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1676 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1677 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1678 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1679 * i386-tlb.h: Re-generate.
1681 2018-03-28 Jan Beulich <jbeulich@suse.com>
1683 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1685 * i386-tlb.h: Re-generate.
1687 2018-03-28 Jan Beulich <jbeulich@suse.com>
1689 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1690 (vex_len_table): Drop Y for vcvt*2si.
1691 (putop): Replace plain 'Y' handling by abort().
1693 2018-03-28 Nick Clifton <nickc@redhat.com>
1696 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1697 instructions with only a base address register.
1698 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1699 handle AARHC64_OPND_SVE_ADDR_R.
1700 (aarch64_print_operand): Likewise.
1701 * aarch64-asm-2.c: Regenerate.
1702 * aarch64_dis-2.c: Regenerate.
1703 * aarch64-opc-2.c: Regenerate.
1705 2018-03-22 Jan Beulich <jbeulich@suse.com>
1707 * i386-opc.tbl: Drop VecESize from register only insn forms and
1708 memory forms not allowing broadcast.
1709 * i386-tlb.h: Re-generate.
1711 2018-03-22 Jan Beulich <jbeulich@suse.com>
1713 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1714 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1715 sha256*): Drop Disp<N>.
1717 2018-03-22 Jan Beulich <jbeulich@suse.com>
1719 * i386-dis.c (EbndS, bnd_swap_mode): New.
1720 (prefix_table): Use EbndS.
1721 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1722 * i386-opc.tbl (bndmov): Move misplaced Load.
1723 * i386-tlb.h: Re-generate.
1725 2018-03-22 Jan Beulich <jbeulich@suse.com>
1727 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1728 templates allowing memory operands and folded ones for register
1730 * i386-tlb.h: Re-generate.
1732 2018-03-22 Jan Beulich <jbeulich@suse.com>
1734 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1735 256-bit templates. Drop redundant leftover Disp<N>.
1736 * i386-tlb.h: Re-generate.
1738 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1740 * riscv-opc.c (riscv_insn_types): New.
1742 2018-03-13 Nick Clifton <nickc@redhat.com>
1744 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1746 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1748 * i386-opc.tbl: Add Optimize to clr.
1749 * i386-tbl.h: Regenerated.
1751 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1753 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1754 * i386-opc.h (OldGcc): Removed.
1755 (i386_opcode_modifier): Remove oldgcc.
1756 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1757 instructions for old (<= 2.8.1) versions of gcc.
1758 * i386-tbl.h: Regenerated.
1760 2018-03-08 Jan Beulich <jbeulich@suse.com>
1762 * i386-opc.h (EVEXDYN): New.
1763 * i386-opc.tbl: Fold various AVX512VL templates.
1764 * i386-tlb.h: Re-generate.
1766 2018-03-08 Jan Beulich <jbeulich@suse.com>
1768 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1769 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1770 vpexpandd, vpexpandq): Fold AFX512VF templates.
1771 * i386-tlb.h: Re-generate.
1773 2018-03-08 Jan Beulich <jbeulich@suse.com>
1775 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1776 Fold 128- and 256-bit VEX-encoded templates.
1777 * i386-tlb.h: Re-generate.
1779 2018-03-08 Jan Beulich <jbeulich@suse.com>
1781 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1782 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1783 vpexpandd, vpexpandq): Fold AVX512F templates.
1784 * i386-tlb.h: Re-generate.
1786 2018-03-08 Jan Beulich <jbeulich@suse.com>
1788 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1789 64-bit templates. Drop Disp<N>.
1790 * i386-tlb.h: Re-generate.
1792 2018-03-08 Jan Beulich <jbeulich@suse.com>
1794 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1795 and 256-bit templates.
1796 * i386-tlb.h: Re-generate.
1798 2018-03-08 Jan Beulich <jbeulich@suse.com>
1800 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1801 * i386-tlb.h: Re-generate.
1803 2018-03-08 Jan Beulich <jbeulich@suse.com>
1805 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1807 * i386-tlb.h: Re-generate.
1809 2018-03-08 Jan Beulich <jbeulich@suse.com>
1811 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1812 * i386-tlb.h: Re-generate.
1814 2018-03-08 Jan Beulich <jbeulich@suse.com>
1816 * i386-gen.c (opcode_modifiers): Delete FloatD.
1817 * i386-opc.h (FloatD): Delete.
1818 (struct i386_opcode_modifier): Delete floatd.
1819 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1821 * i386-tlb.h: Re-generate.
1823 2018-03-08 Jan Beulich <jbeulich@suse.com>
1825 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1827 2018-03-08 Jan Beulich <jbeulich@suse.com>
1829 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1830 * i386-tlb.h: Re-generate.
1832 2018-03-08 Jan Beulich <jbeulich@suse.com>
1834 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1836 * i386-tlb.h: Re-generate.
1838 2018-03-07 Alan Modra <amodra@gmail.com>
1840 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1842 * disassemble.h (print_insn_rs6000): Delete.
1843 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1844 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1845 (print_insn_rs6000): Delete.
1847 2018-03-03 Alan Modra <amodra@gmail.com>
1849 * sysdep.h (opcodes_error_handler): Define.
1850 (_bfd_error_handler): Declare.
1851 * Makefile.am: Remove stray #.
1852 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1854 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1855 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1856 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1857 opcodes_error_handler to print errors. Standardize error messages.
1858 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1859 and include opintl.h.
1860 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1861 * i386-gen.c: Standardize error messages.
1862 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1863 * Makefile.in: Regenerate.
1864 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1865 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1866 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1867 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1868 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1869 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1870 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1871 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1872 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1873 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1874 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1875 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1876 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1878 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1880 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1881 vpsub[bwdq] instructions.
1882 * i386-tbl.h: Regenerated.
1884 2018-03-01 Alan Modra <amodra@gmail.com>
1886 * configure.ac (ALL_LINGUAS): Sort.
1887 * configure: Regenerate.
1889 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1891 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1892 macro by assignements.
1894 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1897 * i386-gen.c (opcode_modifiers): Add Optimize.
1898 * i386-opc.h (Optimize): New enum.
1899 (i386_opcode_modifier): Add optimize.
1900 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1901 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1902 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1903 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1904 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1906 * i386-tbl.h: Regenerated.
1908 2018-02-26 Alan Modra <amodra@gmail.com>
1910 * crx-dis.c (getregliststring): Allocate a large enough buffer
1911 to silence false positive gcc8 warning.
1913 2018-02-22 Shea Levy <shea@shealevy.com>
1915 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1917 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1919 * i386-opc.tbl: Add {rex},
1920 * i386-tbl.h: Regenerated.
1922 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1924 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1925 (mips16_opcodes): Replace `M' with `m' for "restore".
1927 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1929 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1931 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1933 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1934 variable to `function_index'.
1936 2018-02-13 Nick Clifton <nickc@redhat.com>
1939 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1940 about truncation of printing.
1942 2018-02-12 Henry Wong <henry@stuffedcow.net>
1944 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1946 2018-02-05 Nick Clifton <nickc@redhat.com>
1948 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1950 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1952 * i386-dis.c (enum): Add pconfig.
1953 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1954 (cpu_flags): Add CpuPCONFIG.
1955 * i386-opc.h (enum): Add CpuPCONFIG.
1956 (i386_cpu_flags): Add cpupconfig.
1957 * i386-opc.tbl: Add PCONFIG instruction.
1958 * i386-init.h: Regenerate.
1959 * i386-tbl.h: Likewise.
1961 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1963 * i386-dis.c (enum): Add PREFIX_0F09.
1964 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1965 (cpu_flags): Add CpuWBNOINVD.
1966 * i386-opc.h (enum): Add CpuWBNOINVD.
1967 (i386_cpu_flags): Add cpuwbnoinvd.
1968 * i386-opc.tbl: Add WBNOINVD instruction.
1969 * i386-init.h: Regenerate.
1970 * i386-tbl.h: Likewise.
1972 2018-01-17 Jim Wilson <jimw@sifive.com>
1974 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1976 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1978 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1979 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1980 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1981 (cpu_flags): Add CpuIBT, CpuSHSTK.
1982 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1983 (i386_cpu_flags): Add cpuibt, cpushstk.
1984 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1985 * i386-init.h: Regenerate.
1986 * i386-tbl.h: Likewise.
1988 2018-01-16 Nick Clifton <nickc@redhat.com>
1990 * po/pt_BR.po: Updated Brazilian Portugese translation.
1991 * po/de.po: Updated German translation.
1993 2018-01-15 Jim Wilson <jimw@sifive.com>
1995 * riscv-opc.c (match_c_nop): New.
1996 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1998 2018-01-15 Nick Clifton <nickc@redhat.com>
2000 * po/uk.po: Updated Ukranian translation.
2002 2018-01-13 Nick Clifton <nickc@redhat.com>
2004 * po/opcodes.pot: Regenerated.
2006 2018-01-13 Nick Clifton <nickc@redhat.com>
2008 * configure: Regenerate.
2010 2018-01-13 Nick Clifton <nickc@redhat.com>
2012 2.30 branch created.
2014 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2016 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2017 * i386-tbl.h: Regenerate.
2019 2018-01-10 Jan Beulich <jbeulich@suse.com>
2021 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2022 * i386-tbl.h: Re-generate.
2024 2018-01-10 Jan Beulich <jbeulich@suse.com>
2026 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2027 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2028 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2029 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2030 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2031 Disp8MemShift of AVX512VL forms.
2032 * i386-tbl.h: Re-generate.
2034 2018-01-09 Jim Wilson <jimw@sifive.com>
2036 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2037 then the hi_addr value is zero.
2039 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2041 * arm-dis.c (arm_opcodes): Add csdb.
2042 (thumb32_opcodes): Add csdb.
2044 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2046 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2047 * aarch64-asm-2.c: Regenerate.
2048 * aarch64-dis-2.c: Regenerate.
2049 * aarch64-opc-2.c: Regenerate.
2051 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2054 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2055 Remove AVX512 vmovd with 64-bit operands.
2056 * i386-tbl.h: Regenerated.
2058 2018-01-05 Jim Wilson <jimw@sifive.com>
2060 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2063 2018-01-03 Alan Modra <amodra@gmail.com>
2065 Update year range in copyright notice of all files.
2067 2018-01-02 Jan Beulich <jbeulich@suse.com>
2069 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2070 and OPERAND_TYPE_REGZMM entries.
2072 For older changes see ChangeLog-2017
2074 Copyright (C) 2018 Free Software Foundation, Inc.
2076 Copying and distribution of this file, with or without modification,
2077 are permitted in any medium without royalty provided the copyright
2078 notice and this notice are preserved.
2084 version-control: never