opcodes/ChangeLog

   1 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
   2
   3         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
   4         correction to unaligned PCs while printing comment.
   5
   6 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
   7
   8         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
   9         (thumb32_opcodes): Likewise.
  10         (banked_regname): New function.
  11         (print_insn_arm): Add Virtualization Extensions support.
  12         (print_insn_thumb32): Likewise.
  13
  14 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  15
  16         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
  17         ARM state.
  18
  19 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  20
  21         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
  22         (thumb32_opcodes): Likewise.
  23
  24 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  25
  26         * arm-dis.c (arm_opcodes): Add support for pldw.
  27         (thumb32_opcodes): Likewise.
  28
  29 2010-09-22  Robin Getz  <robin.getz@analog.com>
  30
  31         * bfin-dis.c (fmtconst): Cast address to 32bits.
  32
  33 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  34
  35         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
  36
  37 2010-09-22  Robin Getz  <robin.getz@analog.com>
  38
  39         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
  40         Reject P6/P7 to TESTSET.
  41         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
  42         SP onto the stack.
  43         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
  44         P/D fields match all the time.
  45         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
  46         are 0 for accumulator compares.
  47         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
  48         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
  49         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
  50         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  51         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
  52         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
  53         insns.
  54         (decode_dagMODim_0): Verify br field for IREG ops.
  55         (decode_LDST_0): Reject preg load into same preg.
  56         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
  57         (print_insn_bfin): Likewise.
  58
  59 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  60
  61         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
  62
  63 2010-09-22  Robin Getz  <robin.getz@analog.com>
  64
  65         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
  66
  67 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  68
  69         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
  70
  71 2010-09-22  Robin Getz  <robin.getz@analog.com>
  72
  73         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
  74         register values greater than 8.
  75         (IS_RESERVEDREG, allreg, mostreg): New helpers.
  76         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
  77         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
  78         (decode_CC2dreg_0): Check valid CC register number.
  79
  80 2010-09-22  Robin Getz  <robin.getz@analog.com>
  81
  82         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
  83
  84 2010-09-22  Robin Getz  <robin.getz@analog.com>
  85
  86         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
  87         (reg_names): Likewise.
  88         (decode_statbits): Likewise; while reformatting to make manageable.
  89
  90 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  91
  92         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
  93         (decode_pseudoOChar_0): New function.
  94         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
  95
  96 2010-09-22  Robin Getz  <robin.getz@analog.com>
  97
  98         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
  99         LSHIFT instead of SHIFT.
 100
 101 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 102
 103         * bfin-dis.c (constant_formats): Constify the whole structure.
 104         (fmtconst): Add const to return value.
 105         (reg_names): Mark const.
 106         (decode_multfunc): Mark s0/s1 as const.
 107         (decode_macfunc): Mark a/sop as const.
 108
 109 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 110
 111         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 112
 113 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 114
 115         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 116         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 117
 118 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 119
 120         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 121         dlx_insn_type array.
 122
 123 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         PR binutils/11960
 126         * i386-dis.c (sIv): New.
 127         (dis386): Replace Iq with sIv on "pushT".
 128         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 129         (x86_64_table): Replace {T|}/{P|} with P.
 130         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 131         (OP_sI): Update v_mode.  Remove w_mode.
 132
 133 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 134
 135         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 136         on E500 and E500MC.
 137
 138 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 141         prefetchw.
 142
 143 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 144
 145         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 146         to processor flags for PENTIUMPRO processors and later.
 147         * i386-opc.h (enum): Add CpuNop.
 148         (i386_cpu_flags): Add cpunop bit.
 149         * i386-opc.tbl: Change nop cpu_flags.
 150         * i386-init.h: Regenerated.
 151         * i386-tbl.h: Likewise.
 152
 153 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 154
 155         * i386-opc.h (enum): Fix typos in comments.
 156
 157 2010-08-06  Alan Modra  <amodra@gmail.com>
 158
 159         * disassemble.c: Formatting.
 160         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 161
 162 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 165         * i386-tbl.h: Regenerated.
 166
 167 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 168
 169         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 170
 171         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 172         * i386-tbl.h: Regenerated.
 173
 174 2010-07-29  DJ Delorie  <dj@redhat.com>
 175
 176         * rx-decode.opc (SRR): New.
 177         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 178         r0,r0) and NOP3 (max r0,r0) special cases.
 179         * rx-decode.c: Regenerate.
 180
 181 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 182
 183         * i386-dis.c: Add 0F to VEX opcode enums.
 184
 185 2010-07-27  DJ Delorie  <dj@redhat.com>
 186
 187         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 188         (rx_decode_opcode): Likewise.
 189         * rx-decode.c: Regenerate.
 190
 191 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 192             Ina Pandit  <ina.pandit@kpitcummins.com>
 193
 194         * v850-dis.c (v850_sreg_names): Updated structure for system
 195         registers.
 196         (float_cc_names): new structure for condition codes.
 197         (print_value): Update the function that prints value.
 198         (get_operand_value): New function to get the operand value.
 199         (disassemble): Updated to handle the disassembly of instructions.
 200         (print_insn_v850): Updated function to print instruction for different
 201         families.
 202         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 203         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 204         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 205         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 206         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 207         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 208         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 209         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 210         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 211         (v850_operands): Update with the relocation name. Also update
 212         the instructions with specific set of processors.
 213
 214 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 215
 216         * arm-dis.c (print_insn_arm): Add cases for printing more
 217         symbolic operands.
 218         (print_insn_thumb32): Likewise.
 219
 220 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 221
 222         * mips-dis.c (print_insn_mips): Correct branch instruction type
 223         determination.
 224
 225 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 226
 227         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 228         type and delay slot determination.
 229         (print_insn_mips16): Extend branch instruction type and delay
 230         slot determination to cover all instructions.
 231         * mips16-opc.c (BR): Remove macro.
 232         (UBR, CBR): New macros.
 233         (mips16_opcodes): Update branch annotation for "b", "beqz",
 234         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 235         and "jrc".
 236
 237 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 238
 239         AVX Programming Reference (June, 2010)
 240         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 241         * i386-opc.tbl: Likewise.
 242         * i386-tbl.h: Regenerated.
 243
 244 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 247
 248 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 249
 250         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 251         ppc_cpu_t before inverting.
 252         (ppc_parse_cpu): Likewise.
 253         (print_insn_powerpc): Likewise.
 254
 255 2010-07-03  Alan Modra  <amodra@gmail.com>
 256
 257         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 258         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 259         (PPC64, MFDEC2): Update.
 260         (NON32, NO371): Define.
 261         (powerpc_opcode): Update to not use old opcode flags, and avoid
 262         -m601 duplicates.
 263
 264 2010-07-03  DJ Delorie  <dj@delorie.com>
 265
 266         * m32c-ibld.c: Regenerate.
 267
 268 2010-07-03  Alan Modra  <amodra@gmail.com>
 269
 270         * ppc-opc.c (PWR2COM): Define.
 271         (PPCPWR2): Add PPC_OPCODE_COMMON.
 272         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 273         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 274         "rac" from -mcom.
 275
 276 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         AVX Programming Reference (June, 2010)
 279         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 280         (PREFIX_0FAE_REG_1): Likewise.
 281         (PREFIX_0FAE_REG_2): Likewise.
 282         (PREFIX_0FAE_REG_3): Likewise.
 283         (PREFIX_VEX_3813): Likewise.
 284         (PREFIX_VEX_3A1D): Likewise.
 285         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 286         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 287         PREFIX_VEX_3A1D.
 288         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 289         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 290         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 291
 292         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 293         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 294         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 295
 296         * i386-opc.h (CpuXsaveopt): New.
 297         (CpuFSGSBase): Likewise.
 298         (CpuRdRnd): Likewise.
 299         (CpuF16C): Likewise.
 300         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 301         cpuf16c.
 302
 303         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 304         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 305         * i386-init.h: Regenerated.
 306         * i386-tbl.h: Likewise.
 307
 308 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 309
 310         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 311         and mtocrf on EFS.
 312
 313 2010-06-29  Alan Modra  <amodra@gmail.com>
 314
 315         * maxq-dis.c: Delete file.
 316         * Makefile.am: Remove references to maxq.
 317         * configure.in: Likewise.
 318         * disassemble.c: Likewise.
 319         * Makefile.in: Regenerate.
 320         * configure: Regenerate.
 321         * po/POTFILES.in: Regenerate.
 322
 323 2010-06-29  Alan Modra  <amodra@gmail.com>
 324
 325         * mep-dis.c: Regenerate.
 326
 327 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 328
 329         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 330
 331 2010-06-27  Alan Modra  <amodra@gmail.com>
 332
 333         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 334         (decodeInstr): Likewise.
 335         * dlx-dis.c (print_insn_dlx): Likewise.
 336         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 337         * maxq-dis.c (check_move, print_insn): Likewise.
 338         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 339         * msp430-dis.c (msp430_branchinstr): Likewise.
 340         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 341         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 342         * sparc-dis.c (print_insn_sparc): Likewise.
 343         * fr30-asm.c: Regenerate.
 344         * frv-asm.c: Regenerate.
 345         * ip2k-asm.c: Regenerate.
 346         * iq2000-asm.c: Regenerate.
 347         * lm32-asm.c: Regenerate.
 348         * m32c-asm.c: Regenerate.
 349         * m32r-asm.c: Regenerate.
 350         * mep-asm.c: Regenerate.
 351         * mt-asm.c: Regenerate.
 352         * openrisc-asm.c: Regenerate.
 353         * xc16x-asm.c: Regenerate.
 354         * xstormy16-asm.c: Regenerate.
 355
 356 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 357
 358         PR gas/11673
 359         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 360
 361 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 362
 363         PR binutils/11676
 364         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 365
 366 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 367
 368         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 369         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 370         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 371         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 372         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 373         Treat lwsync as msync on e500.
 374
 375 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 376
 377         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 378
 379 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 380
 381         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 382         constants is the same on 32-bit and 64-bit hosts.
 383
 384 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 385
 386         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 387         .short directives so that they can be reassembled.
 388
 389 2010-05-26  Catherine Moore <clm@codesourcery.com>
 390             David Ung  <davidu@mips.com>
 391
 392         * mips-opc.c: Change membership to I1 for instructions ssnop and
 393         ehb.
 394
 395 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         * i386-dis.c (sib): New.
 398         (get_sib): Likewise.
 399         (print_insn): Call get_sib.
 400         OP_E_memory): Use sib.
 401
 402 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 403
 404         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 405         * mips-opc.c (I16): Remove.
 406         (mips_builtin_op): Reclassify jalx.
 407
 408 2010-05-19  Alan Modra  <amodra@gmail.com>
 409
 410         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 411         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 412
 413 2010-05-13  Alan Modra  <amodra@gmail.com>
 414
 415         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 416
 417 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 418
 419         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 420         format.
 421         (print_insn_thumb16): Add support for new %W format.
 422
 423 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 424
 425         * Makefile.in: Regenerate with automake 1.11.1.
 426         * aclocal.m4: Ditto.
 427
 428 2010-05-05  Nick Clifton  <nickc@redhat.com>
 429
 430         * po/es.po: Updated Spanish translation.
 431
 432 2010-04-22  Nick Clifton  <nickc@redhat.com>
 433
 434         * po/opcodes.pot: Updated by the Translation project.
 435         * po/vi.po: Updated Vietnamese translation.
 436
 437 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 440         bits in opcode.
 441
 442 2010-04-09  Nick Clifton  <nickc@redhat.com>
 443
 444         * i386-dis.c (print_insn): Remove unused variable op.
 445         (OP_sI): Remove unused variable mask.
 446
 447 2010-04-07  Alan Modra  <amodra@gmail.com>
 448
 449         * configure: Regenerate.
 450
 451 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 452
 453         * ppc-opc.c (RBOPT): New define.
 454         ("dccci"): Enable for PPCA2.  Make operands optional.
 455         ("iccci"): Likewise.  Do not deprecate for PPC476.
 456
 457 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 458
 459         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 460
 461 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 462
 463         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 464         * Makefile.in: Regenerate.
 465         * configure.in (bfd_tic6x_arch): New.
 466         * configure: Regenerate.
 467         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 468         (disassembler): Handle TI C6X.
 469         * tic6x-dis.c: New.
 470
 471 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 472
 473         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 474
 475 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 476
 477         * dis-buf.c (buffer_read_memory): Give error for reading just
 478         before the start of memory.
 479
 480 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 481             Quentin Neill <quentin.neill@amd.com>
 482
 483         * i386-dis.c (OP_LWP_I): Removed.
 484         (reg_table): Do not use OP_LWP_I, use Iq.
 485         (OP_LWPCB_E): Remove use of names16.
 486         (OP_LWP_E): Same.
 487         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 488         should not set the Vex.length bit.
 489         * i386-tbl.h: Regenerated.
 490
 491 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 492
 493         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 494
 495 2010-02-24  Nick Clifton  <nickc@redhat.com>
 496
 497         PR binutils/6773
 498         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 499         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 500         (thumb32_opcodes): Likewise.
 501
 502 2010-02-15  Nick Clifton  <nickc@redhat.com>
 503
 504         * po/vi.po: Updated Vietnamese translation.
 505
 506 2010-02-12  Doug Evans  <dje@sebabeach.org>
 507
 508         * lm32-opinst.c: Regenerate.
 509
 510 2010-02-11  Doug Evans  <dje@sebabeach.org>
 511
 512         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 513         (print_address): Delete CGEN_PRINT_ADDRESS.
 514         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 515         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 516         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 517         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 518
 519         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 520         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 521         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 522         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 523         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 524         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 525         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 526         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 527         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 528         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 529         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 530         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 531
 532 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 533
 534         * i386-dis.c: Update copyright.
 535         * i386-gen.c: Likewise.
 536         * i386-opc.h: Likewise.
 537         * i386-opc.tbl: Likewise.
 538
 539 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 540             Sebastian Pop  <sebastian.pop@amd.com>
 541
 542         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 543         function to handle 5th imm8 operand.
 544         (PREFIX_VEX_3A48): Added.
 545         (PREFIX_VEX_3A49): Added.
 546         (VEX_W_3A48_P_2): Added.
 547         (VEX_W_3A49_P_2): Added.
 548         (prefix table): Added entries for PREFIX_VEX_3A48
 549         and PREFIX_VEX_3A49.
 550         (vex table): Added entries for VEX_W_3A48_P_2 and
 551         and VEX_W_3A49_P_2.
 552         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 553         for Vec_Imm4 operands.
 554         * i386-opc.h (enum): Added Vec_Imm4.
 555         (i386_operand_type): Added vec_imm4.
 556         * i386-opc.tbl: Add entries for vpermilp[ds].
 557         * i386-init.h: Regenerated.
 558         * i386-tbl.h: Regenerated.
 559
 560 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 561
 562         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 563         and "pwr7".  Move "a2" into alphabetical order.
 564
 565 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 566
 567         * ppc-dis.c (ppc_opts): Add titan entry.
 568         * ppc-opc.c (TITAN, MULHW): Define.
 569         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 570
 571 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 572
 573         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 574         to CPU_BDVER1_FLAGS
 575         * i386-init.h: Regenerated.
 576
 577 2010-02-03  Anthony Green  <green@moxielogic.com>
 578
 579         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 580         0x0f, and make 0x00 an illegal instruction.
 581
 582 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 583
 584         * opcodes/arm-dis.c (struct arm_private_data): New.
 585         (print_insn_coprocessor, print_insn_arm): Update to use struct
 586         arm_private_data.
 587         (is_mapping_symbol, get_map_sym_type): New functions.
 588         (get_sym_code_type): Check the symbol's section.  Do not check
 589         mapping symbols.
 590         (print_insn): Default to disassembling ARM mode code.  Check
 591         for mapping symbols separately from other symbols.  Use
 592         struct arm_private_data.
 593
 594 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * i386-dis.c (EXVexWdqScalar): New.
 597         (vex_scalar_w_dq_mode): Likewise.
 598         (prefix_table): Update entries for PREFIX_VEX_3899,
 599         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 600         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 601         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 602         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 603         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 604         (OP_EX): Likewise.
 605
 606 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 607
 608         * i386-dis.c (XMScalar): New.
 609         (EXdScalar): Likewise.
 610         (EXqScalar): Likewise.
 611         (EXqScalarS): Likewise.
 612         (VexScalar): Likewise.
 613         (EXdVexScalarS): Likewise.
 614         (EXqVexScalarS): Likewise.
 615         (XMVexScalar): Likewise.
 616         (scalar_mode): Likewise.
 617         (d_scalar_mode): Likewise.
 618         (d_scalar_swap_mode): Likewise.
 619         (q_scalar_mode): Likewise.
 620         (q_scalar_swap_mode): Likewise.
 621         (vex_scalar_mode): Likewise.
 622         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 623         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 624         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 625         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 626         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 627         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 628         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 629         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 630         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 631         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 632         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 633         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 634         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 635         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 636         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 637         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 638         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 639         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 640         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 641         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 642         q_scalar_mode, q_scalar_swap_mode.
 643         (OP_XMM): Handle scalar_mode.
 644         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 645         and q_scalar_swap_mode.
 646         (OP_VEX): Handle vex_scalar_mode.
 647
 648 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 649
 650         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 651
 652 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 653
 654         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 655
 656 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 657
 658         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 659
 660 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 661
 662         * i386-dis.c (Bad_Opcode): New.
 663         (bad_opcode): Likewise.
 664         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 665         (dis386_twobyte): Likewise.
 666         (reg_table): Likewise.
 667         (prefix_table): Likewise.
 668         (x86_64_table): Likewise.
 669         (vex_len_table): Likewise.
 670         (vex_w_table): Likewise.
 671         (mod_table): Likewise.
 672         (rm_table): Likewise.
 673         (float_reg): Likewise.
 674         (reg_table): Remove trailing "(bad)" entries.
 675         (prefix_table): Likewise.
 676         (x86_64_table): Likewise.
 677         (vex_len_table): Likewise.
 678         (vex_w_table): Likewise.
 679         (mod_table): Likewise.
 680         (rm_table): Likewise.
 681         (get_valid_dis386): Handle bytemode 0.
 682
 683 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 684
 685         * i386-opc.h (VEXScalar): New.
 686
 687         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 688         instructions.
 689         * i386-tbl.h: Regenerated.
 690
 691 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 692
 693         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 694
 695         * i386-opc.tbl: Add xsave64 and xrstor64.
 696         * i386-tbl.h: Regenerated.
 697
 698 2010-01-20  Nick Clifton  <nickc@redhat.com>
 699
 700         PR 11170
 701         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 702         based post-indexed addressing.
 703
 704 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 705
 706         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 707         * i386-tbl.h: Regenerated.
 708
 709 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 712         comments.
 713
 714 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 715
 716         * i386-dis.c (names_mm): New.
 717         (intel_names_mm): Likewise.
 718         (att_names_mm): Likewise.
 719         (names_xmm): Likewise.
 720         (intel_names_xmm): Likewise.
 721         (att_names_xmm): Likewise.
 722         (names_ymm): Likewise.
 723         (intel_names_ymm): Likewise.
 724         (att_names_ymm): Likewise.
 725         (print_insn): Set names_mm, names_xmm and names_ymm.
 726         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 727         (OP_XMM): Likewise.
 728         (OP_EM): Likewise.
 729         (OP_EMC): Likewise.
 730         (OP_MXC): Likewise.
 731         (OP_EX): Likewise.
 732         (XMM_Fixup): Likewise.
 733         (OP_VEX): Likewise.
 734         (OP_EX_VexReg): Likewise.
 735         (OP_Vex_2src): Likewise.
 736         (OP_Vex_2src_1): Likewise.
 737         (OP_Vex_2src_2): Likewise.
 738         (OP_REG_VexI4): Likewise.
 739
 740 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 741
 742         * i386-dis.c (print_insn): Update comments.
 743
 744 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 745
 746         * i386-dis.c (rex_original): Removed.
 747         (ckprefix): Remove rex_original.
 748         (print_insn): Update comments.
 749
 750 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 751
 752         * Makefile.in: Regenerate.
 753         * configure: Regenerate.
 754
 755 2010-01-07  Doug Evans  <dje@sebabeach.org>
 756
 757         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 758         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 759         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 760         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 761         * xstormy16-ibld.c: Regenerate.
 762
 763 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 764
 765         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 766         * i386-init.h: Regenerated.
 767
 768 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 769
 770         * arm-dis.c (print_insn): Fixed search for next symbol and data
 771         dumping condition, and the initial mapping symbol state.
 772
 773 2010-01-05  Doug Evans  <dje@sebabeach.org>
 774
 775         * cgen-ibld.in: #include "cgen/basic-modes.h".
 776         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 777         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 778         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 779         * xstormy16-ibld.c: Regenerate.
 780
 781 2010-01-04  Nick Clifton  <nickc@redhat.com>
 782
 783         PR 11123
 784         * arm-dis.c (print_insn_coprocessor): Initialise value.
 785
 786 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 787
 788         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 789
 790 2010-01-02  Doug Evans  <dje@sebabeach.org>
 791
 792         * cgen-asm.in: Update copyright year.
 793         * cgen-dis.in: Update copyright year.
 794         * cgen-ibld.in: Update copyright year.
 795         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 796         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 797         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 798         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 799         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 800         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 801         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 802         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 803         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 804         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 805         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 806         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 807         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 808         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 809         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 810         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 811         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 812         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 813         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 814         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 815         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 816
 817 For older changes see ChangeLog-2009
 818 \f
 819 Local Variables:
 820 mode: change-log
 821 left-margin: 8
 822 fill-column: 74
 823 version-control: never
 824 End: