1 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
2 Renlin Li <renlin.li@arm.com>
4 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
5 (get_sym_code_type): Here.
7 2017-12-03 Alan Modra <amodra@gmail.com>
9 * ppc-opc.c (extract_li20): Rewrite.
11 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
13 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
14 (operand_value_powerpc): Update return and argument type.
15 <value, top>: Update type.
16 (skip_optional_operands): Update argument type.
17 (lookup_powerpc): Likewise.
18 (lookup_vle): Likewise.
19 <table_opcd, table_mask, insn2>: Update type.
20 (lookup_spe2): Update argument type.
21 <table_opcd, table_mask, insn2>: Update type.
22 (print_insn_powerpc) <insn, value>: Update type.
23 Use PPC_INT_FMT for printing instructions and operands.
24 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
25 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
26 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
27 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
28 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
29 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
30 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
31 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
32 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
33 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
34 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
35 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
36 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
37 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
38 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
39 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
40 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
41 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
42 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
43 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
44 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
45 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
46 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
47 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
48 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
49 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
50 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
51 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
52 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
53 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
54 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
55 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
56 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
57 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
58 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
59 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
60 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
62 2017-11-29 Jan Beulich <jbeulich@suse.com>
64 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
66 (output_cpu_flags): Update active_cpu_flags.
67 (process_i386_opcode_modifier): Update active_isstring.
68 (output_operand_type): Rename "macro" parameter to "stage",
70 (process_i386_operand_type): Likewise. Track presence of
71 BaseIndex and emit DispN accordingly.
72 (output_i386_opcode, process_i386_registers,
73 process_i386_initializers): Adjust calls to
74 process_i386_operand_type() for its changed parameter type.
75 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
76 all insns operands having BaseIndex set.
77 * i386-tbl.h: Re-generate.
79 2017-11-29 Jan Beulich <jbeulich@suse.com>
81 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
83 (operand_types): Remove Vec_Disp8 entry.
84 * i386-opc.h (Vec_Disp8): Delete.
85 (union i386_operand_type): Remove vec_disp8.
86 (i386-opc.tbl): Remove Vec_Disp8.
87 * i386-init.h, i386-tbl.h: Re-generate.
89 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
91 * po/Make-in (datadir): Define as @datadir@.
92 (localedir): Define as @localedir@.
93 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
95 2017-11-27 Nick Clifton <nickc@redhat.com>
97 * po/zh_CN.po: Updated simplified Chinese translation.
99 2017-11-24 Jan Beulich <jbeulich@suse.com>
101 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
104 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
106 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
107 * i386-tbl.h: Regenerate.
109 2017-11-23 Jan Beulich <jbeulich@suse.com>
111 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
112 the 16-bit addressing case.
114 2017-11-23 Jan Beulich <jbeulich@suse.com>
116 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
117 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
118 * i386-opc.tbl (ud1, ud2b): Add operands.
120 * i386-tbl.h: Re-generate.
122 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
124 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
125 * i386-tbl.h: Regenerate.
127 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
129 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
130 * i386-tbl.h: Regenerate.
132 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
134 *arc-opc (insert_rhv2): Check h-regs range.
136 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
138 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
139 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
141 2017-11-16 Tamar Christina <tamar.christina@arm.com>
143 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
144 and AARCH64_FEATURE_F16.
146 2017-11-16 Tamar Christina <tamar.christina@arm.com>
148 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
149 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
150 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
151 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
152 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
153 (ldapur, ldapursw, stlur): New.
154 * aarch64-dis-2.c: Regenerate.
156 2017-11-16 Jan Beulich <jbeulich@suse.com>
158 (get_valid_dis386): Never flag bad opcode when
159 vex.register_specifier is beyond 7. Always store all four
160 bits of it. Move 16-/32-bit override in EVEX handling after
161 all to be overridden bits have been set.
162 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
163 Use rex to determine GPR register set.
164 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
165 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
167 2017-11-15 Jan Beulich <jbeulich@suse.com>
169 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
170 determine GPR register set.
172 2017-11-15 Jan Beulich <jbeulich@suse.com>
174 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
175 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
176 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
178 (OP_REG_VexI4): Drop low 4 bits check.
180 2017-11-15 Jan Beulich <jbeulich@suse.com>
182 * i386-reg.tbl (axl): Remove Acc and Byte.
183 * i386-tbl.h: Re-generate.
185 2017-11-14 Jan Beulich <jbeulich@suse.com>
187 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
188 (vex_len_table): Use VPCOM.
190 2017-11-14 Jan Beulich <jbeulich@suse.com>
192 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
193 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
194 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
196 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
197 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
198 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
199 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
201 * i386-tbl.h: Re-generate.
203 2017-11-14 Jan Beulich <jbeulich@suse.com>
205 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
206 smov, ssca, stos, ssto, xlat): Drop Disp*.
207 * i386-tbl.h: Re-generate.
209 2017-11-13 Jan Beulich <jbeulich@suse.com>
211 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
212 xsaveopt64): Add No_qSuf.
213 * i386-tbl.h: Re-generate.
215 2017-11-09 Tamar Christina <tamar.christina@arm.com>
217 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
218 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
219 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
220 sder32_el2, vncr_el2.
221 (aarch64_sys_reg_supported_p): Likewise.
222 (aarch64_pstatefields): Add dit register.
223 (aarch64_pstatefield_supported_p): Likewise.
224 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
225 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
226 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
227 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
228 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
229 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
230 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
232 2017-11-09 Tamar Christina <tamar.christina@arm.com>
234 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
235 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
236 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
237 (QL_STLW, QL_STLX): New.
239 2017-11-09 Tamar Christina <tamar.christina@arm.com>
241 * aarch64-asm.h (ins_addr_offset): New.
242 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
243 (aarch64_ins_addr_offset): New.
244 * aarch64-asm-2.c: Regenerate.
245 * aarch64-dis.h (ext_addr_offset): New.
246 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
247 (aarch64_ext_addr_offset): New.
248 * aarch64-dis-2.c: Regenerate.
249 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
250 FLD_imm4_2 and FLD_SM3_imm2.
251 * aarch64-opc.c (fields): Add FLD_imm6_2,
252 FLD_imm4_2 and FLD_SM3_imm2.
253 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
254 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
255 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
256 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
258 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
260 2017-11-09 Tamar Christina <tamar.christina@arm.com>
263 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
264 (aarch64_feature_sm4, aarch64_feature_sha3): New.
265 (aarch64_feature_fp_16_v8_2): New.
266 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
267 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
268 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
270 2017-11-08 Tamar Christina <tamar.christina@arm.com>
272 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
273 (aarch64_feature_sha2, aarch64_feature_aes): New.
275 (AES_INSN, SHA2_INSN): New.
276 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
277 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
278 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
281 2017-11-08 Jiong Wang <jiong.wang@arm.com>
282 Tamar Christina <tamar.christina@arm.com>
284 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
285 FP16 instructions, including vfmal.f16 and vfmsl.f16.
287 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
289 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
291 2017-11-07 Alan Modra <amodra@gmail.com>
293 * opintl.h: Formatting, comment fixes.
294 (gettext, ngettext): Redefine when ENABLE_NLS.
295 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
296 (_): Define using gettext.
297 (textdomain, bindtextdomain): Use safer "do nothing".
299 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
301 * arc-dis.c (print_hex): New variable.
302 (parse_option): Check for hex option.
303 (print_insn_arc): Use hexadecimal representation for short
304 immediate values when requested.
305 (print_arc_disassembler_options): Add hex option to the list.
307 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
309 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
310 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
311 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
312 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
313 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
314 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
315 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
316 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
317 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
318 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
319 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
320 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
321 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
322 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
323 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
324 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
325 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
326 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
327 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
329 (prealloc, prefetch*): Place them before ld instruction.
330 * arc-opc.c (skip_this_opcode): Add ARITH class.
332 2017-10-25 Alan Modra <amodra@gmail.com>
335 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
336 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
337 (imm4flag, size_changed): Likewise.
338 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
339 (words, allWords, processing_argument_number): Likewise.
340 (cst4flag, size_changed): Likewise.
341 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
342 (crx_cst4_maps): Rename from cst4_maps.
343 (crx_no_op_insn): Rename from no_op_insn.
345 2017-10-24 Andrew Waterman <andrew@sifive.com>
347 * riscv-opc.c (match_c_addi16sp) : New function.
348 (match_c_addi4spn): New function.
349 (match_c_lui): Don't allow 0-immediate encodings.
350 (riscv_opcodes) <addi>: Use the above functions.
352 <c.addi4spn>: Likewise.
353 <c.addi16sp>: Likewise.
355 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
357 * i386-init.h: Regenerate
358 * i386-tbl.h: Likewise
360 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
362 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
363 (enum): Add EVEX_W_0F3854_P_2.
364 * i386-dis-evex.h (evex_table): Updated.
365 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
366 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
367 (cpu_flags): Add CpuAVX512_BITALG.
368 * i386-opc.h (enum): Add CpuAVX512_BITALG.
369 (i386_cpu_flags): Add cpuavx512_bitalg..
370 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
371 * i386-init.h: Regenerate.
372 * i386-tbl.h: Likewise.
374 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
376 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
377 * i386-dis-evex.h (evex_table): Updated.
378 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
379 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
380 (cpu_flags): Add CpuAVX512_VNNI.
381 * i386-opc.h (enum): Add CpuAVX512_VNNI.
382 (i386_cpu_flags): Add cpuavx512_vnni.
383 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
384 * i386-init.h: Regenerate.
385 * i386-tbl.h: Likewise.
387 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
389 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
390 (enum): Remove VEX_LEN_0F3A44_P_2.
391 (vex_len_table): Ditto.
392 (enum): Remove VEX_W_0F3A44_P_2.
393 (vew_w_table): Ditto.
394 (prefix_table): Adjust instructions (see prefixes above).
395 * i386-dis-evex.h (evex_table):
396 Add new instructions (see prefixes above).
397 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
398 (bitfield_cpu_flags): Ditto.
399 * i386-opc.h (enum): Ditto.
400 (i386_cpu_flags): Ditto.
401 (CpuUnused): Comment out to avoid zero-width field problem.
402 * i386-opc.tbl (vpclmulqdq): New instruction.
403 * i386-init.h: Regenerate.
406 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
408 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
409 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
410 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
411 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
412 (vex_len_table): Ditto.
413 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
414 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
415 (vew_w_table): Ditto.
416 (prefix_table): Adjust instructions (see prefixes above).
417 * i386-dis-evex.h (evex_table):
418 Add new instructions (see prefixes above).
419 * i386-gen.c (cpu_flag_init): Add VAES.
420 (bitfield_cpu_flags): Ditto.
421 * i386-opc.h (enum): Ditto.
422 (i386_cpu_flags): Ditto.
423 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
424 * i386-init.h: Regenerate.
427 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
429 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
430 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
431 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
432 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
433 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
434 (prefix_table): Updated (see prefixes above).
435 (three_byte_table): Likewise.
436 (vex_w_table): Likewise.
437 * i386-dis-evex.h: Likewise.
438 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
439 (cpu_flags): Add CpuGFNI.
440 * i386-opc.h (enum): Add CpuGFNI.
441 (i386_cpu_flags): Add cpugfni.
442 * i386-opc.tbl: Add Intel GFNI instructions.
443 * i386-init.h: Regenerate.
444 * i386-tbl.h: Likewise.
446 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
448 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
449 Define EXbScalar and EXwScalar for OP_EX.
450 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
451 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
452 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
453 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
454 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
455 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
456 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
457 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
458 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
459 (OP_E_memory): Likewise.
460 * i386-dis-evex.h: Updated.
461 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
462 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
463 (cpu_flags): Add CpuAVX512_VBMI2.
464 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
465 (i386_cpu_flags): Add cpuavx512_vbmi2.
466 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
467 * i386-init.h: Regenerate.
468 * i386-tbl.h: Likewise.
470 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
472 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
474 2017-10-12 James Bowman <james.bowman@ftdichip.com>
476 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
477 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
478 K15. Add jmpix pattern.
480 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
482 * s390-opc.txt (prno, tpei, irbm): New instructions added.
484 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
486 * s390-opc.c (INSTR_SI_RD): New macro.
487 (INSTR_S_RD): Adjust example instruction.
488 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
491 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
493 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
494 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
495 VLE multimple load/store instructions. Old e_ldm* variants are
497 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
499 2017-09-27 Nick Clifton <nickc@redhat.com>
502 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
503 names for the fmv.x.s and fmv.s.x instructions respectively.
505 2017-09-26 do <do@nerilex.org>
508 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
509 be used on CPUs that have emacs support.
511 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
513 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
515 2017-09-09 Kamil Rytarowski <n54@gmx.com>
517 * nds32-asm.c: Rename __BIT() to N32_BIT().
518 * nds32-asm.h: Likewise.
519 * nds32-dis.c: Likewise.
521 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
523 * i386-dis.c (last_active_prefix): Removed.
524 (ckprefix): Don't set last_active_prefix.
525 (NOTRACK_Fixup): Don't check last_active_prefix.
527 2017-08-31 Nick Clifton <nickc@redhat.com>
529 * po/fr.po: Updated French translation.
531 2017-08-31 James Bowman <james.bowman@ftdichip.com>
533 * ft32-dis.c (print_insn_ft32): Correct display of non-address
536 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
537 Edmar Wienskoski <edmar.wienskoski@nxp.com>
539 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
540 PPC_OPCODE_EFS2 flag to "e200z4" entry.
541 New entries efs2 and spe2.
542 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
543 (SPE2_OPCD_SEGS): New macro.
544 (spe2_opcd_indices): New.
545 (disassemble_init_powerpc): Handle SPE2 opcodes.
546 (lookup_spe2): New function.
547 (print_insn_powerpc): call lookup_spe2.
548 * ppc-opc.c (insert_evuimm1_ex0): New function.
549 (extract_evuimm1_ex0): Likewise.
550 (insert_evuimm_lt8): Likewise.
551 (extract_evuimm_lt8): Likewise.
552 (insert_off_spe2): Likewise.
553 (extract_off_spe2): Likewise.
554 (insert_Ddd): Likewise.
555 (extract_Ddd): Likewise.
557 (EVUIMM_LT8): Likewise.
558 (EVUIMM_LT16): Adjust.
560 (EVUIMM_1): Likewise.
561 (EVUIMM_1_EX0): Likewise.
564 (VX_OFF_SPE2): Likewise.
567 (VX_MASK_DDD): New mask.
569 (VX_RA_CONST): New macro.
570 (VX_RA_CONST_MASK): Likewise.
571 (VX_RB_CONST): Likewise.
572 (VX_RB_CONST_MASK): Likewise.
573 (VX_OFF_SPE2_MASK): Likewise.
574 (VX_SPE_CRFD): Likewise.
575 (VX_SPE_CRFD_MASK VX): Likewise.
576 (VX_SPE2_CLR): Likewise.
577 (VX_SPE2_CLR_MASK): Likewise.
578 (VX_SPE2_SPLATB): Likewise.
579 (VX_SPE2_SPLATB_MASK): Likewise.
580 (VX_SPE2_OCTET): Likewise.
581 (VX_SPE2_OCTET_MASK): Likewise.
582 (VX_SPE2_DDHH): Likewise.
583 (VX_SPE2_DDHH_MASK): Likewise.
584 (VX_SPE2_HH): Likewise.
585 (VX_SPE2_HH_MASK): Likewise.
586 (VX_SPE2_EVMAR): Likewise.
587 (VX_SPE2_EVMAR_MASK): Likewise.
590 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
591 (powerpc_macros): Map old SPE instructions have new names
592 with the same opcodes. Add SPE2 instructions which just are
594 (spe2_opcodes): Add SPE2 opcodes.
596 2017-08-23 Alan Modra <amodra@gmail.com>
598 * ppc-opc.c: Formatting and comment fixes. Move insert and
599 extract functions earlier, deleting forward declarations.
600 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
603 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
605 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
607 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
608 Edmar Wienskoski <edmar.wienskoski@nxp.com>
610 * ppc-opc.c (insert_evuimm2_ex0): New function.
611 (extract_evuimm2_ex0): Likewise.
612 (insert_evuimm4_ex0): Likewise.
613 (extract_evuimm4_ex0): Likewise.
614 (insert_evuimm8_ex0): Likewise.
615 (extract_evuimm8_ex0): Likewise.
616 (insert_evuimm_lt16): Likewise.
617 (extract_evuimm_lt16): Likewise.
618 (insert_rD_rS_even): Likewise.
619 (extract_rD_rS_even): Likewise.
620 (insert_off_lsp): Likewise.
621 (extract_off_lsp): Likewise.
622 (RD_EVEN): New operand.
625 (EVUIMM_LT16): New operand.
627 (EVUIMM_2_EX0): New operand.
629 (EVUIMM_4_EX0): New operand.
631 (EVUIMM_8_EX0): New operand.
633 (VX_OFF): New operand.
635 (VX_LSP_MASK): Likewise.
636 (VX_LSP_OFF_MASK): Likewise.
637 (PPC_OPCODE_LSP): Likewise.
638 (vle_opcodes): Add LSP opcodes.
639 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
641 2017-08-09 Jiong Wang <jiong.wang@arm.com>
643 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
644 register operands in CRC instructions.
645 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
648 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
650 * disassemble.c (disassembler): Mark big and mach with
653 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
655 * disassemble.c (disassembler): Remove arch/mach/endian
658 2017-07-25 Nick Clifton <nickc@redhat.com>
661 * arc-opc.c (insert_rhv2): Use lower case first letter in error
663 (insert_r0): Likewise.
664 (insert_r1): Likewise.
665 (insert_r2): Likewise.
666 (insert_r3): Likewise.
667 (insert_sp): Likewise.
668 (insert_gp): Likewise.
669 (insert_pcl): Likewise.
670 (insert_blink): Likewise.
671 (insert_ilink1): Likewise.
672 (insert_ilink2): Likewise.
673 (insert_ras): Likewise.
674 (insert_rbs): Likewise.
675 (insert_rcs): Likewise.
676 (insert_simm3s): Likewise.
677 (insert_rrange): Likewise.
678 (insert_r13el): Likewise.
679 (insert_fpel): Likewise.
680 (insert_blinkel): Likewise.
681 (insert_pclel): Likewise.
682 (insert_nps_bitop_size_2b): Likewise.
683 (insert_nps_imm_offset): Likewise.
684 (insert_nps_imm_entry): Likewise.
685 (insert_nps_size_16bit): Likewise.
686 (insert_nps_##NAME##_pos): Likewise.
687 (insert_nps_##NAME): Likewise.
688 (insert_nps_bitop_ins_ext): Likewise.
689 (insert_nps_##NAME): Likewise.
690 (insert_nps_min_hofs): Likewise.
691 (insert_nps_##NAME): Likewise.
692 (insert_nps_rbdouble_64): Likewise.
693 (insert_nps_misc_imm_offset): Likewise.
694 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
697 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
698 Jiong Wang <jiong.wang@arm.com>
700 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
702 * aarch64-dis-2.c: Regenerated.
704 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
706 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
709 2017-07-20 Nick Clifton <nickc@redhat.com>
711 * po/de.po: Updated German translation.
713 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
715 * arc-regs.h (sec_stat): New aux register.
716 (aux_kernel_sp): Likewise.
717 (aux_sec_u_sp): Likewise.
718 (aux_sec_k_sp): Likewise.
719 (sec_vecbase_build): Likewise.
720 (nsc_table_top): Likewise.
721 (nsc_table_base): Likewise.
722 (ersec_stat): Likewise.
723 (aux_sec_except): Likewise.
725 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
727 * arc-opc.c (extract_uimm12_20): New function.
728 (UIMM12_20): New operand.
730 * arc-tbl.h (sjli): Add new instruction.
732 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
733 John Eric Martin <John.Martin@emmicro-us.com>
735 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
736 (UIMM3_23): Adjust accordingly.
737 * arc-regs.h: Add/correct jli_base register.
738 * arc-tbl.h (jli_s): Likewise.
740 2017-07-18 Nick Clifton <nickc@redhat.com>
743 * aarch64-opc.c: Fix spelling typos.
744 * i386-dis.c: Likewise.
746 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
748 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
749 max_addr_offset and octets variables to size_t.
751 2017-07-12 Alan Modra <amodra@gmail.com>
753 * po/da.po: Update from translationproject.org/latest/opcodes/.
754 * po/de.po: Likewise.
755 * po/es.po: Likewise.
756 * po/fi.po: Likewise.
757 * po/fr.po: Likewise.
758 * po/id.po: Likewise.
759 * po/it.po: Likewise.
760 * po/nl.po: Likewise.
761 * po/pt_BR.po: Likewise.
762 * po/ro.po: Likewise.
763 * po/sv.po: Likewise.
764 * po/tr.po: Likewise.
765 * po/uk.po: Likewise.
766 * po/vi.po: Likewise.
767 * po/zh_CN.po: Likewise.
769 2017-07-11 Yao Qi <yao.qi@linaro.org>
770 Alan Modra <amodra@gmail.com>
772 * cgen.sh: Mark generated files read-only.
773 * epiphany-asm.c: Regenerate.
774 * epiphany-desc.c: Regenerate.
775 * epiphany-desc.h: Regenerate.
776 * epiphany-dis.c: Regenerate.
777 * epiphany-ibld.c: Regenerate.
778 * epiphany-opc.c: Regenerate.
779 * epiphany-opc.h: Regenerate.
780 * fr30-asm.c: Regenerate.
781 * fr30-desc.c: Regenerate.
782 * fr30-desc.h: Regenerate.
783 * fr30-dis.c: Regenerate.
784 * fr30-ibld.c: Regenerate.
785 * fr30-opc.c: Regenerate.
786 * fr30-opc.h: Regenerate.
787 * frv-asm.c: Regenerate.
788 * frv-desc.c: Regenerate.
789 * frv-desc.h: Regenerate.
790 * frv-dis.c: Regenerate.
791 * frv-ibld.c: Regenerate.
792 * frv-opc.c: Regenerate.
793 * frv-opc.h: Regenerate.
794 * ip2k-asm.c: Regenerate.
795 * ip2k-desc.c: Regenerate.
796 * ip2k-desc.h: Regenerate.
797 * ip2k-dis.c: Regenerate.
798 * ip2k-ibld.c: Regenerate.
799 * ip2k-opc.c: Regenerate.
800 * ip2k-opc.h: Regenerate.
801 * iq2000-asm.c: Regenerate.
802 * iq2000-desc.c: Regenerate.
803 * iq2000-desc.h: Regenerate.
804 * iq2000-dis.c: Regenerate.
805 * iq2000-ibld.c: Regenerate.
806 * iq2000-opc.c: Regenerate.
807 * iq2000-opc.h: Regenerate.
808 * lm32-asm.c: Regenerate.
809 * lm32-desc.c: Regenerate.
810 * lm32-desc.h: Regenerate.
811 * lm32-dis.c: Regenerate.
812 * lm32-ibld.c: Regenerate.
813 * lm32-opc.c: Regenerate.
814 * lm32-opc.h: Regenerate.
815 * lm32-opinst.c: Regenerate.
816 * m32c-asm.c: Regenerate.
817 * m32c-desc.c: Regenerate.
818 * m32c-desc.h: Regenerate.
819 * m32c-dis.c: Regenerate.
820 * m32c-ibld.c: Regenerate.
821 * m32c-opc.c: Regenerate.
822 * m32c-opc.h: Regenerate.
823 * m32r-asm.c: Regenerate.
824 * m32r-desc.c: Regenerate.
825 * m32r-desc.h: Regenerate.
826 * m32r-dis.c: Regenerate.
827 * m32r-ibld.c: Regenerate.
828 * m32r-opc.c: Regenerate.
829 * m32r-opc.h: Regenerate.
830 * m32r-opinst.c: Regenerate.
831 * mep-asm.c: Regenerate.
832 * mep-desc.c: Regenerate.
833 * mep-desc.h: Regenerate.
834 * mep-dis.c: Regenerate.
835 * mep-ibld.c: Regenerate.
836 * mep-opc.c: Regenerate.
837 * mep-opc.h: Regenerate.
838 * mt-asm.c: Regenerate.
839 * mt-desc.c: Regenerate.
840 * mt-desc.h: Regenerate.
841 * mt-dis.c: Regenerate.
842 * mt-ibld.c: Regenerate.
843 * mt-opc.c: Regenerate.
844 * mt-opc.h: Regenerate.
845 * or1k-asm.c: Regenerate.
846 * or1k-desc.c: Regenerate.
847 * or1k-desc.h: Regenerate.
848 * or1k-dis.c: Regenerate.
849 * or1k-ibld.c: Regenerate.
850 * or1k-opc.c: Regenerate.
851 * or1k-opc.h: Regenerate.
852 * or1k-opinst.c: Regenerate.
853 * xc16x-asm.c: Regenerate.
854 * xc16x-desc.c: Regenerate.
855 * xc16x-desc.h: Regenerate.
856 * xc16x-dis.c: Regenerate.
857 * xc16x-ibld.c: Regenerate.
858 * xc16x-opc.c: Regenerate.
859 * xc16x-opc.h: Regenerate.
860 * xstormy16-asm.c: Regenerate.
861 * xstormy16-desc.c: Regenerate.
862 * xstormy16-desc.h: Regenerate.
863 * xstormy16-dis.c: Regenerate.
864 * xstormy16-ibld.c: Regenerate.
865 * xstormy16-opc.c: Regenerate.
866 * xstormy16-opc.h: Regenerate.
868 2017-07-07 Alan Modra <amodra@gmail.com>
870 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
871 * m32c-dis.c: Regenerate.
872 * mep-dis.c: Regenerate.
874 2017-07-05 Borislav Petkov <bp@suse.de>
876 * i386-dis.c: Enable ModRM.reg /6 aliases.
878 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
880 * opcodes/arm-dis.c: Support MVFR2 in disassembly
883 2017-07-04 Tristan Gingold <gingold@adacore.com>
885 * configure: Regenerate.
887 2017-07-03 Tristan Gingold <gingold@adacore.com>
889 * po/opcodes.pot: Regenerate.
891 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
893 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
894 entries to the MSA ASE instruction block.
896 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
897 Maciej W. Rozycki <macro@imgtec.com>
899 * micromips-opc.c (XPA, XPAVZ): New macros.
900 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
903 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
904 Maciej W. Rozycki <macro@imgtec.com>
906 * micromips-opc.c (I36): New macro.
907 (micromips_opcodes): Add "eretnc".
909 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
910 Andrew Bennett <andrew.bennett@imgtec.com>
912 * mips-dis.c (mips_calculate_combination_ases): Handle the
914 (parse_mips_ase_option): New function.
915 (parse_mips_dis_option): Factor out ASE option handling to the
916 new function. Call `mips_calculate_combination_ases'.
917 * mips-opc.c (XPAVZ): New macro.
918 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
919 "mfhgc0", "mthc0" and "mthgc0".
921 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
923 * mips-dis.c (mips_calculate_combination_ases): New function.
924 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
925 calculation to the new function.
926 (set_default_mips_dis_options): Call the new function.
928 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
930 * arc-dis.c (parse_disassembler_options): Use
931 FOR_EACH_DISASSEMBLER_OPTION.
933 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
935 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
936 disassembler option strings.
937 (parse_cpu_option): Likewise.
939 2017-06-28 Tamar Christina <tamar.christina@arm.com>
941 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
942 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
943 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
944 (aarch64_feature_dotprod, DOT_INSN): New.
946 * aarch64-dis-2.c: Regenerated.
948 2017-06-28 Jiong Wang <jiong.wang@arm.com>
950 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
952 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
953 Matthew Fortune <matthew.fortune@imgtec.com>
954 Andrew Bennett <andrew.bennett@imgtec.com>
956 * mips-formats.h (INT_BIAS): New macro.
957 (INT_ADJ): Redefine in INT_BIAS terms.
958 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
959 (mips_print_save_restore): New function.
960 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
961 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
963 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
964 (print_mips16_insn_arg): Call `mips_print_save_restore' for
965 OP_SAVE_RESTORE_LIST handling, factored out from here.
966 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
967 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
968 (mips_builtin_opcodes): Add "restore" and "save" entries.
969 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
971 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
973 2017-06-23 Andrew Waterman <andrew@sifive.com>
975 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
976 alias; do not mark SLTI instruction as an alias.
978 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
980 * i386-dis.c (RM_0FAE_REG_5): Removed.
981 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
982 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
983 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
984 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
985 PREFIX_MOD_3_0F01_REG_5_RM_0.
986 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
987 PREFIX_MOD_3_0FAE_REG_5.
988 (mod_table): Update MOD_0FAE_REG_5.
989 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
990 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
991 * i386-tbl.h: Regenerated.
993 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
995 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
996 * i386-opc.tbl: Likewise.
997 * i386-tbl.h: Regenerated.
999 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1001 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1003 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1006 2017-06-19 Nick Clifton <nickc@redhat.com>
1009 * score-dis.c (score_opcodes): Add sentinel.
1011 2017-06-16 Alan Modra <amodra@gmail.com>
1013 * rx-decode.c: Regenerate.
1015 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1018 * i386-dis.c (OP_E_register): Check valid bnd register.
1021 2017-06-15 Nick Clifton <nickc@redhat.com>
1024 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1027 2017-06-15 Nick Clifton <nickc@redhat.com>
1030 * rl78-decode.opc (OP_BUF_LEN): Define.
1031 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1032 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1034 * rl78-decode.c: Regenerate.
1036 2017-06-15 Nick Clifton <nickc@redhat.com>
1039 * bfin-dis.c (gregs): Clip index to prevent overflow.
1041 (regs_lo): Likewise.
1042 (regs_hi): Likewise.
1044 2017-06-14 Nick Clifton <nickc@redhat.com>
1047 * score7-dis.c (score_opcodes): Add sentinel.
1049 2017-06-14 Yao Qi <yao.qi@linaro.org>
1051 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1052 * arm-dis.c: Likewise.
1053 * ia64-dis.c: Likewise.
1054 * mips-dis.c: Likewise.
1055 * spu-dis.c: Likewise.
1056 * disassemble.h (print_insn_aarch64): New declaration, moved from
1058 (print_insn_big_arm, print_insn_big_mips): Likewise.
1059 (print_insn_i386, print_insn_ia64): Likewise.
1060 (print_insn_little_arm, print_insn_little_mips): Likewise.
1062 2017-06-14 Nick Clifton <nickc@redhat.com>
1065 * rx-decode.opc: Include libiberty.h
1066 (GET_SCALE): New macro - validates access to SCALE array.
1067 (GET_PSCALE): New macro - validates access to PSCALE array.
1068 (DIs, SIs, S2Is, rx_disp): Use new macros.
1069 * rx-decode.c: Regenerate.
1071 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1073 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1075 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1077 * arc-dis.c (enforced_isa_mask): Declare.
1078 (cpu_types): Likewise.
1079 (parse_cpu_option): New function.
1080 (parse_disassembler_options): Use it.
1081 (print_insn_arc): Use enforced_isa_mask.
1082 (print_arc_disassembler_options): Document new options.
1084 2017-05-24 Yao Qi <yao.qi@linaro.org>
1086 * alpha-dis.c: Include disassemble.h, don't include
1088 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1089 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1090 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1091 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1092 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1093 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1094 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1095 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1096 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1097 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1098 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1099 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1100 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1101 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1102 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1103 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1104 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1105 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1106 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1107 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1108 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1109 * z80-dis.c, z8k-dis.c: Likewise.
1110 * disassemble.h: New file.
1112 2017-05-24 Yao Qi <yao.qi@linaro.org>
1114 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1115 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1117 2017-05-24 Yao Qi <yao.qi@linaro.org>
1119 * disassemble.c (disassembler): Add arguments a, big and mach.
1122 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1124 * i386-dis.c (NOTRACK_Fixup): New.
1125 (NOTRACK): Likewise.
1126 (NOTRACK_PREFIX): Likewise.
1127 (last_active_prefix): Likewise.
1128 (reg_table): Use NOTRACK on indirect call and jmp.
1129 (ckprefix): Set last_active_prefix.
1130 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1131 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1132 * i386-opc.h (NoTrackPrefixOk): New.
1133 (i386_opcode_modifier): Add notrackprefixok.
1134 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1136 * i386-tbl.h: Regenerated.
1138 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1140 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1142 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1143 bfd_mach_sparc_v9m8.
1144 (print_insn_sparc): Handle new operand types.
1145 * sparc-opc.c (MASK_M8): Define.
1147 (v6notlet): Likewise.
1158 (v9andleon): Likewise.
1161 (HWS2_VM8): Likewise.
1162 (sparc_opcode_archs): Add entry for "m8".
1163 (sparc_opcodes): Add OSA2017 and M8 instructions
1164 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1166 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1167 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1168 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1169 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1170 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1171 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1172 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1173 ASI_CORE_SELECT_COMMIT_NHT.
1175 2017-05-18 Alan Modra <amodra@gmail.com>
1177 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1178 * aarch64-dis.c: Likewise.
1179 * aarch64-gen.c: Likewise.
1180 * aarch64-opc.c: Likewise.
1182 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1183 Matthew Fortune <matthew.fortune@imgtec.com>
1185 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1186 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1187 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1188 (print_insn_arg) <OP_REG28>: Add handler.
1189 (validate_insn_args) <OP_REG28>: Handle.
1190 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1191 32-bit encoding and 9-bit immediates.
1192 (print_insn_mips16): Handle MIPS16 instructions that require
1193 32-bit encoding and MFC0/MTC0 operand decoding.
1194 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1195 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1196 (RD_C0, WR_C0, E2, E2MT): New macros.
1197 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1198 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1199 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1200 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1201 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1202 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1203 instructions, "swl", "swr", "sync" and its "sync_acquire",
1204 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1205 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1206 regular/extended entries for original MIPS16 ISA revision
1207 instructions whose extended forms are subdecoded in the MIPS16e2
1208 ISA revision: "li", "sll" and "srl".
1210 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1212 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1213 reference in CP0 move operand decoding.
1215 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1217 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1218 type to hexadecimal.
1219 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1221 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1223 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1224 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1225 "sync_rmb" and "sync_wmb" as aliases.
1226 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1227 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1229 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1231 * arc-dis.c (parse_option): Update quarkse_em option..
1232 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1234 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1236 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1238 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1240 2017-05-01 Michael Clark <michaeljclark@mac.com>
1242 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1245 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1247 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1248 and branches and not synthetic data instructions.
1250 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1252 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1254 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1256 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1257 * arc-opc.c (insert_r13el): New function.
1259 * arc-tbl.h: Add new enter/leave variants.
1261 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1263 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1265 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1267 * mips-dis.c (print_mips_disassembler_options): Add
1270 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1272 * mips16-opc.c (AL): New macro.
1273 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1274 of "ld" and "lw" as aliases.
1276 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1278 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1281 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1282 Alan Modra <amodra@gmail.com>
1284 * ppc-opc.c (ELEV): Define.
1285 (vle_opcodes): Add se_rfgi and e_sc.
1286 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1289 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1291 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1293 2017-04-21 Nick Clifton <nickc@redhat.com>
1296 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1299 2017-04-13 Alan Modra <amodra@gmail.com>
1301 * epiphany-desc.c: Regenerate.
1302 * fr30-desc.c: Regenerate.
1303 * frv-desc.c: Regenerate.
1304 * ip2k-desc.c: Regenerate.
1305 * iq2000-desc.c: Regenerate.
1306 * lm32-desc.c: Regenerate.
1307 * m32c-desc.c: Regenerate.
1308 * m32r-desc.c: Regenerate.
1309 * mep-desc.c: Regenerate.
1310 * mt-desc.c: Regenerate.
1311 * or1k-desc.c: Regenerate.
1312 * xc16x-desc.c: Regenerate.
1313 * xstormy16-desc.c: Regenerate.
1315 2017-04-11 Alan Modra <amodra@gmail.com>
1317 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1318 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1319 PPC_OPCODE_TMR for e6500.
1320 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1321 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1322 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1323 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1324 (PPCHTM): Define as PPC_OPCODE_POWER8.
1325 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1327 2017-04-10 Alan Modra <amodra@gmail.com>
1329 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1330 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1331 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1332 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1334 2017-04-09 Pip Cet <pipcet@gmail.com>
1336 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1337 appropriate floating-point precision directly.
1339 2017-04-07 Alan Modra <amodra@gmail.com>
1341 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1342 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1343 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1344 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1345 vector instructions with E6500 not PPCVEC2.
1347 2017-04-06 Pip Cet <pipcet@gmail.com>
1349 * Makefile.am: Add wasm32-dis.c.
1350 * configure.ac: Add wasm32-dis.c to wasm32 target.
1351 * disassemble.c: Add wasm32 disassembler code.
1352 * wasm32-dis.c: New file.
1353 * Makefile.in: Regenerate.
1354 * configure: Regenerate.
1355 * po/POTFILES.in: Regenerate.
1356 * po/opcodes.pot: Regenerate.
1358 2017-04-05 Pedro Alves <palves@redhat.com>
1360 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1361 * arm-dis.c (parse_arm_disassembler_options): Constify.
1362 * ppc-dis.c (powerpc_init_dialect): Constify local.
1363 * vax-dis.c (parse_disassembler_options): Constify.
1365 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1367 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1370 2017-03-30 Pip Cet <pipcet@gmail.com>
1372 * configure.ac: Add (empty) bfd_wasm32_arch target.
1373 * configure: Regenerate
1374 * po/opcodes.pot: Regenerate.
1376 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1378 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1380 * opcodes/sparc-opc.c (asi_table): New ASIs.
1382 2017-03-29 Alan Modra <amodra@gmail.com>
1384 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1386 (lookup_powerpc): Don't special case -1 dialect. Handle
1388 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1389 lookup_powerpc call, pass it on second.
1391 2017-03-27 Alan Modra <amodra@gmail.com>
1394 * ppc-dis.c (struct ppc_mopt): Comment.
1395 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1397 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1399 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1400 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1401 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1402 (insert_nps_misc_imm_offset): New function.
1403 (extract_nps_misc imm_offset): New function.
1404 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1405 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1407 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1409 * s390-mkopc.c (main): Remove vx2 check.
1410 * s390-opc.txt: Remove vx2 instruction flags.
1412 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1414 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1415 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1416 (insert_nps_imm_offset): New function.
1417 (extract_nps_imm_offset): New function.
1418 (insert_nps_imm_entry): New function.
1419 (extract_nps_imm_entry): New function.
1421 2017-03-17 Alan Modra <amodra@gmail.com>
1424 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1425 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1426 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1428 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1430 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1434 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1436 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1438 2017-03-13 Andrew Waterman <andrew@sifive.com>
1440 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1445 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1447 * i386-gen.c (opcode_modifiers): Replace S with Load.
1448 * i386-opc.h (S): Removed.
1450 (i386_opcode_modifier): Replace s with load.
1451 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1452 and {evex}. Replace S with Load.
1453 * i386-tbl.h: Regenerated.
1455 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1457 * i386-opc.tbl: Use CpuCET on rdsspq.
1458 * i386-tbl.h: Regenerated.
1460 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1462 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1463 <vsx>: Do not use PPC_OPCODE_VSX3;
1465 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1467 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1469 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1471 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1472 (MOD_0F1E_PREFIX_1): Likewise.
1473 (MOD_0F38F5_PREFIX_2): Likewise.
1474 (MOD_0F38F6_PREFIX_0): Likewise.
1475 (RM_0F1E_MOD_3_REG_7): Likewise.
1476 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1477 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1478 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1479 (PREFIX_0F1E): Likewise.
1480 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1481 (PREFIX_0F38F5): Likewise.
1482 (dis386_twobyte): Use PREFIX_0F1E.
1483 (reg_table): Add REG_0F1E_MOD_3.
1484 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1485 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1486 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1487 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1488 (three_byte_table): Use PREFIX_0F38F5.
1489 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1490 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1491 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1492 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1493 PREFIX_MOD_3_0F01_REG_5_RM_2.
1494 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1495 (cpu_flags): Add CpuCET.
1496 * i386-opc.h (CpuCET): New enum.
1497 (CpuUnused): Commented out.
1498 (i386_cpu_flags): Add cpucet.
1499 * i386-opc.tbl: Add Intel CET instructions.
1500 * i386-init.h: Regenerated.
1501 * i386-tbl.h: Likewise.
1503 2017-03-06 Alan Modra <amodra@gmail.com>
1506 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1507 (extract_raq, extract_ras, extract_rbx): New functions.
1508 (powerpc_operands): Use opposite corresponding insert function.
1510 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1511 register restriction.
1513 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1515 * disassemble.c Include "safe-ctype.h".
1516 (disassemble_init_for_target): Handle s390 init.
1517 (remove_whitespace_and_extra_commas): New function.
1518 (disassembler_options_cmp): Likewise.
1519 * arm-dis.c: Include "libiberty.h".
1521 (regnames): Use long disassembler style names.
1522 Add force-thumb and no-force-thumb options.
1523 (NUM_ARM_REGNAMES): Rename from this...
1524 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1525 (get_arm_regname_num_options): Delete.
1526 (set_arm_regname_option): Likewise.
1527 (get_arm_regnames): Likewise.
1528 (parse_disassembler_options): Likewise.
1529 (parse_arm_disassembler_option): Rename from this...
1530 (parse_arm_disassembler_options): ...to this. Make static.
1531 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1532 (print_insn): Use parse_arm_disassembler_options.
1533 (disassembler_options_arm): New function.
1534 (print_arm_disassembler_options): Handle updated regnames.
1535 * ppc-dis.c: Include "libiberty.h".
1536 (ppc_opts): Add "32" and "64" entries.
1537 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1538 (powerpc_init_dialect): Add break to switch statement.
1539 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1540 (disassembler_options_powerpc): New function.
1541 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1542 Remove printing of "32" and "64".
1543 * s390-dis.c: Include "libiberty.h".
1544 (init_flag): Remove unneeded variable.
1545 (struct s390_options_t): New structure type.
1546 (options): New structure.
1547 (init_disasm): Rename from this...
1548 (disassemble_init_s390): ...to this. Add initializations for
1549 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1550 (print_insn_s390): Delete call to init_disasm.
1551 (disassembler_options_s390): New function.
1552 (print_s390_disassembler_options): Print using information from
1554 * po/opcodes.pot: Regenerate.
1556 2017-02-28 Jan Beulich <jbeulich@suse.com>
1558 * i386-dis.c (PCMPESTR_Fixup): New.
1559 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1560 (prefix_table): Use PCMPESTR_Fixup.
1561 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1563 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1564 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1565 Split 64-bit and non-64-bit variants.
1566 * opcodes/i386-tbl.h: Re-generate.
1568 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1570 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1571 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1572 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1573 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1574 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1575 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1576 (OP_SVE_V_HSD): New macros.
1577 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1578 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1579 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1580 (aarch64_opcode_table): Add new SVE instructions.
1581 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1582 for rotation operands. Add new SVE operands.
1583 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1584 (ins_sve_quad_index): Likewise.
1585 (ins_imm_rotate): Split into...
1586 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1587 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1588 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1590 (aarch64_ins_sve_addr_ri_s4): New function.
1591 (aarch64_ins_sve_quad_index): Likewise.
1592 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1593 * aarch64-asm-2.c: Regenerate.
1594 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1595 (ext_sve_quad_index): Likewise.
1596 (ext_imm_rotate): Split into...
1597 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1598 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1599 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1601 (aarch64_ext_sve_addr_ri_s4): New function.
1602 (aarch64_ext_sve_quad_index): Likewise.
1603 (aarch64_ext_sve_index): Allow quad indices.
1604 (do_misc_decoding): Likewise.
1605 * aarch64-dis-2.c: Regenerate.
1606 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1607 aarch64_field_kinds.
1608 (OPD_F_OD_MASK): Widen by one bit.
1609 (OPD_F_NO_ZR): Bump accordingly.
1610 (get_operand_field_width): New function.
1611 * aarch64-opc.c (fields): Add new SVE fields.
1612 (operand_general_constraint_met_p): Handle new SVE operands.
1613 (aarch64_print_operand): Likewise.
1614 * aarch64-opc-2.c: Regenerate.
1616 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1618 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1619 (aarch64_feature_compnum): ...this.
1620 (SIMD_V8_3): Replace with...
1622 (CNUM_INSN): New macro.
1623 (aarch64_opcode_table): Use it for the complex number instructions.
1625 2017-02-24 Jan Beulich <jbeulich@suse.com>
1627 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1629 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1631 Add support for associating SPARC ASIs with an architecture level.
1632 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1633 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1634 decoding of SPARC ASIs.
1636 2017-02-23 Jan Beulich <jbeulich@suse.com>
1638 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1639 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1641 2017-02-21 Jan Beulich <jbeulich@suse.com>
1643 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1644 1 (instead of to itself). Correct typo.
1646 2017-02-14 Andrew Waterman <andrew@sifive.com>
1648 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1651 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1653 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1654 (aarch64_sys_reg_supported_p): Handle them.
1656 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1658 * arc-opc.c (UIMM6_20R): Define.
1659 (SIMM12_20): Use above.
1660 (SIMM12_20R): Define.
1661 (SIMM3_5_S): Use above.
1662 (UIMM7_A32_11R_S): Define.
1663 (UIMM7_9_S): Use above.
1664 (UIMM3_13R_S): Define.
1665 (SIMM11_A32_7_S): Use above.
1667 (UIMM10_A32_8_S): Use above.
1668 (UIMM8_8R_S): Define.
1670 (arc_relax_opcodes): Use all above defines.
1672 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1674 * arc-regs.h: Distinguish some of the registers different on
1675 ARC700 and HS38 cpus.
1677 2017-02-14 Alan Modra <amodra@gmail.com>
1680 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1681 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1683 2017-02-11 Stafford Horne <shorne@gmail.com>
1684 Alan Modra <amodra@gmail.com>
1686 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1687 Use insn_bytes_value and insn_int_value directly instead. Don't
1688 free allocated memory until function exit.
1690 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1692 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1694 2017-02-03 Nick Clifton <nickc@redhat.com>
1697 * aarch64-opc.c (print_register_list): Ensure that the register
1698 list index will fir into the tb buffer.
1699 (print_register_offset_address): Likewise.
1700 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1702 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1705 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1706 instructions when the previous fetch packet ends with a 32-bit
1709 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1711 * pru-opc.c: Remove vague reference to a future GDB port.
1713 2017-01-20 Nick Clifton <nickc@redhat.com>
1715 * po/ga.po: Updated Irish translation.
1717 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1719 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1721 2017-01-13 Yao Qi <yao.qi@linaro.org>
1723 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1724 if FETCH_DATA returns 0.
1725 (m68k_scan_mask): Likewise.
1726 (print_insn_m68k): Update code to handle -1 return value.
1728 2017-01-13 Yao Qi <yao.qi@linaro.org>
1730 * m68k-dis.c (enum print_insn_arg_error): New.
1731 (NEXTBYTE): Replace -3 with
1732 PRINT_INSN_ARG_MEMORY_ERROR.
1733 (NEXTULONG): Likewise.
1734 (NEXTSINGLE): Likewise.
1735 (NEXTDOUBLE): Likewise.
1736 (NEXTDOUBLE): Likewise.
1737 (NEXTPACKED): Likewise.
1738 (FETCH_ARG): Likewise.
1739 (FETCH_DATA): Update comments.
1740 (print_insn_arg): Update comments. Replace magic numbers with
1742 (match_insn_m68k): Likewise.
1744 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1746 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1747 * i386-dis-evex.h (evex_table): Updated.
1748 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1749 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1750 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1751 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1752 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1753 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1754 * i386-init.h: Regenerate.
1755 * i386-tbl.h: Ditto.
1757 2017-01-12 Yao Qi <yao.qi@linaro.org>
1759 * msp430-dis.c (msp430_singleoperand): Return -1 if
1760 msp430dis_opcode_signed returns false.
1761 (msp430_doubleoperand): Likewise.
1762 (msp430_branchinstr): Return -1 if
1763 msp430dis_opcode_unsigned returns false.
1764 (msp430x_calla_instr): Likewise.
1765 (print_insn_msp430): Likewise.
1767 2017-01-05 Nick Clifton <nickc@redhat.com>
1770 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1771 could not be matched.
1772 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1775 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1777 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1778 (aarch64_opcode_table): Use RCPC_INSN.
1780 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1782 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1784 * riscv-opcodes/all-opcodes: Likewise.
1786 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1788 * riscv-dis.c (print_insn_args): Add fall through comment.
1790 2017-01-03 Nick Clifton <nickc@redhat.com>
1792 * po/sr.po: New Serbian translation.
1793 * configure.ac (ALL_LINGUAS): Add sr.
1794 * configure: Regenerate.
1796 2017-01-02 Alan Modra <amodra@gmail.com>
1798 * epiphany-desc.h: Regenerate.
1799 * epiphany-opc.h: Regenerate.
1800 * fr30-desc.h: Regenerate.
1801 * fr30-opc.h: Regenerate.
1802 * frv-desc.h: Regenerate.
1803 * frv-opc.h: Regenerate.
1804 * ip2k-desc.h: Regenerate.
1805 * ip2k-opc.h: Regenerate.
1806 * iq2000-desc.h: Regenerate.
1807 * iq2000-opc.h: Regenerate.
1808 * lm32-desc.h: Regenerate.
1809 * lm32-opc.h: Regenerate.
1810 * m32c-desc.h: Regenerate.
1811 * m32c-opc.h: Regenerate.
1812 * m32r-desc.h: Regenerate.
1813 * m32r-opc.h: Regenerate.
1814 * mep-desc.h: Regenerate.
1815 * mep-opc.h: Regenerate.
1816 * mt-desc.h: Regenerate.
1817 * mt-opc.h: Regenerate.
1818 * or1k-desc.h: Regenerate.
1819 * or1k-opc.h: Regenerate.
1820 * xc16x-desc.h: Regenerate.
1821 * xc16x-opc.h: Regenerate.
1822 * xstormy16-desc.h: Regenerate.
1823 * xstormy16-opc.h: Regenerate.
1825 2017-01-02 Alan Modra <amodra@gmail.com>
1827 Update year range in copyright notice of all files.
1829 For older changes see ChangeLog-2016
1831 Copyright (C) 2017 Free Software Foundation, Inc.
1833 Copying and distribution of this file, with or without modification,
1834 are permitted in any medium without royalty provided the copyright
1835 notice and this notice are preserved.
1841 version-control: never