opcodes/ChangeLog

   1 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         *arc-opc (insert_rhv2): Check h-regs range.
   4
   5 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
   6
   7         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
   8         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
   9
  10 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  11
  12         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
  13         and AARCH64_FEATURE_F16.
  14
  15 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  16
  17         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
  18         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
  19         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
  20         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
  21         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
  22         (ldapur, ldapursw, stlur): New.
  23         * aarch64-dis-2.c: Regenerate.
  24
  25 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  26
  27         (get_valid_dis386): Never flag bad opcode when
  28         vex.register_specifier is beyond 7. Always store all four
  29         bits of it. Move 16-/32-bit override in EVEX handling after
  30         all to be overridden bits have been set.
  31         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  32         Use rex to determine GPR register set.
  33         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  34         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  35
  36 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  39         determine GPR register set.
  40
  41 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  44         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  45         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  46         pass.
  47         (OP_REG_VexI4): Drop low 4 bits check.
  48
  49 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-reg.tbl (axl): Remove Acc and Byte.
  52         * i386-tbl.h: Re-generate.
  53
  54 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
  57         (vex_len_table): Use VPCOM.
  58
  59 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
  62         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
  63         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
  64         vpcmpw): Move up.
  65         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
  66         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
  67         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
  68         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
  69         vpcmpnltuw): New.
  70         * i386-tbl.h: Re-generate.
  71
  72 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
  75         smov, ssca, stos, ssto, xlat): Drop Disp*.
  76         * i386-tbl.h: Re-generate.
  77
  78 2017-11-13  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
  81         xsaveopt64): Add No_qSuf.
  82         * i386-tbl.h: Re-generate.
  83
  84 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  85
  86         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
  87         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
  88         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
  89         sder32_el2, vncr_el2.
  90         (aarch64_sys_reg_supported_p): Likewise.
  91         (aarch64_pstatefields): Add dit register.
  92         (aarch64_pstatefield_supported_p): Likewise.
  93         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
  94         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
  95         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
  96         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
  97         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
  98         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
  99         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 100
 101 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 102
 103         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 104         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 105         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 106         (QL_STLW, QL_STLX): New.
 107
 108 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 109
 110         * aarch64-asm.h (ins_addr_offset): New.
 111         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 112         (aarch64_ins_addr_offset): New.
 113         * aarch64-asm-2.c: Regenerate.
 114         * aarch64-dis.h (ext_addr_offset): New.
 115         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 116         (aarch64_ext_addr_offset): New.
 117         * aarch64-dis-2.c: Regenerate.
 118         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 119         FLD_imm4_2 and FLD_SM3_imm2.
 120         * aarch64-opc.c (fields): Add FLD_imm6_2,
 121         FLD_imm4_2 and FLD_SM3_imm2.
 122         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 123         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 124         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 125         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 126         * aarch64-tbl.h
 127         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 128
 129 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 130
 131         * aarch64-tbl.h
 132         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 133         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 134         (aarch64_feature_fp_16_v8_2): New.
 135         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 136         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 137         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 138
 139 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 140
 141         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 142         (aarch64_feature_sha2, aarch64_feature_aes): New.
 143         (SHA2, AES): New.
 144         (AES_INSN, SHA2_INSN): New.
 145         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 146         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 147          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 148         Change to SHA2_INS.
 149
 150 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 151             Tamar Christina <tamar.christina@arm.com>
 152
 153         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 154         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 155
 156 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 157
 158         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 159
 160 2017-11-07  Alan Modra  <amodra@gmail.com>
 161
 162         * opintl.h: Formatting, comment fixes.
 163         (gettext, ngettext): Redefine when ENABLE_NLS.
 164         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 165         (_): Define using gettext.
 166         (textdomain, bindtextdomain): Use safer "do nothing".
 167
 168 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 169
 170         * arc-dis.c (print_hex): New variable.
 171         (parse_option): Check for hex option.
 172         (print_insn_arc): Use hexadecimal representation for short
 173         immediate values when requested.
 174         (print_arc_disassembler_options): Add hex option to the list.
 175
 176 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 177
 178         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 179         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 180         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 181         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 182         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 183         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 184         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 185         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 186         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 187         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 188         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 189         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 190         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 191         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 192         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 193         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 194         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 195         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 196         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 197         Changed opcodes.
 198         (prealloc, prefetch*): Place them before ld instruction.
 199         * arc-opc.c (skip_this_opcode): Add ARITH class.
 200
 201 2017-10-25  Alan Modra  <amodra@gmail.com>
 202
 203         PR 22348
 204         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 205         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 206         (imm4flag, size_changed): Likewise.
 207         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 208         (words, allWords, processing_argument_number): Likewise.
 209         (cst4flag, size_changed): Likewise.
 210         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 211         (crx_cst4_maps): Rename from cst4_maps.
 212         (crx_no_op_insn): Rename from no_op_insn.
 213
 214 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 215
 216         * riscv-opc.c (match_c_addi16sp) : New function.
 217         (match_c_addi4spn): New function.
 218         (match_c_lui): Don't allow 0-immediate encodings.
 219         (riscv_opcodes) <addi>: Use the above functions.
 220         <add>: Likewise.
 221         <c.addi4spn>: Likewise.
 222         <c.addi16sp>: Likewise.
 223
 224 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 225
 226         * i386-init.h: Regenerate
 227         * i386-tbl.h: Likewise
 228
 229 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 230
 231         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 232         (enum): Add EVEX_W_0F3854_P_2.
 233         * i386-dis-evex.h (evex_table): Updated.
 234         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 235         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 236         (cpu_flags): Add CpuAVX512_BITALG.
 237         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 238         (i386_cpu_flags): Add cpuavx512_bitalg..
 239         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 240         * i386-init.h: Regenerate.
 241         * i386-tbl.h: Likewise.
 242
 243 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 244
 245         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 246         * i386-dis-evex.h (evex_table): Updated.
 247         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 248         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 249         (cpu_flags): Add CpuAVX512_VNNI.
 250         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 251         (i386_cpu_flags): Add cpuavx512_vnni.
 252         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 253         * i386-init.h: Regenerate.
 254         * i386-tbl.h: Likewise.
 255
 256 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 257
 258         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 259         (enum): Remove VEX_LEN_0F3A44_P_2.
 260         (vex_len_table): Ditto.
 261         (enum): Remove VEX_W_0F3A44_P_2.
 262         (vew_w_table): Ditto.
 263         (prefix_table): Adjust instructions (see prefixes above).
 264         * i386-dis-evex.h (evex_table):
 265         Add new instructions (see prefixes above).
 266         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 267         (bitfield_cpu_flags): Ditto.
 268         * i386-opc.h (enum): Ditto.
 269         (i386_cpu_flags): Ditto.
 270         (CpuUnused): Comment out to avoid zero-width field problem.
 271         * i386-opc.tbl (vpclmulqdq): New instruction.
 272         * i386-init.h: Regenerate.
 273         * i386-tbl.h: Ditto.
 274
 275 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 276
 277         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 278         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 279         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 280         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 281         (vex_len_table): Ditto.
 282         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 283         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 284         (vew_w_table): Ditto.
 285         (prefix_table): Adjust instructions (see prefixes above).
 286         * i386-dis-evex.h (evex_table):
 287         Add new instructions (see prefixes above).
 288         * i386-gen.c (cpu_flag_init): Add VAES.
 289         (bitfield_cpu_flags): Ditto.
 290         * i386-opc.h (enum): Ditto.
 291         (i386_cpu_flags): Ditto.
 292         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 293         * i386-init.h: Regenerate.
 294         * i386-tbl.h: Ditto.
 295
 296 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 297
 298         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 299         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 300         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 301         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 302         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 303         (prefix_table): Updated (see prefixes above).
 304         (three_byte_table): Likewise.
 305         (vex_w_table): Likewise.
 306         * i386-dis-evex.h: Likewise.
 307         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 308         (cpu_flags): Add CpuGFNI.
 309         * i386-opc.h (enum): Add CpuGFNI.
 310         (i386_cpu_flags): Add cpugfni.
 311         * i386-opc.tbl: Add Intel GFNI instructions.
 312         * i386-init.h: Regenerate.
 313         * i386-tbl.h: Likewise.
 314
 315 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 316
 317         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 318         Define EXbScalar and EXwScalar for OP_EX.
 319         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 320         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 321         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 322         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 323         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 324         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 325         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 326         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 327         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 328         (OP_E_memory): Likewise.
 329         * i386-dis-evex.h: Updated.
 330         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 331         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 332         (cpu_flags): Add CpuAVX512_VBMI2.
 333         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 334         (i386_cpu_flags): Add cpuavx512_vbmi2.
 335         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 336         * i386-init.h: Regenerate.
 337         * i386-tbl.h: Likewise.
 338
 339 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 340
 341         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 342
 343 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 344
 345         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 346         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 347         K15. Add jmpix pattern.
 348
 349 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 350
 351         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 352
 353 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 354
 355         * s390-opc.c (INSTR_SI_RD): New macro.
 356         (INSTR_S_RD): Adjust example instruction.
 357         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 358         SI_RD.
 359
 360 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 361
 362         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 363         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 364         VLE multimple load/store instructions. Old e_ldm* variants are
 365         kept as aliases.
 366         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 367
 368 2017-09-27  Nick Clifton  <nickc@redhat.com>
 369
 370         PR 22179
 371         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 372         names for the fmv.x.s and fmv.s.x instructions respectively.
 373
 374 2017-09-26  do  <do@nerilex.org>
 375
 376         PR 22123
 377         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 378         be used on CPUs that have emacs support.
 379
 380 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 381
 382         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 383
 384 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 385
 386         * nds32-asm.c: Rename __BIT() to N32_BIT().
 387         * nds32-asm.h: Likewise.
 388         * nds32-dis.c: Likewise.
 389
 390 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 391
 392         * i386-dis.c (last_active_prefix): Removed.
 393         (ckprefix): Don't set last_active_prefix.
 394         (NOTRACK_Fixup): Don't check last_active_prefix.
 395
 396 2017-08-31  Nick Clifton  <nickc@redhat.com>
 397
 398         * po/fr.po: Updated French translation.
 399
 400 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 401
 402         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 403         fields.
 404
 405 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 406             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 407
 408         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 409         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 410         New entries efs2 and spe2.
 411         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 412         (SPE2_OPCD_SEGS): New macro.
 413         (spe2_opcd_indices): New.
 414         (disassemble_init_powerpc): Handle SPE2 opcodes.
 415         (lookup_spe2): New function.
 416         (print_insn_powerpc): call lookup_spe2.
 417         * ppc-opc.c (insert_evuimm1_ex0): New function.
 418         (extract_evuimm1_ex0): Likewise.
 419         (insert_evuimm_lt8): Likewise.
 420         (extract_evuimm_lt8): Likewise.
 421         (insert_off_spe2): Likewise.
 422         (extract_off_spe2): Likewise.
 423         (insert_Ddd): Likewise.
 424         (extract_Ddd): Likewise.
 425         (DD): New operand.
 426         (EVUIMM_LT8): Likewise.
 427         (EVUIMM_LT16): Adjust.
 428         (MMMM): New operand.
 429         (EVUIMM_1): Likewise.
 430         (EVUIMM_1_EX0): Likewise.
 431         (EVUIMM_2): Adjust.
 432         (NNN): New operand.
 433         (VX_OFF_SPE2): Likewise.
 434         (BBB): Likewise.
 435         (DDD): Likewise.
 436         (VX_MASK_DDD): New mask.
 437         (HH): New operand.
 438         (VX_RA_CONST): New macro.
 439         (VX_RA_CONST_MASK): Likewise.
 440         (VX_RB_CONST): Likewise.
 441         (VX_RB_CONST_MASK): Likewise.
 442         (VX_OFF_SPE2_MASK): Likewise.
 443         (VX_SPE_CRFD): Likewise.
 444         (VX_SPE_CRFD_MASK VX): Likewise.
 445         (VX_SPE2_CLR): Likewise.
 446         (VX_SPE2_CLR_MASK): Likewise.
 447         (VX_SPE2_SPLATB): Likewise.
 448         (VX_SPE2_SPLATB_MASK): Likewise.
 449         (VX_SPE2_OCTET): Likewise.
 450         (VX_SPE2_OCTET_MASK): Likewise.
 451         (VX_SPE2_DDHH): Likewise.
 452         (VX_SPE2_DDHH_MASK): Likewise.
 453         (VX_SPE2_HH): Likewise.
 454         (VX_SPE2_HH_MASK): Likewise.
 455         (VX_SPE2_EVMAR): Likewise.
 456         (VX_SPE2_EVMAR_MASK): Likewise.
 457         (PPCSPE2): Likewise.
 458         (PPCEFS2): Likewise.
 459         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 460         (powerpc_macros): Map old SPE instructions have new names
 461         with the same opcodes. Add SPE2 instructions which just are
 462         mapped to SPE2.
 463         (spe2_opcodes): Add SPE2 opcodes.
 464
 465 2017-08-23  Alan Modra  <amodra@gmail.com>
 466
 467         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 468         extract functions earlier, deleting forward declarations.
 469         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 470         RA_MASK.
 471
 472 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 473
 474         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 475
 476 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 477             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 478
 479         * ppc-opc.c (insert_evuimm2_ex0): New function.
 480         (extract_evuimm2_ex0): Likewise.
 481         (insert_evuimm4_ex0): Likewise.
 482         (extract_evuimm4_ex0): Likewise.
 483         (insert_evuimm8_ex0): Likewise.
 484         (extract_evuimm8_ex0): Likewise.
 485         (insert_evuimm_lt16): Likewise.
 486         (extract_evuimm_lt16): Likewise.
 487         (insert_rD_rS_even): Likewise.
 488         (extract_rD_rS_even): Likewise.
 489         (insert_off_lsp): Likewise.
 490         (extract_off_lsp): Likewise.
 491         (RD_EVEN): New operand.
 492         (RS_EVEN): Likewise.
 493         (RSQ): Adjust.
 494         (EVUIMM_LT16): New operand.
 495         (HTM_SI): Adjust.
 496         (EVUIMM_2_EX0): New operand.
 497         (EVUIMM_4): Adjust.
 498         (EVUIMM_4_EX0): New operand.
 499         (EVUIMM_8): Adjust.
 500         (EVUIMM_8_EX0): New operand.
 501         (WS): Adjust.
 502         (VX_OFF): New operand.
 503         (VX_LSP): New macro.
 504         (VX_LSP_MASK): Likewise.
 505         (VX_LSP_OFF_MASK): Likewise.
 506         (PPC_OPCODE_LSP): Likewise.
 507         (vle_opcodes): Add LSP opcodes.
 508         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 509
 510 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 511
 512         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 513         register operands in CRC instructions.
 514         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 515         comments.
 516
 517 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 518
 519         * disassemble.c (disassembler): Mark big and mach with
 520         ATTRIBUTE_UNUSED.
 521
 522 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 523
 524         * disassemble.c (disassembler): Remove arch/mach/endian
 525         assertions.
 526
 527 2017-07-25  Nick Clifton  <nickc@redhat.com>
 528
 529         PR 21739
 530         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 531         message.
 532         (insert_r0): Likewise.
 533         (insert_r1): Likewise.
 534         (insert_r2): Likewise.
 535         (insert_r3): Likewise.
 536         (insert_sp): Likewise.
 537         (insert_gp): Likewise.
 538         (insert_pcl): Likewise.
 539         (insert_blink): Likewise.
 540         (insert_ilink1): Likewise.
 541         (insert_ilink2): Likewise.
 542         (insert_ras): Likewise.
 543         (insert_rbs): Likewise.
 544         (insert_rcs): Likewise.
 545         (insert_simm3s): Likewise.
 546         (insert_rrange): Likewise.
 547         (insert_r13el): Likewise.
 548         (insert_fpel): Likewise.
 549         (insert_blinkel): Likewise.
 550         (insert_pclel): Likewise.
 551         (insert_nps_bitop_size_2b): Likewise.
 552         (insert_nps_imm_offset): Likewise.
 553         (insert_nps_imm_entry): Likewise.
 554         (insert_nps_size_16bit): Likewise.
 555         (insert_nps_##NAME##_pos): Likewise.
 556         (insert_nps_##NAME): Likewise.
 557         (insert_nps_bitop_ins_ext): Likewise.
 558         (insert_nps_##NAME): Likewise.
 559         (insert_nps_min_hofs): Likewise.
 560         (insert_nps_##NAME): Likewise.
 561         (insert_nps_rbdouble_64): Likewise.
 562         (insert_nps_misc_imm_offset): Likewise.
 563         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 564         option description.
 565
 566 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 567             Jiong Wang  <jiong.wang@arm.com>
 568
 569         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 570         correct the print.
 571         * aarch64-dis-2.c: Regenerated.
 572
 573 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 574
 575         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 576         table.
 577
 578 2017-07-20  Nick Clifton  <nickc@redhat.com>
 579
 580         * po/de.po: Updated German translation.
 581
 582 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 583
 584         * arc-regs.h (sec_stat): New aux register.
 585         (aux_kernel_sp): Likewise.
 586         (aux_sec_u_sp): Likewise.
 587         (aux_sec_k_sp): Likewise.
 588         (sec_vecbase_build): Likewise.
 589         (nsc_table_top): Likewise.
 590         (nsc_table_base): Likewise.
 591         (ersec_stat): Likewise.
 592         (aux_sec_except): Likewise.
 593
 594 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 595
 596         * arc-opc.c (extract_uimm12_20): New function.
 597         (UIMM12_20): New operand.
 598         (SIMM3_5_S): Adjust.
 599         * arc-tbl.h (sjli): Add new instruction.
 600
 601 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 602             John Eric Martin  <John.Martin@emmicro-us.com>
 603
 604         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 605         (UIMM3_23): Adjust accordingly.
 606         * arc-regs.h: Add/correct jli_base register.
 607         * arc-tbl.h (jli_s): Likewise.
 608
 609 2017-07-18  Nick Clifton  <nickc@redhat.com>
 610
 611         PR 21775
 612         * aarch64-opc.c: Fix spelling typos.
 613         * i386-dis.c: Likewise.
 614
 615 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 616
 617         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 618         max_addr_offset and octets variables to size_t.
 619
 620 2017-07-12  Alan Modra  <amodra@gmail.com>
 621
 622         * po/da.po: Update from translationproject.org/latest/opcodes/.
 623         * po/de.po: Likewise.
 624         * po/es.po: Likewise.
 625         * po/fi.po: Likewise.
 626         * po/fr.po: Likewise.
 627         * po/id.po: Likewise.
 628         * po/it.po: Likewise.
 629         * po/nl.po: Likewise.
 630         * po/pt_BR.po: Likewise.
 631         * po/ro.po: Likewise.
 632         * po/sv.po: Likewise.
 633         * po/tr.po: Likewise.
 634         * po/uk.po: Likewise.
 635         * po/vi.po: Likewise.
 636         * po/zh_CN.po: Likewise.
 637
 638 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 639             Alan Modra  <amodra@gmail.com>
 640
 641         * cgen.sh: Mark generated files read-only.
 642         * epiphany-asm.c: Regenerate.
 643         * epiphany-desc.c: Regenerate.
 644         * epiphany-desc.h: Regenerate.
 645         * epiphany-dis.c: Regenerate.
 646         * epiphany-ibld.c: Regenerate.
 647         * epiphany-opc.c: Regenerate.
 648         * epiphany-opc.h: Regenerate.
 649         * fr30-asm.c: Regenerate.
 650         * fr30-desc.c: Regenerate.
 651         * fr30-desc.h: Regenerate.
 652         * fr30-dis.c: Regenerate.
 653         * fr30-ibld.c: Regenerate.
 654         * fr30-opc.c: Regenerate.
 655         * fr30-opc.h: Regenerate.
 656         * frv-asm.c: Regenerate.
 657         * frv-desc.c: Regenerate.
 658         * frv-desc.h: Regenerate.
 659         * frv-dis.c: Regenerate.
 660         * frv-ibld.c: Regenerate.
 661         * frv-opc.c: Regenerate.
 662         * frv-opc.h: Regenerate.
 663         * ip2k-asm.c: Regenerate.
 664         * ip2k-desc.c: Regenerate.
 665         * ip2k-desc.h: Regenerate.
 666         * ip2k-dis.c: Regenerate.
 667         * ip2k-ibld.c: Regenerate.
 668         * ip2k-opc.c: Regenerate.
 669         * ip2k-opc.h: Regenerate.
 670         * iq2000-asm.c: Regenerate.
 671         * iq2000-desc.c: Regenerate.
 672         * iq2000-desc.h: Regenerate.
 673         * iq2000-dis.c: Regenerate.
 674         * iq2000-ibld.c: Regenerate.
 675         * iq2000-opc.c: Regenerate.
 676         * iq2000-opc.h: Regenerate.
 677         * lm32-asm.c: Regenerate.
 678         * lm32-desc.c: Regenerate.
 679         * lm32-desc.h: Regenerate.
 680         * lm32-dis.c: Regenerate.
 681         * lm32-ibld.c: Regenerate.
 682         * lm32-opc.c: Regenerate.
 683         * lm32-opc.h: Regenerate.
 684         * lm32-opinst.c: Regenerate.
 685         * m32c-asm.c: Regenerate.
 686         * m32c-desc.c: Regenerate.
 687         * m32c-desc.h: Regenerate.
 688         * m32c-dis.c: Regenerate.
 689         * m32c-ibld.c: Regenerate.
 690         * m32c-opc.c: Regenerate.
 691         * m32c-opc.h: Regenerate.
 692         * m32r-asm.c: Regenerate.
 693         * m32r-desc.c: Regenerate.
 694         * m32r-desc.h: Regenerate.
 695         * m32r-dis.c: Regenerate.
 696         * m32r-ibld.c: Regenerate.
 697         * m32r-opc.c: Regenerate.
 698         * m32r-opc.h: Regenerate.
 699         * m32r-opinst.c: Regenerate.
 700         * mep-asm.c: Regenerate.
 701         * mep-desc.c: Regenerate.
 702         * mep-desc.h: Regenerate.
 703         * mep-dis.c: Regenerate.
 704         * mep-ibld.c: Regenerate.
 705         * mep-opc.c: Regenerate.
 706         * mep-opc.h: Regenerate.
 707         * mt-asm.c: Regenerate.
 708         * mt-desc.c: Regenerate.
 709         * mt-desc.h: Regenerate.
 710         * mt-dis.c: Regenerate.
 711         * mt-ibld.c: Regenerate.
 712         * mt-opc.c: Regenerate.
 713         * mt-opc.h: Regenerate.
 714         * or1k-asm.c: Regenerate.
 715         * or1k-desc.c: Regenerate.
 716         * or1k-desc.h: Regenerate.
 717         * or1k-dis.c: Regenerate.
 718         * or1k-ibld.c: Regenerate.
 719         * or1k-opc.c: Regenerate.
 720         * or1k-opc.h: Regenerate.
 721         * or1k-opinst.c: Regenerate.
 722         * xc16x-asm.c: Regenerate.
 723         * xc16x-desc.c: Regenerate.
 724         * xc16x-desc.h: Regenerate.
 725         * xc16x-dis.c: Regenerate.
 726         * xc16x-ibld.c: Regenerate.
 727         * xc16x-opc.c: Regenerate.
 728         * xc16x-opc.h: Regenerate.
 729         * xstormy16-asm.c: Regenerate.
 730         * xstormy16-desc.c: Regenerate.
 731         * xstormy16-desc.h: Regenerate.
 732         * xstormy16-dis.c: Regenerate.
 733         * xstormy16-ibld.c: Regenerate.
 734         * xstormy16-opc.c: Regenerate.
 735         * xstormy16-opc.h: Regenerate.
 736
 737 2017-07-07  Alan Modra  <amodra@gmail.com>
 738
 739         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 740         * m32c-dis.c: Regenerate.
 741         * mep-dis.c: Regenerate.
 742
 743 2017-07-05  Borislav Petkov  <bp@suse.de>
 744
 745         * i386-dis.c: Enable ModRM.reg /6 aliases.
 746
 747 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 748
 749         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 750         with vmrs and vmsr.
 751
 752 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 753
 754         * configure: Regenerate.
 755
 756 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 757
 758         * po/opcodes.pot: Regenerate.
 759
 760 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 761
 762         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 763         entries to the MSA ASE instruction block.
 764
 765 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 766             Maciej W. Rozycki  <macro@imgtec.com>
 767
 768         * micromips-opc.c (XPA, XPAVZ): New macros.
 769         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 770         "mthgc0".
 771
 772 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 773             Maciej W. Rozycki  <macro@imgtec.com>
 774
 775         * micromips-opc.c (I36): New macro.
 776         (micromips_opcodes): Add "eretnc".
 777
 778 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 779             Andrew Bennett  <andrew.bennett@imgtec.com>
 780
 781         * mips-dis.c (mips_calculate_combination_ases): Handle the
 782         ASE_XPA_VIRT flag.
 783         (parse_mips_ase_option): New function.
 784         (parse_mips_dis_option): Factor out ASE option handling to the
 785         new function.  Call `mips_calculate_combination_ases'.
 786         * mips-opc.c (XPAVZ): New macro.
 787         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 788         "mfhgc0", "mthc0" and "mthgc0".
 789
 790 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 791
 792         * mips-dis.c (mips_calculate_combination_ases): New function.
 793         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 794         calculation to the new function.
 795         (set_default_mips_dis_options): Call the new function.
 796
 797 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 798
 799         * arc-dis.c (parse_disassembler_options): Use
 800         FOR_EACH_DISASSEMBLER_OPTION.
 801
 802 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 803
 804         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 805         disassembler option strings.
 806         (parse_cpu_option): Likewise.
 807
 808 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 809
 810         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 811         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 812         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 813         (aarch64_feature_dotprod, DOT_INSN): New.
 814         (udot, sdot): New.
 815         * aarch64-dis-2.c: Regenerated.
 816
 817 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 818
 819         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 820
 821 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 822             Matthew Fortune  <matthew.fortune@imgtec.com>
 823             Andrew Bennett  <andrew.bennett@imgtec.com>
 824
 825         * mips-formats.h (INT_BIAS): New macro.
 826         (INT_ADJ): Redefine in INT_BIAS terms.
 827         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 828         (mips_print_save_restore): New function.
 829         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 830         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 831         call.
 832         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 833         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 834         OP_SAVE_RESTORE_LIST handling, factored out from here.
 835         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 836         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 837         (mips_builtin_opcodes): Add "restore" and "save" entries.
 838         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 839         (IAMR2): New macro.
 840         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 841
 842 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 843
 844         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 845         alias; do not mark SLTI instruction as an alias.
 846
 847 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 848
 849         * i386-dis.c (RM_0FAE_REG_5): Removed.
 850         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 851         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 852         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 853         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 854         PREFIX_MOD_3_0F01_REG_5_RM_0.
 855         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 856         PREFIX_MOD_3_0FAE_REG_5.
 857         (mod_table): Update MOD_0FAE_REG_5.
 858         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 859         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 860         * i386-tbl.h: Regenerated.
 861
 862 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 863
 864         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 865         * i386-opc.tbl: Likewise.
 866         * i386-tbl.h: Regenerated.
 867
 868 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 869
 870         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 871         and "jmp{&|}".
 872         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 873         prefix.
 874
 875 2017-06-19  Nick Clifton  <nickc@redhat.com>
 876
 877         PR binutils/21614
 878         * score-dis.c (score_opcodes): Add sentinel.
 879
 880 2017-06-16  Alan Modra  <amodra@gmail.com>
 881
 882         * rx-decode.c: Regenerate.
 883
 884 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 885
 886         PR binutils/21594
 887         * i386-dis.c (OP_E_register): Check valid bnd register.
 888         (OP_G): Likewise.
 889
 890 2017-06-15  Nick Clifton  <nickc@redhat.com>
 891
 892         PR binutils/21595
 893         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 894         range value.
 895
 896 2017-06-15  Nick Clifton  <nickc@redhat.com>
 897
 898         PR binutils/21588
 899         * rl78-decode.opc (OP_BUF_LEN): Define.
 900         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 901         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 902         array.
 903         * rl78-decode.c: Regenerate.
 904
 905 2017-06-15  Nick Clifton  <nickc@redhat.com>
 906
 907         PR binutils/21586
 908         * bfin-dis.c (gregs): Clip index to prevent overflow.
 909         (regs): Likewise.
 910         (regs_lo): Likewise.
 911         (regs_hi): Likewise.
 912
 913 2017-06-14  Nick Clifton  <nickc@redhat.com>
 914
 915         PR binutils/21576
 916         * score7-dis.c (score_opcodes): Add sentinel.
 917
 918 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 919
 920         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 921         * arm-dis.c: Likewise.
 922         * ia64-dis.c: Likewise.
 923         * mips-dis.c: Likewise.
 924         * spu-dis.c: Likewise.
 925         * disassemble.h (print_insn_aarch64): New declaration, moved from
 926         include/dis-asm.h.
 927         (print_insn_big_arm, print_insn_big_mips): Likewise.
 928         (print_insn_i386, print_insn_ia64): Likewise.
 929         (print_insn_little_arm, print_insn_little_mips): Likewise.
 930
 931 2017-06-14  Nick Clifton  <nickc@redhat.com>
 932
 933         PR binutils/21587
 934         * rx-decode.opc: Include libiberty.h
 935         (GET_SCALE): New macro - validates access to SCALE array.
 936         (GET_PSCALE): New macro - validates access to PSCALE array.
 937         (DIs, SIs, S2Is, rx_disp): Use new macros.
 938         * rx-decode.c: Regenerate.
 939
 940 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 941
 942         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 943
 944 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 945
 946         * arc-dis.c (enforced_isa_mask): Declare.
 947         (cpu_types): Likewise.
 948         (parse_cpu_option): New function.
 949         (parse_disassembler_options): Use it.
 950         (print_insn_arc): Use enforced_isa_mask.
 951         (print_arc_disassembler_options): Document new options.
 952
 953 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 954
 955         * alpha-dis.c: Include disassemble.h, don't include
 956         dis-asm.h.
 957         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 958         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 959         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 960         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 961         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 962         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 963         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 964         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 965         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 966         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 967         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 968         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 969         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 970         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 971         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 972         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 973         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 974         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 975         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 976         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 977         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 978         * z80-dis.c, z8k-dis.c: Likewise.
 979         * disassemble.h: New file.
 980
 981 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 982
 983         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 984         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 985
 986 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 987
 988         * disassemble.c (disassembler): Add arguments a, big and mach.
 989         Use them.
 990
 991 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 992
 993         * i386-dis.c (NOTRACK_Fixup): New.
 994         (NOTRACK): Likewise.
 995         (NOTRACK_PREFIX): Likewise.
 996         (last_active_prefix): Likewise.
 997         (reg_table): Use NOTRACK on indirect call and jmp.
 998         (ckprefix): Set last_active_prefix.
 999         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1000         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1001         * i386-opc.h (NoTrackPrefixOk): New.
1002         (i386_opcode_modifier): Add notrackprefixok.
1003         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1004         Add notrack.
1005         * i386-tbl.h: Regenerated.
1006
1007 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1008
1009         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1010         (X_IMM2): Define.
1011         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1012         bfd_mach_sparc_v9m8.
1013         (print_insn_sparc): Handle new operand types.
1014         * sparc-opc.c (MASK_M8): Define.
1015         (v6): Add MASK_M8.
1016         (v6notlet): Likewise.
1017         (v7): Likewise.
1018         (v8): Likewise.
1019         (v9): Likewise.
1020         (v9a): Likewise.
1021         (v9b): Likewise.
1022         (v9c): Likewise.
1023         (v9d): Likewise.
1024         (v9e): Likewise.
1025         (v9v): Likewise.
1026         (v9m): Likewise.
1027         (v9andleon): Likewise.
1028         (m8): Define.
1029         (HWS_VM8): Define.
1030         (HWS2_VM8): Likewise.
1031         (sparc_opcode_archs): Add entry for "m8".
1032         (sparc_opcodes): Add OSA2017 and M8 instructions
1033         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1034         fpx{ll,ra,rl}64x,
1035         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1036         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1037         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1038         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1039         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1040         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1041         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1042         ASI_CORE_SELECT_COMMIT_NHT.
1043
1044 2017-05-18  Alan Modra  <amodra@gmail.com>
1045
1046         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1047         * aarch64-dis.c: Likewise.
1048         * aarch64-gen.c: Likewise.
1049         * aarch64-opc.c: Likewise.
1050
1051 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1052             Matthew Fortune  <matthew.fortune@imgtec.com>
1053
1054         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1055         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1056         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1057         (print_insn_arg) <OP_REG28>: Add handler.
1058         (validate_insn_args) <OP_REG28>: Handle.
1059         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1060         32-bit encoding and 9-bit immediates.
1061         (print_insn_mips16): Handle MIPS16 instructions that require
1062         32-bit encoding and MFC0/MTC0 operand decoding.
1063         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1064         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1065         (RD_C0, WR_C0, E2, E2MT): New macros.
1066         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1067         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1068         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1069         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1070         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1071         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1072         instructions, "swl", "swr", "sync" and its "sync_acquire",
1073         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1074         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1075         regular/extended entries for original MIPS16 ISA revision
1076         instructions whose extended forms are subdecoded in the MIPS16e2
1077         ISA revision: "li", "sll" and "srl".
1078
1079 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1080
1081         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1082         reference in CP0 move operand decoding.
1083
1084 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1085
1086         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1087         type to hexadecimal.
1088         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1089
1090 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1091
1092         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1093         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1094         "sync_rmb" and "sync_wmb" as aliases.
1095         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1096         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1097
1098 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1099
1100         * arc-dis.c (parse_option): Update quarkse_em option..
1101         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1102         QUARKSE1.
1103         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1104
1105 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1106
1107         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1108
1109 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1110
1111         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1112         register.
1113
1114 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1115
1116         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1117         and branches and not synthetic data instructions.
1118
1119 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1120
1121         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1122
1123 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1124
1125         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1126         * arc-opc.c (insert_r13el): New function.
1127         (R13_EL): Define.
1128         * arc-tbl.h: Add new enter/leave variants.
1129
1130 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1131
1132         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1133
1134 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1135
1136         * mips-dis.c (print_mips_disassembler_options): Add
1137         `no-aliases'.
1138
1139 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1140
1141         * mips16-opc.c (AL): New macro.
1142         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1143         of "ld" and "lw" as aliases.
1144
1145 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1146
1147         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1148         arguments.
1149
1150 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1151             Alan Modra  <amodra@gmail.com>
1152
1153         * ppc-opc.c (ELEV): Define.
1154         (vle_opcodes): Add se_rfgi and e_sc.
1155         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1156         for E200Z4.
1157
1158 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1159
1160         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1161
1162 2017-04-21  Nick Clifton  <nickc@redhat.com>
1163
1164         PR binutils/21380
1165         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1166         LD3R and LD4R.
1167
1168 2017-04-13  Alan Modra  <amodra@gmail.com>
1169
1170         * epiphany-desc.c: Regenerate.
1171         * fr30-desc.c: Regenerate.
1172         * frv-desc.c: Regenerate.
1173         * ip2k-desc.c: Regenerate.
1174         * iq2000-desc.c: Regenerate.
1175         * lm32-desc.c: Regenerate.
1176         * m32c-desc.c: Regenerate.
1177         * m32r-desc.c: Regenerate.
1178         * mep-desc.c: Regenerate.
1179         * mt-desc.c: Regenerate.
1180         * or1k-desc.c: Regenerate.
1181         * xc16x-desc.c: Regenerate.
1182         * xstormy16-desc.c: Regenerate.
1183
1184 2017-04-11  Alan Modra  <amodra@gmail.com>
1185
1186         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1187         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1188         PPC_OPCODE_TMR for e6500.
1189         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1190         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1191         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1192         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1193         (PPCHTM): Define as PPC_OPCODE_POWER8.
1194         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1195
1196 2017-04-10  Alan Modra  <amodra@gmail.com>
1197
1198         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1199         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1200         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1201         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1202
1203 2017-04-09  Pip Cet  <pipcet@gmail.com>
1204
1205         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1206         appropriate floating-point precision directly.
1207
1208 2017-04-07  Alan Modra  <amodra@gmail.com>
1209
1210         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1211         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1212         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1213         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1214         vector instructions with E6500 not PPCVEC2.
1215
1216 2017-04-06  Pip Cet  <pipcet@gmail.com>
1217
1218         * Makefile.am: Add wasm32-dis.c.
1219         * configure.ac: Add wasm32-dis.c to wasm32 target.
1220         * disassemble.c: Add wasm32 disassembler code.
1221         * wasm32-dis.c: New file.
1222         * Makefile.in: Regenerate.
1223         * configure: Regenerate.
1224         * po/POTFILES.in: Regenerate.
1225         * po/opcodes.pot: Regenerate.
1226
1227 2017-04-05  Pedro Alves  <palves@redhat.com>
1228
1229         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1230         * arm-dis.c (parse_arm_disassembler_options): Constify.
1231         * ppc-dis.c (powerpc_init_dialect): Constify local.
1232         * vax-dis.c (parse_disassembler_options): Constify.
1233
1234 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1235
1236         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1237         RISCV_GP_SYMBOL.
1238
1239 2017-03-30  Pip Cet  <pipcet@gmail.com>
1240
1241         * configure.ac: Add (empty) bfd_wasm32_arch target.
1242         * configure: Regenerate
1243         * po/opcodes.pot: Regenerate.
1244
1245 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1246
1247         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1248         OSA2015.
1249         * opcodes/sparc-opc.c (asi_table): New ASIs.
1250
1251 2017-03-29  Alan Modra  <amodra@gmail.com>
1252
1253         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1254         "raw" option.
1255         (lookup_powerpc): Don't special case -1 dialect.  Handle
1256         PPC_OPCODE_RAW.
1257         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1258         lookup_powerpc call, pass it on second.
1259
1260 2017-03-27  Alan Modra  <amodra@gmail.com>
1261
1262         PR 21303
1263         * ppc-dis.c (struct ppc_mopt): Comment.
1264         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1265
1266 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1267
1268         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1269         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1270         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1271         (insert_nps_misc_imm_offset): New function.
1272         (extract_nps_misc imm_offset): New function.
1273         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1274         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1275
1276 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1277
1278         * s390-mkopc.c (main): Remove vx2 check.
1279         * s390-opc.txt: Remove vx2 instruction flags.
1280
1281 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1282
1283         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1284         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1285         (insert_nps_imm_offset): New function.
1286         (extract_nps_imm_offset): New function.
1287         (insert_nps_imm_entry): New function.
1288         (extract_nps_imm_entry): New function.
1289
1290 2017-03-17  Alan Modra  <amodra@gmail.com>
1291
1292         PR 21248
1293         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1294         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1295         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1296
1297 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1298
1299         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1300         <c.andi>: Likewise.
1301         <c.addiw> Likewise.
1302
1303 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1304
1305         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1306
1307 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1308
1309         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1310         <srl> Likewise.
1311         <srai> Likewise.
1312         <sra> Likewise.
1313
1314 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1315
1316         * i386-gen.c (opcode_modifiers): Replace S with Load.
1317         * i386-opc.h (S): Removed.
1318         (Load): New.
1319         (i386_opcode_modifier): Replace s with load.
1320         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1321         and {evex}.  Replace S with Load.
1322         * i386-tbl.h: Regenerated.
1323
1324 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1325
1326         * i386-opc.tbl: Use CpuCET on rdsspq.
1327         * i386-tbl.h: Regenerated.
1328
1329 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1330
1331         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1332         <vsx>: Do not use PPC_OPCODE_VSX3;
1333
1334 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1335
1336         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1337
1338 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1339
1340         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1341         (MOD_0F1E_PREFIX_1): Likewise.
1342         (MOD_0F38F5_PREFIX_2): Likewise.
1343         (MOD_0F38F6_PREFIX_0): Likewise.
1344         (RM_0F1E_MOD_3_REG_7): Likewise.
1345         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1346         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1347         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1348         (PREFIX_0F1E): Likewise.
1349         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1350         (PREFIX_0F38F5): Likewise.
1351         (dis386_twobyte): Use PREFIX_0F1E.
1352         (reg_table): Add REG_0F1E_MOD_3.
1353         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1354         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1355         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1356         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1357         (three_byte_table): Use PREFIX_0F38F5.
1358         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1359         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1360         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1361         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1362         PREFIX_MOD_3_0F01_REG_5_RM_2.
1363         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1364         (cpu_flags): Add CpuCET.
1365         * i386-opc.h (CpuCET): New enum.
1366         (CpuUnused): Commented out.
1367         (i386_cpu_flags): Add cpucet.
1368         * i386-opc.tbl: Add Intel CET instructions.
1369         * i386-init.h: Regenerated.
1370         * i386-tbl.h: Likewise.
1371
1372 2017-03-06  Alan Modra  <amodra@gmail.com>
1373
1374         PR 21124
1375         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1376         (extract_raq, extract_ras, extract_rbx): New functions.
1377         (powerpc_operands): Use opposite corresponding insert function.
1378         (Q_MASK): Define.
1379         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1380         register restriction.
1381
1382 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1383
1384         * disassemble.c Include "safe-ctype.h".
1385         (disassemble_init_for_target): Handle s390 init.
1386         (remove_whitespace_and_extra_commas): New function.
1387         (disassembler_options_cmp): Likewise.
1388         * arm-dis.c: Include "libiberty.h".
1389         (NUM_ELEM): Delete.
1390         (regnames): Use long disassembler style names.
1391         Add force-thumb and no-force-thumb options.
1392         (NUM_ARM_REGNAMES): Rename from this...
1393         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1394         (get_arm_regname_num_options): Delete.
1395         (set_arm_regname_option): Likewise.
1396         (get_arm_regnames): Likewise.
1397         (parse_disassembler_options): Likewise.
1398         (parse_arm_disassembler_option): Rename from this...
1399         (parse_arm_disassembler_options): ...to this.  Make static.
1400         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1401         (print_insn): Use parse_arm_disassembler_options.
1402         (disassembler_options_arm): New function.
1403         (print_arm_disassembler_options): Handle updated regnames.
1404         * ppc-dis.c: Include "libiberty.h".
1405         (ppc_opts): Add "32" and "64" entries.
1406         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1407         (powerpc_init_dialect): Add break to switch statement.
1408         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1409         (disassembler_options_powerpc): New function.
1410         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1411         Remove printing of "32" and "64".
1412         * s390-dis.c: Include "libiberty.h".
1413         (init_flag): Remove unneeded variable.
1414         (struct s390_options_t): New structure type.
1415         (options): New structure.
1416         (init_disasm): Rename from this...
1417         (disassemble_init_s390): ...to this.  Add initializations for
1418         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1419         (print_insn_s390): Delete call to init_disasm.
1420         (disassembler_options_s390): New function.
1421         (print_s390_disassembler_options): Print using information from
1422         struct 'options'.
1423         * po/opcodes.pot: Regenerate.
1424
1425 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1426
1427         * i386-dis.c (PCMPESTR_Fixup): New.
1428         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1429         (prefix_table): Use PCMPESTR_Fixup.
1430         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1431         PCMPESTR_Fixup.
1432         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1433         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1434         Split 64-bit and non-64-bit variants.
1435         * opcodes/i386-tbl.h: Re-generate.
1436
1437 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1438
1439         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1440         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1441         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1442         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1443         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1444         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1445         (OP_SVE_V_HSD): New macros.
1446         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1447         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1448         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1449         (aarch64_opcode_table): Add new SVE instructions.
1450         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1451         for rotation operands.  Add new SVE operands.
1452         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1453         (ins_sve_quad_index): Likewise.
1454         (ins_imm_rotate): Split into...
1455         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1456         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1457         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1458         functions.
1459         (aarch64_ins_sve_addr_ri_s4): New function.
1460         (aarch64_ins_sve_quad_index): Likewise.
1461         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1462         * aarch64-asm-2.c: Regenerate.
1463         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1464         (ext_sve_quad_index): Likewise.
1465         (ext_imm_rotate): Split into...
1466         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1467         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1468         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1469         functions.
1470         (aarch64_ext_sve_addr_ri_s4): New function.
1471         (aarch64_ext_sve_quad_index): Likewise.
1472         (aarch64_ext_sve_index): Allow quad indices.
1473         (do_misc_decoding): Likewise.
1474         * aarch64-dis-2.c: Regenerate.
1475         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1476         aarch64_field_kinds.
1477         (OPD_F_OD_MASK): Widen by one bit.
1478         (OPD_F_NO_ZR): Bump accordingly.
1479         (get_operand_field_width): New function.
1480         * aarch64-opc.c (fields): Add new SVE fields.
1481         (operand_general_constraint_met_p): Handle new SVE operands.
1482         (aarch64_print_operand): Likewise.
1483         * aarch64-opc-2.c: Regenerate.
1484
1485 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1486
1487         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1488         (aarch64_feature_compnum): ...this.
1489         (SIMD_V8_3): Replace with...
1490         (COMPNUM): ...this.
1491         (CNUM_INSN): New macro.
1492         (aarch64_opcode_table): Use it for the complex number instructions.
1493
1494 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1495
1496         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1497
1498 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1499
1500         Add support for associating SPARC ASIs with an architecture level.
1501         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1502         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1503         decoding of SPARC ASIs.
1504
1505 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1506
1507         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1508         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1509
1510 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1511
1512         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1513         1 (instead of to itself). Correct typo.
1514
1515 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1516
1517         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1518         pseudoinstructions.
1519
1520 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1521
1522         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1523         (aarch64_sys_reg_supported_p): Handle them.
1524
1525 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1526
1527         * arc-opc.c (UIMM6_20R): Define.
1528         (SIMM12_20): Use above.
1529         (SIMM12_20R): Define.
1530         (SIMM3_5_S): Use above.
1531         (UIMM7_A32_11R_S): Define.
1532         (UIMM7_9_S): Use above.
1533         (UIMM3_13R_S): Define.
1534         (SIMM11_A32_7_S): Use above.
1535         (SIMM9_8R): Define.
1536         (UIMM10_A32_8_S): Use above.
1537         (UIMM8_8R_S): Define.
1538         (W6): Use above.
1539         (arc_relax_opcodes): Use all above defines.
1540
1541 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1542
1543         * arc-regs.h: Distinguish some of the registers different on
1544         ARC700 and HS38 cpus.
1545
1546 2017-02-14  Alan Modra  <amodra@gmail.com>
1547
1548         PR 21118
1549         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1550         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1551
1552 2017-02-11  Stafford Horne  <shorne@gmail.com>
1553             Alan Modra  <amodra@gmail.com>
1554
1555         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1556         Use insn_bytes_value and insn_int_value directly instead.  Don't
1557         free allocated memory until function exit.
1558
1559 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1560
1561         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1562
1563 2017-02-03  Nick Clifton  <nickc@redhat.com>
1564
1565         PR 21096
1566         * aarch64-opc.c (print_register_list): Ensure that the register
1567         list index will fir into the tb buffer.
1568         (print_register_offset_address): Likewise.
1569         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1570
1571 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1572
1573         PR 21056
1574         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1575         instructions when the previous fetch packet ends with a 32-bit
1576         instruction.
1577
1578 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1579
1580         * pru-opc.c: Remove vague reference to a future GDB port.
1581
1582 2017-01-20  Nick Clifton  <nickc@redhat.com>
1583
1584         * po/ga.po: Updated Irish translation.
1585
1586 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1587
1588         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1589
1590 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1591
1592         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1593         if FETCH_DATA returns 0.
1594         (m68k_scan_mask): Likewise.
1595         (print_insn_m68k): Update code to handle -1 return value.
1596
1597 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1598
1599         * m68k-dis.c (enum print_insn_arg_error): New.
1600         (NEXTBYTE): Replace -3 with
1601         PRINT_INSN_ARG_MEMORY_ERROR.
1602         (NEXTULONG): Likewise.
1603         (NEXTSINGLE): Likewise.
1604         (NEXTDOUBLE): Likewise.
1605         (NEXTDOUBLE): Likewise.
1606         (NEXTPACKED): Likewise.
1607         (FETCH_ARG): Likewise.
1608         (FETCH_DATA): Update comments.
1609         (print_insn_arg): Update comments. Replace magic numbers with
1610         enum.
1611         (match_insn_m68k): Likewise.
1612
1613 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1614
1615         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1616         * i386-dis-evex.h (evex_table): Updated.
1617         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1618         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1619         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1620         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1621         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1622         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1623         * i386-init.h: Regenerate.
1624         * i386-tbl.h: Ditto.
1625
1626 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1627
1628         * msp430-dis.c (msp430_singleoperand): Return -1 if
1629         msp430dis_opcode_signed returns false.
1630         (msp430_doubleoperand): Likewise.
1631         (msp430_branchinstr): Return -1 if
1632         msp430dis_opcode_unsigned returns false.
1633         (msp430x_calla_instr): Likewise.
1634         (print_insn_msp430): Likewise.
1635
1636 2017-01-05  Nick Clifton  <nickc@redhat.com>
1637
1638         PR 20946
1639         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1640         could not be matched.
1641         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1642         NULL.
1643
1644 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1645
1646         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1647         (aarch64_opcode_table): Use RCPC_INSN.
1648
1649 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1650
1651         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1652         extension.
1653         * riscv-opcodes/all-opcodes: Likewise.
1654
1655 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1656
1657         * riscv-dis.c (print_insn_args): Add fall through comment.
1658
1659 2017-01-03  Nick Clifton  <nickc@redhat.com>
1660
1661         * po/sr.po: New Serbian translation.
1662         * configure.ac (ALL_LINGUAS): Add sr.
1663         * configure: Regenerate.
1664
1665 2017-01-02  Alan Modra  <amodra@gmail.com>
1666
1667         * epiphany-desc.h: Regenerate.
1668         * epiphany-opc.h: Regenerate.
1669         * fr30-desc.h: Regenerate.
1670         * fr30-opc.h: Regenerate.
1671         * frv-desc.h: Regenerate.
1672         * frv-opc.h: Regenerate.
1673         * ip2k-desc.h: Regenerate.
1674         * ip2k-opc.h: Regenerate.
1675         * iq2000-desc.h: Regenerate.
1676         * iq2000-opc.h: Regenerate.
1677         * lm32-desc.h: Regenerate.
1678         * lm32-opc.h: Regenerate.
1679         * m32c-desc.h: Regenerate.
1680         * m32c-opc.h: Regenerate.
1681         * m32r-desc.h: Regenerate.
1682         * m32r-opc.h: Regenerate.
1683         * mep-desc.h: Regenerate.
1684         * mep-opc.h: Regenerate.
1685         * mt-desc.h: Regenerate.
1686         * mt-opc.h: Regenerate.
1687         * or1k-desc.h: Regenerate.
1688         * or1k-opc.h: Regenerate.
1689         * xc16x-desc.h: Regenerate.
1690         * xc16x-opc.h: Regenerate.
1691         * xstormy16-desc.h: Regenerate.
1692         * xstormy16-opc.h: Regenerate.
1693
1694 2017-01-02  Alan Modra  <amodra@gmail.com>
1695
1696         Update year range in copyright notice of all files.
1697
1698 For older changes see ChangeLog-2016
1699 \f
1700 Copyright (C) 2017 Free Software Foundation, Inc.
1701
1702 Copying and distribution of this file, with or without modification,
1703 are permitted in any medium without royalty provided the copyright
1704 notice and this notice are preserved.
1705
1706 Local Variables:
1707 mode: change-log
1708 left-margin: 8
1709 fill-column: 74
1710 version-control: never
1711 End: