opcodes/ChangeLog

   1 2016-12-01  Nick Clifton  <nickc@redhat.com>
   2
   3         PR binutils/20893
   4         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
   5         opcode designator.
   6
   7 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
   8
   9         * arc-opc.c (insert_ra_chk): New function.
  10         (insert_rb_chk): Likewise.
  11         (insert_rad): Update text error message.
  12         (insert_rcd): Likewise.
  13         (insert_rhv2): Likewise.
  14         (insert_r0): Likewise.
  15         (insert_r1): Likewise.
  16         (insert_r2): Likewise.
  17         (insert_r3): Likewise.
  18         (insert_sp): Likewise.
  19         (insert_gp): Likewise.
  20         (insert_pcl): Likewise.
  21         (insert_blink): Likewise.
  22         (insert_ilink1): Likewise.
  23         (insert_ilink2): Likewise.
  24         (insert_ras): Likewise.
  25         (insert_rbs): Likewise.
  26         (insert_rcs): Likewise.
  27         (insert_simm3s): Likewise.
  28         (insert_rrange): Likewise.
  29         (insert_fpel): Likewise.
  30         (insert_blinkel): Likewise.
  31         (insert_pcel): Likewise.
  32         (insert_nps_3bit_dst): Likewise.
  33         (insert_nps_3bit_dst_short): Likewise.
  34         (insert_nps_3bit_src2_short): Likewise.
  35         (insert_nps_bitop_size_2b): Likewise.
  36         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
  37         (RA_CHK): Define.
  38         (RB): Adjust.
  39         (RB_CHK): Define.
  40         (RC): Adjust.
  41         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
  42         * arc-tbl.h (div, divu): All instructions are DIVREM class.
  43         Change first insn argument to check for LP_COUNT usage.
  44         (rem): Likewise.
  45         (ld, ldd): All instructions are LOAD class.  Change first insn
  46         argument to check for LP_COUNT usage.
  47         (st, std): All instructions are STORE class.
  48         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
  49         Change first insn argument to check for LP_COUNT usage.
  50         (mov): All instructions are MOVE class.  Change first insn
  51         argument to check for LP_COUNT usage.
  52
  53 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  54
  55         * arc-dis.c (is_compatible_p): Remove function.
  56         (skip_this_opcode): Don't add any decoding class to decode list.
  57         Remove warning.
  58         (find_format_from_table): Go through all opcodes, and warn if we
  59         use a guessed mnemonic.
  60
  61 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
  62             Amit Pawar  <amit.pawar@amd.com>
  63
  64         PR binutils/20637
  65         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
  66         instructions.
  67
  68 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
  69
  70         * configure: Regenerate.
  71
  72 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  73
  74         * sparc-opc.c (HWS_V8): Definition moved from
  75         gas/config/tc-sparc.c.
  76         (HWS_V9): Likewise.
  77         (HWS_VA): Likewise.
  78         (HWS_VB): Likewise.
  79         (HWS_VC): Likewise.
  80         (HWS_VD): Likewise.
  81         (HWS_VE): Likewise.
  82         (HWS_VV): Likewise.
  83         (HWS_VM): Likewise.
  84         (HWS2_VM): Likewise.
  85         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
  86         existing entries.
  87
  88 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  89
  90         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
  91         instructions.
  92
  93 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  94
  95         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
  96         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
  97         (aarch64_opcode_table): Add fcmla and fcadd.
  98         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
  99         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 100         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 101         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 102         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 103         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 104         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 105         (operand_general_constraint_met_p): Rotate and index range check.
 106         (aarch64_print_operand): Handle rotate operand.
 107         * aarch64-asm-2.c: Regenerate.
 108         * aarch64-dis-2.c: Likewise.
 109         * aarch64-opc-2.c: Likewise.
 110
 111 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 112
 113         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 114         * aarch64-asm-2.c: Regenerate.
 115         * aarch64-dis-2.c: Regenerate.
 116         * aarch64-opc-2.c: Regenerate.
 117
 118 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 119
 120         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 121         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 122         * aarch64-asm-2.c: Regenerate.
 123         * aarch64-dis-2.c: Regenerate.
 124         * aarch64-opc-2.c: Regenerate.
 125
 126 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 127
 128         * aarch64-tbl.h (QL_X1NIL): New.
 129         (arch64_opcode_table): Add ldraa, ldrab.
 130         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 131         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 132         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 133         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 134         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 135         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 136         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 137         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 138         (aarch64_print_operand): Likewise.
 139         * aarch64-asm-2.c: Regenerate.
 140         * aarch64-dis-2.c: Regenerate.
 141         * aarch64-opc-2.c: Regenerate.
 142
 143 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 144
 145         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 146         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 147         * aarch64-asm-2.c: Regenerate.
 148         * aarch64-dis-2.c: Regenerate.
 149         * aarch64-opc-2.c: Regenerate.
 150
 151 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 152
 153         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 154         (AARCH64_OPERANDS): Add Rm_SP.
 155         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 156         * aarch64-asm-2.c: Regenerate.
 157         * aarch64-dis-2.c: Regenerate.
 158         * aarch64-opc-2.c: Regenerate.
 159
 160 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 161
 162         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 163         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 164         autdzb, xpaci, xpacd.
 165         * aarch64-asm-2.c: Regenerate.
 166         * aarch64-dis-2.c: Regenerate.
 167         * aarch64-opc-2.c: Regenerate.
 168
 169 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 170
 171         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 172         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 173         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 174         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 175
 176 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 177
 178         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 179         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 180         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 181         autibsp.
 182         * aarch64-asm-2.c: Regenerate.
 183         * aarch64-dis-2.c: Regenerate.
 184
 185 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 186
 187         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 188
 189 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 190
 191         PR binutils/20799
 192         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 193         * i386-dis.c (EdqwS): Removed.
 194         (dqw_swap_mode): Likewise.
 195         (intel_operand_size): Don't check dqw_swap_mode.
 196         (OP_E_register): Likewise.
 197         (OP_E_memory): Likewise.
 198         (OP_G): Likewise.
 199         (OP_EX): Likewise.
 200         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 201         * i386-tbl.h: Regerated.
 202
 203 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 204
 205         * i386-opc.tbl: Merge AVX512F vmovq.
 206         * i386-tbl.h: Regerated.
 207
 208 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 209
 210         PR binutils/20701
 211         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 212         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 213         (three_byte_table): Remove THREE_BYTE_0F7A.
 214
 215 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         PR binutils/20775
 218         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 219         (FGRPd9_4): Replace 1 with 2.
 220         (FGRPd9_5): Replace 2 with 3.
 221         (FGRPd9_6): Replace 3 with 4.
 222         (FGRPd9_7): Replace 4 with 5.
 223         (FGRPda_5): Replace 5 with 6.
 224         (FGRPdb_4): Replace 6 with 7.
 225         (FGRPde_3): Replace 7 with 8.
 226         (FGRPdf_4): Replace 8 with 9.
 227         (fgrps): Add an entry for Bad_Opcode.
 228
 229 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 230
 231         * arc-opc.c (arc_flag_operands): Add F_DI14.
 232         (arc_flag_classes): Add C_DI14.
 233         * arc-nps400-tbl.h: Add new exc instructions.
 234
 235 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 236
 237         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 238         major opcode 0xa.
 239         * arc-nps-400-tbl.h: Add dcmac instruction.
 240         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 241         (insert_nps_rbdouble_64): Added.
 242         (extract_nps_rbdouble_64): Added.
 243         (insert_nps_proto_size): Added.
 244         (extract_nps_proto_size): Added.
 245
 246 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 247
 248         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 249         relating to long instruction processing, add new limm field.
 250         (OPCODE): Rename to...
 251         (OPCODE_32BIT_INSN): ...this.
 252         (OPCODE_AC): Delete.
 253         (skip_this_opcode): Handle different instruction lengths, update
 254         macro name.
 255         (special_flag_p): Update parameter type.
 256         (find_format_from_table): Update for more instruction lengths.
 257         (find_format_long_instructions): Delete.
 258         (find_format): Update for more instruction lengths.
 259         (arc_insn_length): Likewise.
 260         (extract_operand_value): Update for more instruction lengths.
 261         (operand_iterator_next): Remove code relating to long
 262         instructions.
 263         (arc_opcode_to_insn_type): New function.
 264         (print_insn_arc):Update for more instructions lengths.
 265         * arc-ext.c (extInstruction_t): Change argument type.
 266         * arc-ext.h (extInstruction_t): Change argument type.
 267         * arc-fxi.h: Change type unsigned to unsigned long long
 268         extensively throughout.
 269         * arc-nps400-tbl.h: Add long instructions taken from
 270         arc_long_opcodes table in arc-opc.c.
 271         * arc-opc.c: Update parameter types on insert/extract handlers.
 272         (arc_long_opcodes): Delete.
 273         (arc_num_long_opcodes): Delete.
 274         (arc_opcode_len): Update for more instruction lengths.
 275
 276 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 277
 278         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 279
 280 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 281
 282         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 283         with arc_opcode_len.
 284         (find_format_long_instructions): Likewise.
 285         * arc-opc.c (arc_opcode_len): New function.
 286
 287 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 288
 289         * arc-nps400-tbl.h: Fix some instruction masks.
 290
 291 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 292
 293         * i386-dis.c (REG_82): Removed.
 294         (X86_64_82_REG_0): Likewise.
 295         (X86_64_82_REG_1): Likewise.
 296         (X86_64_82_REG_2): Likewise.
 297         (X86_64_82_REG_3): Likewise.
 298         (X86_64_82_REG_4): Likewise.
 299         (X86_64_82_REG_5): Likewise.
 300         (X86_64_82_REG_6): Likewise.
 301         (X86_64_82_REG_7): Likewise.
 302         (X86_64_82): New.
 303         (dis386): Use X86_64_82 instead of REG_82.
 304         (reg_table): Remove REG_82.
 305         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 306         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 307         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 308         X86_64_82_REG_7.
 309
 310 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 311
 312         PR binutils/20754
 313         * i386-dis.c (REG_82): New.
 314         (X86_64_82_REG_0): Likewise.
 315         (X86_64_82_REG_1): Likewise.
 316         (X86_64_82_REG_2): Likewise.
 317         (X86_64_82_REG_3): Likewise.
 318         (X86_64_82_REG_4): Likewise.
 319         (X86_64_82_REG_5): Likewise.
 320         (X86_64_82_REG_6): Likewise.
 321         (X86_64_82_REG_7): Likewise.
 322         (dis386): Use REG_82.
 323         (reg_table): Add REG_82.
 324         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 325         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 326         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 327
 328 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         * i386-dis.c (REG_82): Renamed to ...
 331         (REG_83): This.
 332         (dis386): Updated.
 333         (reg_table): Likewise.
 334
 335 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 336
 337         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 338         * i386-dis-evex.h (evex_table): Updated.
 339         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 340         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 341         (cpu_flags): Add CpuAVX512_4VNNIW.
 342         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 343         (i386_cpu_flags): Add cpuavx512_4vnniw.
 344         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 345         * i386-init.h: Regenerate.
 346         * i386-tbl.h: Ditto.
 347
 348 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 349
 350         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 351         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 352         * i386-dis-evex.h (evex_table): Updated.
 353         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 354         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 355         (cpu_flags): Add CpuAVX512_4FMAPS.
 356         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 357         * i386-opc.h (AVX512_4FMAP): New.
 358         (i386_cpu_flags): Add cpuavx512_4fmaps.
 359         (ImplicitQuadGroup): New.
 360         (i386_opcode_modifier): Add implicitquadgroup.
 361         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 362         * i386-init.h: Regenerate.
 363         * i386-tbl.h: Ditto.
 364
 365 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 366             Andrew Waterman <andrew@sifive.com>
 367
 368         Add support for RISC-V architecture.
 369         * configure.ac: Add entry for bfd_riscv_arch.
 370         * configure: Regenerate.
 371         * disassemble.c (disassembler): Add support for riscv.
 372         (disassembler_usage): Likewise.
 373         * riscv-dis.c: New file.
 374         * riscv-opc.c: New file.
 375
 376 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 377
 378         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 379         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 380         (rm_table): Update the RM_0FAE_REG_7 entry.
 381         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 382         (cpu_flags): Remove CpuPCOMMIT.
 383         * i386-opc.h (CpuPCOMMIT): Removed.
 384         (i386_cpu_flags): Remove cpupcommit.
 385         * i386-opc.tbl: Remove pcommit.
 386         * i386-init.h: Regenerated.
 387         * i386-tbl.h: Likewise.
 388
 389 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 390
 391         PR binutis/20705
 392         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 393         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 394         32-bit mode.  Don't check vex.register_specifier in 32-bit
 395         mode.
 396         (OP_VEX): Check for invalid mask registers.
 397
 398 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 399
 400         PR binutis/20699
 401         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 402         sizeflag.
 403
 404 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 405
 406         PR binutis/20704
 407         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 408
 409 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 410
 411         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 412         local variable to `index_regno'.
 413
 414 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 415
 416         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 417
 418 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 419
 420         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 421         usage on ISA basis.
 422
 423 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 424
 425         PR target/20666
 426         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 427
 428 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 429
 430         PR target/20667
 431         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 432         available.
 433
 434 2016-10-07  Alan Modra  <amodra@gmail.com>
 435
 436         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 437
 438 2016-10-06  Alan Modra  <amodra@gmail.com>
 439
 440         * aarch64-opc.c: Spell fall through comments consistently.
 441         * i386-dis.c: Likewise.
 442         * aarch64-dis.c: Add missing fall through comments.
 443         * aarch64-opc.c: Likewise.
 444         * arc-dis.c: Likewise.
 445         * arm-dis.c: Likewise.
 446         * i386-dis.c: Likewise.
 447         * m68k-dis.c: Likewise.
 448         * mep-asm.c: Likewise.
 449         * ns32k-dis.c: Likewise.
 450         * sh-dis.c: Likewise.
 451         * tic4x-dis.c: Likewise.
 452         * tic6x-dis.c: Likewise.
 453         * vax-dis.c: Likewise.
 454
 455 2016-10-06  Alan Modra  <amodra@gmail.com>
 456
 457         * arc-ext.c (create_map): Add missing break.
 458         * msp430-decode.opc (encode_as): Likewise.
 459         * msp430-decode.c: Regenerate.
 460
 461 2016-10-06  Alan Modra  <amodra@gmail.com>
 462
 463         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 464         * crx-dis.c (print_insn_crx): Likewise.
 465
 466 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 467
 468         PR binutils/20657
 469         * i386-dis.c (putop): Don't assign alt twice.
 470
 471 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 472
 473         PR target/20553
 474         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 475
 476 2016-09-29  Alan Modra  <amodra@gmail.com>
 477
 478         * ppc-opc.c (L): Make compulsory.
 479         (LOPT): New, optional form of L.
 480         (HTM_R): Define as LOPT.
 481         (L0, L1): Delete.
 482         (L32OPT): New, optional for 32-bit L.
 483         (L2OPT): New, 2-bit L for dcbf.
 484         (SVC_LEC): Update.
 485         (L2): Define.
 486         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 487         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 488         <dcbf>: Use L2OPT.
 489         <tlbiel, tlbie>: Use LOPT.
 490         <wclr, wclrall>: Use L2.
 491
 492 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 493
 494         * Makefile.in: Regenerate.
 495         * configure: Likewise.
 496
 497 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 498
 499         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 500         (EXTINSN2OP): Use EXTINSN2OPF.
 501         (bspeekm, bspop, modapp): New extension instructions.
 502         * arc-opc.c (F_DNZ_ND): Define.
 503         (F_DNZ_D): Likewise.
 504         (F_SIZEB1): Changed.
 505         (C_DNZ_D): Define.
 506         (C_HARD): Changed.
 507         * arc-tbl.h (dbnz): New instruction.
 508         (prealloc): Allow it for ARC EM.
 509         (xbfu): Likewise.
 510
 511 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 512
 513         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 514         after commas in addresses.
 515         (aarch64_print_operand): Likewise.
 516
 517 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 518
 519         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 520         rather than "should be" or "expected to be" in error messages.
 521
 522 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 523
 524         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 525         (print_mnemonic_name): ...here.
 526         (print_comment): New function.
 527         (print_aarch64_insn): Call it.
 528         * aarch64-opc.c (aarch64_conds): Add SVE names.
 529         (aarch64_print_operand): Print alternative condition names in
 530         a comment.
 531
 532 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 533
 534         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 535         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 536         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 537         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 538         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 539         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 540         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 541         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 542         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 543         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 544         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 545         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 546         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 547         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 548         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 549         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 550         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 551         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 552         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 553         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 554         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 555         (aarch64_feature_sve): New variable.
 556         (SVE): New macro.
 557         (_SVE_INSN): Likewise.
 558         (aarch64_opcode_table): Add SVE instructions.
 559         * aarch64-opc.h (extract_fields): Declare.
 560         * aarch64-opc-2.c: Regenerate.
 561         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 562         * aarch64-asm-2.c: Regenerate.
 563         * aarch64-dis.c (extract_fields): Make global.
 564         (do_misc_decoding): Handle the new SVE aarch64_ops.
 565         * aarch64-dis-2.c: Regenerate.
 566
 567 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 568
 569         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 570         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 571         aarch64_field_kinds.
 572         * aarch64-opc.c (fields): Add corresponding entries.
 573         * aarch64-asm.c (aarch64_get_variant): New function.
 574         (aarch64_encode_variant_using_iclass): Likewise.
 575         (aarch64_opcode_encode): Call it.
 576         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 577         (aarch64_opcode_decode): Call it.
 578
 579 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 580
 581         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 582         and FP register operands.
 583         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 584         (FLD_SVE_Vn): New aarch64_field_kinds.
 585         * aarch64-opc.c (fields): Add corresponding entries.
 586         (aarch64_print_operand): Handle the new SVE core and FP register
 587         operands.
 588         * aarch64-opc-2.c: Regenerate.
 589         * aarch64-asm-2.c: Likewise.
 590         * aarch64-dis-2.c: Likewise.
 591
 592 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 593
 594         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 595         immediate operands.
 596         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 597         * aarch64-opc.c (fields): Add corresponding entry.
 598         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 599         operands.
 600         (aarch64_print_operand): Likewise.
 601         * aarch64-opc-2.c: Regenerate.
 602         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 603         (ins_sve_float_zero_one): New inserters.
 604         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 605         (aarch64_ins_sve_float_half_two): Likewise.
 606         (aarch64_ins_sve_float_zero_one): Likewise.
 607         * aarch64-asm-2.c: Regenerate.
 608         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 609         (ext_sve_float_zero_one): New extractors.
 610         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 611         (aarch64_ext_sve_float_half_two): Likewise.
 612         (aarch64_ext_sve_float_zero_one): Likewise.
 613         * aarch64-dis-2.c: Regenerate.
 614
 615 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 616
 617         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 618         integer immediate operands.
 619         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 620         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 621         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 622         * aarch64-opc.c (fields): Add corresponding entries.
 623         (operand_general_constraint_met_p): Handle the new SVE integer
 624         immediate operands.
 625         (aarch64_print_operand): Likewise.
 626         (aarch64_sve_dupm_mov_immediate_p): New function.
 627         * aarch64-opc-2.c: Regenerate.
 628         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 629         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 630         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 631         (aarch64_ins_limm): ...here.
 632         (aarch64_ins_inv_limm): New function.
 633         (aarch64_ins_sve_aimm): Likewise.
 634         (aarch64_ins_sve_asimm): Likewise.
 635         (aarch64_ins_sve_limm_mov): Likewise.
 636         (aarch64_ins_sve_shlimm): Likewise.
 637         (aarch64_ins_sve_shrimm): Likewise.
 638         * aarch64-asm-2.c: Regenerate.
 639         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 640         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 641         * aarch64-dis.c (decode_limm): New function, split out from...
 642         (aarch64_ext_limm): ...here.
 643         (aarch64_ext_inv_limm): New function.
 644         (decode_sve_aimm): Likewise.
 645         (aarch64_ext_sve_aimm): Likewise.
 646         (aarch64_ext_sve_asimm): Likewise.
 647         (aarch64_ext_sve_limm_mov): Likewise.
 648         (aarch64_top_bit): Likewise.
 649         (aarch64_ext_sve_shlimm): Likewise.
 650         (aarch64_ext_sve_shrimm): Likewise.
 651         * aarch64-dis-2.c: Regenerate.
 652
 653 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 654
 655         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 656         operands.
 657         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 658         the AARCH64_MOD_MUL_VL entry.
 659         (value_aligned_p): Cope with non-power-of-two alignments.
 660         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 661         (print_immediate_offset_address): Likewise.
 662         (aarch64_print_operand): Likewise.
 663         * aarch64-opc-2.c: Regenerate.
 664         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 665         (ins_sve_addr_ri_s9xvl): New inserters.
 666         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 667         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 668         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 669         * aarch64-asm-2.c: Regenerate.
 670         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 671         (ext_sve_addr_ri_s9xvl): New extractors.
 672         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 673         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 674         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 675         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 676         * aarch64-dis-2.c: Regenerate.
 677
 678 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 679
 680         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 681         address operands.
 682         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 683         (FLD_SVE_xs_22): New aarch64_field_kinds.
 684         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 685         (get_operand_specific_data): New function.
 686         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 687         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 688         (operand_general_constraint_met_p): Handle the new SVE address
 689         operands.
 690         (sve_reg): New array.
 691         (get_addr_sve_reg_name): New function.
 692         (aarch64_print_operand): Handle the new SVE address operands.
 693         * aarch64-opc-2.c: Regenerate.
 694         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 695         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 696         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 697         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 698         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 699         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 700         (aarch64_ins_sve_addr_zi_u5): Likewise.
 701         (aarch64_ins_sve_addr_zz): Likewise.
 702         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 703         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 704         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 705         * aarch64-asm-2.c: Regenerate.
 706         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 707         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 708         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 709         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 710         (aarch64_ext_sve_addr_ri_u6): Likewise.
 711         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 712         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 713         (aarch64_ext_sve_addr_zi_u5): Likewise.
 714         (aarch64_ext_sve_addr_zz): Likewise.
 715         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 716         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 717         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 718         * aarch64-dis-2.c: Regenerate.
 719
 720 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 721
 722         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 723         AARCH64_OPND_SVE_PATTERN_SCALED.
 724         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 725         * aarch64-opc.c (fields): Add a corresponding entry.
 726         (set_multiplier_out_of_range_error): New function.
 727         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 728         (operand_general_constraint_met_p): Handle
 729         AARCH64_OPND_SVE_PATTERN_SCALED.
 730         (print_register_offset_address): Use PRIi64 to print the
 731         shift amount.
 732         (aarch64_print_operand): Likewise.  Handle
 733         AARCH64_OPND_SVE_PATTERN_SCALED.
 734         * aarch64-opc-2.c: Regenerate.
 735         * aarch64-asm.h (ins_sve_scale): New inserter.
 736         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 737         * aarch64-asm-2.c: Regenerate.
 738         * aarch64-dis.h (ext_sve_scale): New inserter.
 739         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 740         * aarch64-dis-2.c: Regenerate.
 741
 742 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 743
 744         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 745         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 746         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 747         (FLD_SVE_prfop): Likewise.
 748         * aarch64-opc.c: Include libiberty.h.
 749         (aarch64_sve_pattern_array): New variable.
 750         (aarch64_sve_prfop_array): Likewise.
 751         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 752         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 753         AARCH64_OPND_SVE_PRFOP.
 754         * aarch64-asm-2.c: Regenerate.
 755         * aarch64-dis-2.c: Likewise.
 756         * aarch64-opc-2.c: Likewise.
 757
 758 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 759
 760         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 761         AARCH64_OPND_QLF_P_[ZM].
 762         (aarch64_print_operand): Print /z and /m where appropriate.
 763
 764 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 765
 766         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 767         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 768         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 769         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 770         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 771         * aarch64-opc.c (fields): Add corresponding entries here.
 772         (operand_general_constraint_met_p): Check that SVE register lists
 773         have the correct length.  Check the ranges of SVE index registers.
 774         Check for cases where p8-p15 are used in 3-bit predicate fields.
 775         (aarch64_print_operand): Handle the new SVE operands.
 776         * aarch64-opc-2.c: Regenerate.
 777         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 778         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 779         (aarch64_ins_sve_reglist): Likewise.
 780         * aarch64-asm-2.c: Regenerate.
 781         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 782         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 783         (aarch64_ext_sve_reglist): Likewise.
 784         * aarch64-dis-2.c: Regenerate.
 785
 786 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 787
 788         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 789         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 790         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 791         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 792         tied operands.
 793
 794 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 795
 796         * aarch64-opc.c (get_offset_int_reg_name): New function.
 797         (print_immediate_offset_address): Likewise.
 798         (print_register_offset_address): Take the base and offset
 799         registers as parameters.
 800         (aarch64_print_operand): Update caller accordingly.  Use
 801         print_immediate_offset_address.
 802
 803 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 804
 805         * aarch64-opc.c (BANK): New macro.
 806         (R32, R64): Take a register number as argument
 807         (int_reg): Use BANK.
 808
 809 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 810
 811         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 812         (aarch64_print_operand): Update accordingly.
 813
 814 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 815
 816         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 817         for FPIMM.
 818         * aarch64-asm.h (ins_fpimm): New inserter.
 819         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 820         * aarch64-asm-2.c: Regenerate.
 821         * aarch64-dis.h (ext_fpimm): New extractor.
 822         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 823         (aarch64_ext_fpimm): New function.
 824         * aarch64-dis-2.c: Regenerate.
 825
 826 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 827
 828         * aarch64-asm.c: Include libiberty.h.
 829         (insert_fields): New function.
 830         (aarch64_ins_imm): Use it.
 831         * aarch64-dis.c (extract_fields): New function.
 832         (aarch64_ext_imm): Use it.
 833
 834 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 835
 836         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 837         with an esize parameter.
 838         (operand_general_constraint_met_p): Update accordingly.
 839         Fix misindented code.
 840         * aarch64-asm.c (aarch64_ins_limm): Update call to
 841         aarch64_logical_immediate_p.
 842
 843 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 844
 845         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 846
 847 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 848
 849         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 850
 851 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 852
 853         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 854
 855 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 856
 857         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 858         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 859         xor3>: Delete mnemonics.
 860         <cp_abort>: Rename mnemonic from ...
 861         <cpabort>: ...to this.
 862         <setb>: Change to a X form instruction.
 863         <sync>: Change to 1 operand form.
 864         <copy>: Delete mnemonic.
 865         <copy_first>: Rename mnemonic from ...
 866         <copy>: ...to this.
 867         <paste, paste.>: Delete mnemonics.
 868         <paste_last>: Rename mnemonic from ...
 869         <paste.>: ...to this.
 870
 871 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 872
 873         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 874
 875 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 876
 877         * s390-mkopc.c (main): Support alternate arch strings.
 878
 879 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 880
 881         * s390-opc.txt: Fix kmctr instruction type.
 882
 883 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 884
 885         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 886         * i386-init.h: Regenerated.
 887
 888 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 889
 890         * opcodes/arc-dis.c (print_insn_arc): Changed.
 891
 892 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 893
 894         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 895         camellia_fl.
 896
 897 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 898
 899         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 900         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 901         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 902
 903 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 904
 905         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 906         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 907         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 908         PREFIX_MOD_3_0FAE_REG_4.
 909         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 910         PREFIX_MOD_3_0FAE_REG_4.
 911         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 912         (cpu_flags): Add CpuPTWRITE.
 913         * i386-opc.h (CpuPTWRITE): New.
 914         (i386_cpu_flags): Add cpuptwrite.
 915         * i386-opc.tbl: Add ptwrite instruction.
 916         * i386-init.h: Regenerated.
 917         * i386-tbl.h: Likewise.
 918
 919 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 920
 921         * arc-dis.h: Wrap around in extern "C".
 922
 923 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 924
 925         * aarch64-tbl.h (V8_2_INSN): New macro.
 926         (aarch64_opcode_table): Use it.
 927
 928 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 929
 930         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 931         CORE_INSN, __FP_INSN and SIMD_INSN.
 932
 933 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 934
 935         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 936         (aarch64_opcode_table): Update uses accordingly.
 937
 938 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 939         Kwok Cheung Yeung  <kcy@codesourcery.com>
 940
 941         opcodes/
 942         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 943         'e_cmplwi' to 'e_cmpli' instead.
 944         (OPVUPRT, OPVUPRT_MASK): Define.
 945         (powerpc_opcodes): Add E200Z4 insns.
 946         (vle_opcodes): Add context save/restore insns.
 947
 948 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 949
 950         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 951         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 952         "j".
 953
 954 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 955
 956         * arc-nps400-tbl.h: Change block comments to GNU format.
 957         * arc-dis.c: Add new globals addrtypenames,
 958         addrtypenames_max, and addtypeunknown.
 959         (get_addrtype): New function.
 960         (print_insn_arc): Print colons and address types when
 961         required.
 962         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 963         define insert and extract functions for all address types.
 964         (arc_operands): Add operands for colon and all address
 965         types.
 966         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 967         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 968         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 969         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 970         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 971         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 972
 973 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 974
 975         * configure: Regenerated.
 976
 977 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 978
 979         * arc-dis.c (skipclass): New structure.
 980         (decodelist): New variable.
 981         (is_compatible_p): New function.
 982         (new_element): Likewise.
 983         (skip_class_p): Likewise.
 984         (find_format_from_table): Use skip_class_p function.
 985         (find_format): Decode first the extension instructions.
 986         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 987         e_flags.
 988         (parse_option): New function.
 989         (parse_disassembler_options): Likewise.
 990         (print_arc_disassembler_options): Likewise.
 991         (print_insn_arc): Use parse_disassembler_options function.  Proper
 992         select ARCv2 cpu variant.
 993         * disassemble.c (disassembler_usage): Add ARC disassembler
 994         options.
 995
 996 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 997
 998         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 999         annotation from the "nal" entry and reorder it beyond "bltzal".
1000
1001 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1002
1003         * sparc-opc.c (ldtxa): New macro.
1004         (sparc_opcodes): Use the macro defined above to add entries for
1005         the LDTXA instructions.
1006         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1007         instruction.
1008
1009 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1010
1011         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1012         and "jmpc".
1013
1014 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1017         (movzb): Adjust to cover all permitted suffixes.
1018         (movzw): New.
1019         * i386-tbl.h: Re-generate.
1020
1021 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1024         (lgdt): Remove Tbyte from non-64-bit variant.
1025         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1026         xsaves64, xsavec64): Remove Disp16.
1027         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1028         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1029         64-bit variants.
1030         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1031         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1032         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1033         64-bit variants.
1034         * i386-tbl.h: Re-generate.
1035
1036 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1039         * i386-tbl.h: Re-generate.
1040
1041 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1042
1043         * arm-dis.c (print_insn): Fix typo in comment.
1044
1045 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1046
1047         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1048         range of ldst_elemlist operands.
1049         (print_register_list): Use PRIi64 to print the index.
1050         (aarch64_print_operand): Likewise.
1051
1052 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1053
1054         * mcore-opc.h: Remove sentinal.
1055         * mcore-dis.c (print_insn_mcore): Adjust.
1056
1057 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1058
1059         * arc-opc.c: Correct description of availability of NPS400
1060         features.
1061
1062 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1063
1064         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1065         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1066         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1067         xor3>: New mnemonics.
1068         <setb>: Change to a VX form instruction.
1069         (insert_sh6): Add support for rldixor.
1070         (extract_sh6): Likewise.
1071
1072 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1073
1074         * arc-ext.h: Wrap in extern C.
1075
1076 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1077
1078         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1079         Use same method for determining instruction length on ARC700 and
1080         NPS-400.
1081         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1082         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1083         with the NPS400 subclass.
1084         * arc-opc.c: Likewise.
1085
1086 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1087
1088         * sparc-opc.c (rdasr): New macro.
1089         (wrasr): Likewise.
1090         (rdpr): Likewise.
1091         (wrpr): Likewise.
1092         (rdhpr): Likewise.
1093         (wrhpr): Likewise.
1094         (sparc_opcodes): Use the macros above to fix and expand the
1095         definition of read/write instructions from/to
1096         asr/privileged/hyperprivileged instructions.
1097         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1098         %hva_mask_nz.  Prefer softint_set and softint_clear over
1099         set_softint and clear_softint.
1100         (print_insn_sparc): Support %ver in Rd.
1101
1102 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1103
1104         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1105         architecture according to the hardware capabilities they require.
1106
1107 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1108
1109         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1110         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1111         bfd_mach_sparc_v9{c,d,e,v,m}.
1112         * sparc-opc.c (MASK_V9C): Define.
1113         (MASK_V9D): Likewise.
1114         (MASK_V9E): Likewise.
1115         (MASK_V9V): Likewise.
1116         (MASK_V9M): Likewise.
1117         (v6): Add MASK_V9{C,D,E,V,M}.
1118         (v6notlet): Likewise.
1119         (v7): Likewise.
1120         (v8): Likewise.
1121         (v9): Likewise.
1122         (v9andleon): Likewise.
1123         (v9a): Likewise.
1124         (v9b): Likewise.
1125         (v9c): Define.
1126         (v9d): Likewise.
1127         (v9e): Likewise.
1128         (v9v): Likewise.
1129         (v9m): Likewise.
1130         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1131
1132 2016-06-15  Nick Clifton  <nickc@redhat.com>
1133
1134         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1135         constants to match expected behaviour.
1136         (nds32_parse_opcode): Likewise.  Also for whitespace.
1137
1138 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1139
1140         * arc-opc.c (extract_rhv1): Extract value from insn.
1141
1142 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1143
1144         * arc-nps400-tbl.h: Add ldbit instruction.
1145         * arc-opc.c: Add flag classes required for ldbit.
1146
1147 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1148
1149         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1150         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1151         support the above instructions.
1152
1153 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1154
1155         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1156         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1157         csma, cbba, zncv, and hofs.
1158         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1159         support the above instructions.
1160
1161 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1162
1163         * arc-nps400-tbl.h: Add andab and orab instructions.
1164
1165 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1166
1167         * arc-nps400-tbl.h: Add addl-like instructions.
1168
1169 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1170
1171         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1172
1173 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1174
1175         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1176         instructions.
1177
1178 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1179
1180         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1181         variable.
1182         (init_disasm): Handle new command line option "insnlength".
1183         (print_s390_disassembler_options): Mention new option in help
1184         output.
1185         (print_insn_s390): Use the encoded insn length when dumping
1186         unknown instructions.
1187
1188 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1189
1190         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1191          to the address and set as symbol address for LDS/ STS immediate operands.
1192
1193 2016-06-07  Alan Modra  <amodra@gmail.com>
1194
1195         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1196         cpu for "vle" to e500.
1197         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1198         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1199         (PPCNONE): Delete, substitute throughout.
1200         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1201         except for major opcode 4 and 31.
1202         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1203
1204 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1205
1206         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1207         ARM_EXT_RAS in relevant entries.
1208
1209 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1210
1211         PR binutils/20196
1212         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1213         opcodes for E6500.
1214
1215 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1216
1217         PR binutis/18386
1218         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1219         (indir_v_mode): New.
1220         Add comments for '&'.
1221         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1222         (putop): Handle '&'.
1223         (intel_operand_size): Handle indir_v_mode.
1224         (OP_E_register): Likewise.
1225         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1226         64-bit indirect call/jmp for AMD64.
1227         * i386-tbl.h: Regenerated
1228
1229 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1230
1231         * arc-dis.c (struct arc_operand_iterator): New structure.
1232         (find_format_from_table): All the old content from find_format,
1233         with some minor adjustments, and parameter renaming.
1234         (find_format_long_instructions): New function.
1235         (find_format): Rewritten.
1236         (arc_insn_length): Add LSB parameter.
1237         (extract_operand_value): New function.
1238         (operand_iterator_next): New function.
1239         (print_insn_arc): Use new functions to find opcode, and iterator
1240         over operands.
1241         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1242         (extract_nps_3bit_dst_short): New function.
1243         (insert_nps_3bit_src2_short): New function.
1244         (extract_nps_3bit_src2_short): New function.
1245         (insert_nps_bitop1_size): New function.
1246         (extract_nps_bitop1_size): New function.
1247         (insert_nps_bitop2_size): New function.
1248         (extract_nps_bitop2_size): New function.
1249         (insert_nps_bitop_mod4_msb): New function.
1250         (extract_nps_bitop_mod4_msb): New function.
1251         (insert_nps_bitop_mod4_lsb): New function.
1252         (extract_nps_bitop_mod4_lsb): New function.
1253         (insert_nps_bitop_dst_pos3_pos4): New function.
1254         (extract_nps_bitop_dst_pos3_pos4): New function.
1255         (insert_nps_bitop_ins_ext): New function.
1256         (extract_nps_bitop_ins_ext): New function.
1257         (arc_operands): Add new operands.
1258         (arc_long_opcodes): New global array.
1259         (arc_num_long_opcodes): New global.
1260         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1261
1262 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1263
1264         * nds32-asm.h: Add extern "C".
1265         * sh-opc.h: Likewise.
1266
1267 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1268
1269         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1270         0,b,limm to the rflt instruction.
1271
1272 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1273
1274         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1275         constant.
1276
1277 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1278
1279         PR gas/20145
1280         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1281         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1282         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1283         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1284         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1285         * i386-init.h: Regenerated.
1286
1287 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1288
1289         PR gas/20145
1290         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1291         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1292         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1293         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1294         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1295         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1296         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1297         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1298         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1299         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1300         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1301         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1302         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1303         CpuRegMask for AVX512.
1304         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1305         and CpuRegMask.
1306         (set_bitfield_from_cpu_flag_init): New function.
1307         (set_bitfield): Remove const on f.  Call
1308         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1309         * i386-opc.h (CpuRegMMX): New.
1310         (CpuRegXMM): Likewise.
1311         (CpuRegYMM): Likewise.
1312         (CpuRegZMM): Likewise.
1313         (CpuRegMask): Likewise.
1314         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1315         and cpuregmask.
1316         * i386-init.h: Regenerated.
1317         * i386-tbl.h: Likewise.
1318
1319 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1320
1321         PR gas/20154
1322         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1323         (opcode_modifiers): Add AMD64 and Intel64.
1324         (main): Properly verify CpuMax.
1325         * i386-opc.h (CpuAMD64): Removed.
1326         (CpuIntel64): Likewise.
1327         (CpuMax): Set to CpuNo64.
1328         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1329         (AMD64): New.
1330         (Intel64): Likewise.
1331         (i386_opcode_modifier): Add amd64 and intel64.
1332         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1333         on call and jmp.
1334         * i386-init.h: Regenerated.
1335         * i386-tbl.h: Likewise.
1336
1337 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1338
1339         PR gas/20154
1340         * i386-gen.c (main): Fail if CpuMax is incorrect.
1341         * i386-opc.h (CpuMax): Set to CpuIntel64.
1342         * i386-tbl.h: Regenerated.
1343
1344 2016-05-27  Nick Clifton  <nickc@redhat.com>
1345
1346         PR target/20150
1347         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1348         (msp430dis_opcode_unsigned): New function.
1349         (msp430dis_opcode_signed): New function.
1350         (msp430_singleoperand): Use the new opcode reading functions.
1351         Only disassenmble bytes if they were successfully read.
1352         (msp430_doubleoperand): Likewise.
1353         (msp430_branchinstr): Likewise.
1354         (msp430x_callx_instr): Likewise.
1355         (print_insn_msp430): Check that it is safe to read bytes before
1356         attempting disassembly.  Use the new opcode reading functions.
1357
1358 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1359
1360         * ppc-opc.c (CY): New define.  Document it.
1361         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1362
1363 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1364
1365         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1366         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1367         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1368         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1369         CPU_ANY_AVX_FLAGS.
1370         * i386-init.h: Regenerated.
1371
1372 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1373
1374         PR gas/20141
1375         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1376         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1377         * i386-init.h: Regenerated.
1378
1379 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1380
1381         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1382         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1383         * i386-init.h: Regenerated.
1384
1385 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1386
1387         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1388         information.
1389         (print_insn_arc): Set insn_type information.
1390         * arc-opc.c (C_CC): Add F_CLASS_COND.
1391         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1392         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1393         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1394         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1395         (brne, brne_s, jeq_s, jne_s): Likewise.
1396
1397 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1398
1399         * arc-tbl.h (neg): New instruction variant.
1400
1401 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1402
1403         * arc-dis.c (find_format, find_format, get_auxreg)
1404         (print_insn_arc): Changed.
1405         * arc-ext.h (INSERT_XOP): Likewise.
1406
1407 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1408
1409         * tic54x-dis.c (sprint_mmr): Adjust.
1410         * tic54x-opc.c: Likewise.
1411
1412 2016-05-19  Alan Modra  <amodra@gmail.com>
1413
1414         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1415
1416 2016-05-19  Alan Modra  <amodra@gmail.com>
1417
1418         * ppc-opc.c: Formatting.
1419         (NSISIGNOPT): Define.
1420         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1421
1422 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1423
1424         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1425         replacing references to `micromips_ase' throughout.
1426         (_print_insn_mips): Don't use file-level microMIPS annotation to
1427         determine the disassembly mode with the symbol table.
1428
1429 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1430
1431         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1432
1433 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1434
1435         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1436         mips64r6.
1437         * mips-opc.c (D34): New macro.
1438         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1439
1440 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1441
1442         * i386-dis.c (prefix_table): Add RDPID instruction.
1443         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1444         (cpu_flags): Add RDPID bitfield.
1445         * i386-opc.h (enum): Add RDPID element.
1446         (i386_cpu_flags): Add RDPID field.
1447         * i386-opc.tbl: Add RDPID instruction.
1448         * i386-init.h: Regenerate.
1449         * i386-tbl.h: Regenerate.
1450
1451 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1452
1453         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1454         branch type of a symbol.
1455         (print_insn): Likewise.
1456
1457 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1458
1459         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1460         Mainline Security Extensions instructions.
1461         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1462         Extensions instructions.
1463         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1464         instructions.
1465         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1466         special registers.
1467
1468 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1469
1470         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1471
1472 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1473
1474         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1475         (arcExtMap_genOpcode): Likewise.
1476         * arc-opc.c (arg_32bit_rc): Define new variable.
1477         (arg_32bit_u6): Likewise.
1478         (arg_32bit_limm): Likewise.
1479
1480 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1481
1482         * aarch64-gen.c (VERIFIER): Define.
1483         * aarch64-opc.c (VERIFIER): Define.
1484         (verify_ldpsw): Use static linkage.
1485         * aarch64-opc.h (verify_ldpsw): Remove.
1486         * aarch64-tbl.h: Use VERIFIER for verifiers.
1487
1488 2016-04-28  Nick Clifton  <nickc@redhat.com>
1489
1490         PR target/19722
1491         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1492         * aarch64-opc.c (verify_ldpsw): New function.
1493         * aarch64-opc.h (verify_ldpsw): New prototype.
1494         * aarch64-tbl.h: Add initialiser for verifier field.
1495         (LDPSW): Set verifier to verify_ldpsw.
1496
1497 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1498
1499         PR binutils/19983
1500         PR binutils/19984
1501         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1502         smaller than address size.
1503
1504 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1505
1506         * alpha-dis.c: Regenerate.
1507         * crx-dis.c: Likewise.
1508         * disassemble.c: Likewise.
1509         * epiphany-opc.c: Likewise.
1510         * fr30-opc.c: Likewise.
1511         * frv-opc.c: Likewise.
1512         * ip2k-opc.c: Likewise.
1513         * iq2000-opc.c: Likewise.
1514         * lm32-opc.c: Likewise.
1515         * lm32-opinst.c: Likewise.
1516         * m32c-opc.c: Likewise.
1517         * m32r-opc.c: Likewise.
1518         * m32r-opinst.c: Likewise.
1519         * mep-opc.c: Likewise.
1520         * mt-opc.c: Likewise.
1521         * or1k-opc.c: Likewise.
1522         * or1k-opinst.c: Likewise.
1523         * tic80-opc.c: Likewise.
1524         * xc16x-opc.c: Likewise.
1525         * xstormy16-opc.c: Likewise.
1526
1527 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1528
1529         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1530         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1531         calcsd, and calcxd instructions.
1532         * arc-opc.c (insert_nps_bitop_size): Delete.
1533         (extract_nps_bitop_size): Delete.
1534         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1535         (extract_nps_qcmp_m3): Define.
1536         (extract_nps_qcmp_m2): Define.
1537         (extract_nps_qcmp_m1): Define.
1538         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1539         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1540         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1541         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1542         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1543         NPS_QCMP_M3.
1544
1545 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1546
1547         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1548
1549 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1550
1551         * Makefile.in: Regenerated with automake 1.11.6.
1552         * aclocal.m4: Likewise.
1553
1554 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1555
1556         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1557         instructions.
1558         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1559         (extract_nps_cmem_uimm16): New function.
1560         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1561
1562 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1563
1564         * arc-dis.c (arc_insn_length): New function.
1565         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1566         (find_format): Change insnLen parameter to unsigned.
1567
1568 2016-04-13  Nick Clifton  <nickc@redhat.com>
1569
1570         PR target/19937
1571         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1572         the LD.B and LD.BU instructions.
1573
1574 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1575
1576         * arc-dis.c (find_format): Check for extension flags.
1577         (print_flags): New function.
1578         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1579         .extAuxRegister.
1580         * arc-ext.c (arcExtMap_coreRegName): Use
1581         LAST_EXTENSION_CORE_REGISTER.
1582         (arcExtMap_coreReadWrite): Likewise.
1583         (dump_ARC_extmap): Update printing.
1584         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1585         (arc_aux_regs): Add cpu field.
1586         * arc-regs.h: Add cpu field, lower case name aux registers.
1587
1588 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1589
1590         * arc-tbl.h: Add rtsc, sleep with no arguments.
1591
1592 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1593
1594         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1595         Initialize.
1596         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1597         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1598         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1599         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1600         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1601         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1602         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1603         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1604         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1605         (arc_opcode arc_opcodes): Null terminate the array.
1606         (arc_num_opcodes): Remove.
1607         * arc-ext.h (INSERT_XOP): Define.
1608         (extInstruction_t): Likewise.
1609         (arcExtMap_instName): Delete.
1610         (arcExtMap_insn): New function.
1611         (arcExtMap_genOpcode): Likewise.
1612         * arc-ext.c (ExtInstruction): Remove.
1613         (create_map): Zero initialize instruction fields.
1614         (arcExtMap_instName): Remove.
1615         (arcExtMap_insn): New function.
1616         (dump_ARC_extmap): More info while debuging.
1617         (arcExtMap_genOpcode): New function.
1618         * arc-dis.c (find_format): New function.
1619         (print_insn_arc): Use find_format.
1620         (arc_get_disassembler): Enable dump_ARC_extmap only when
1621         debugging.
1622
1623 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1624
1625         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1626         instruction bits out.
1627
1628 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1629
1630         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1631         * arc-opc.c (arc_flag_operands): Add new flags.
1632         (arc_flag_classes): Add new classes.
1633
1634 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1635
1636         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1637
1638 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1639
1640         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1641         encode1, rflt, crc16, and crc32 instructions.
1642         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1643         (arc_flag_classes): Add C_NPS_R.
1644         (insert_nps_bitop_size_2b): New function.
1645         (extract_nps_bitop_size_2b): Likewise.
1646         (insert_nps_bitop_uimm8): Likewise.
1647         (extract_nps_bitop_uimm8): Likewise.
1648         (arc_operands): Add new operand entries.
1649
1650 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1651
1652         * arc-regs.h: Add a new subclass field.  Add double assist
1653         accumulator register values.
1654         * arc-tbl.h: Use DPA subclass to mark the double assist
1655         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1656         * arc-opc.c (RSP): Define instead of SP.
1657         (arc_aux_regs): Add the subclass field.
1658
1659 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1660
1661         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1662
1663 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1664
1665         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1666         NPS_R_SRC1.
1667
1668 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1669
1670         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1671         issues.  No functional changes.
1672
1673 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1674
1675         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1676         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1677         (RTT): Remove duplicate.
1678         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1679         (PCT_CONFIG*): Remove.
1680         (D1L, D1H, D2H, D2L): Define.
1681
1682 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1683
1684         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1685
1686 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1687
1688         * arc-tbl.h (invld07): Remove.
1689         * arc-ext-tbl.h: New file.
1690         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1691         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1692
1693 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1694
1695         Fix -Wstack-usage warnings.
1696         * aarch64-dis.c (print_operands): Substitute size.
1697         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1698
1699 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1700
1701         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1702         to get a proper diagnostic when an invalid ASR register is used.
1703
1704 2016-03-22  Nick Clifton  <nickc@redhat.com>
1705
1706         * configure: Regenerate.
1707
1708 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1709
1710         * arc-nps400-tbl.h: New file.
1711         * arc-opc.c: Add top level comment.
1712         (insert_nps_3bit_dst): New function.
1713         (extract_nps_3bit_dst): New function.
1714         (insert_nps_3bit_src2): New function.
1715         (extract_nps_3bit_src2): New function.
1716         (insert_nps_bitop_size): New function.
1717         (extract_nps_bitop_size): New function.
1718         (arc_flag_operands): Add nps400 entries.
1719         (arc_flag_classes): Add nps400 entries.
1720         (arc_operands): Add nps400 entries.
1721         (arc_opcodes): Add nps400 include.
1722
1723 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1724
1725         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1726         the new class enum values.
1727
1728 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1729
1730         * arc-dis.c (print_insn_arc): Handle nps400.
1731
1732 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1733
1734         * arc-opc.c (BASE): Delete.
1735
1736 2016-03-18  Nick Clifton  <nickc@redhat.com>
1737
1738         PR target/19721
1739         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1740         of MOV insn that aliases an ORR insn.
1741
1742 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1743
1744         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1745
1746 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1747
1748         * mcore-opc.h: Add const qualifiers.
1749         * microblaze-opc.h (struct op_code_struct): Likewise.
1750         * sh-opc.h: Likewise.
1751         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1752         (tic4x_print_op): Likewise.
1753
1754 2016-03-02  Alan Modra  <amodra@gmail.com>
1755
1756         * or1k-desc.h: Regenerate.
1757         * fr30-ibld.c: Regenerate.
1758         * rl78-decode.c: Regenerate.
1759
1760 2016-03-01  Nick Clifton  <nickc@redhat.com>
1761
1762         PR target/19747
1763         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1764
1765 2016-02-24  Renlin Li  <renlin.li@arm.com>
1766
1767         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1768         (print_insn_coprocessor): Support fp16 instructions.
1769
1770 2016-02-24  Renlin Li  <renlin.li@arm.com>
1771
1772         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1773         vminnm, vrint(mpna).
1774
1775 2016-02-24  Renlin Li  <renlin.li@arm.com>
1776
1777         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1778         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1779
1780 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1781
1782         * i386-dis.c (print_insn): Parenthesize expression to prevent
1783         truncated addresses.
1784         (OP_J): Likewise.
1785
1786 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1787             Janek van Oirschot  <jvanoirs@synopsys.com>
1788
1789         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1790         variable.
1791
1792 2016-02-04  Nick Clifton  <nickc@redhat.com>
1793
1794         PR target/19561
1795         * msp430-dis.c (print_insn_msp430): Add a special case for
1796         decoding an RRC instruction with the ZC bit set in the extension
1797         word.
1798
1799 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1800
1801         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1802         * epiphany-ibld.c: Regenerate.
1803         * fr30-ibld.c: Regenerate.
1804         * frv-ibld.c: Regenerate.
1805         * ip2k-ibld.c: Regenerate.
1806         * iq2000-ibld.c: Regenerate.
1807         * lm32-ibld.c: Regenerate.
1808         * m32c-ibld.c: Regenerate.
1809         * m32r-ibld.c: Regenerate.
1810         * mep-ibld.c: Regenerate.
1811         * mt-ibld.c: Regenerate.
1812         * or1k-ibld.c: Regenerate.
1813         * xc16x-ibld.c: Regenerate.
1814         * xstormy16-ibld.c: Regenerate.
1815
1816 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1817
1818         * epiphany-dis.c: Regenerated from latest cpu files.
1819
1820 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1821
1822         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1823         test bit.
1824
1825 2016-01-25  Renlin Li  <renlin.li@arm.com>
1826
1827         * arm-dis.c (mapping_symbol_for_insn): New function.
1828         (find_ifthen_state): Call mapping_symbol_for_insn().
1829
1830 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1831
1832         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1833         of MSR UAO immediate operand.
1834
1835 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1836
1837         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1838         instruction support.
1839
1840 2016-01-17  Alan Modra  <amodra@gmail.com>
1841
1842         * configure: Regenerate.
1843
1844 2016-01-14  Nick Clifton  <nickc@redhat.com>
1845
1846         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1847         instructions that can support stack pointer operations.
1848         * rl78-decode.c: Regenerate.
1849         * rl78-dis.c: Fix display of stack pointer in MOVW based
1850         instructions.
1851
1852 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1853
1854         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1855         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1856         erxtatus_el1 and erxaddr_el1.
1857
1858 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1859
1860         * arm-dis.c (arm_opcodes): Add "esb".
1861         (thumb_opcodes): Likewise.
1862
1863 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1864
1865         * ppc-opc.c <xscmpnedp>: Delete.
1866         <xvcmpnedp>: Likewise.
1867         <xvcmpnedp.>: Likewise.
1868         <xvcmpnesp>: Likewise.
1869         <xvcmpnesp.>: Likewise.
1870
1871 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1872
1873         PR gas/13050
1874         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1875         addition to ISA_A.
1876
1877 2016-01-01  Alan Modra  <amodra@gmail.com>
1878
1879         Update year range in copyright notice of all files.
1880
1881 For older changes see ChangeLog-2015
1882 \f
1883 Copyright (C) 2016 Free Software Foundation, Inc.
1884
1885 Copying and distribution of this file, with or without modification,
1886 are permitted in any medium without royalty provided the copyright
1887 notice and this notice are preserved.
1888
1889 Local Variables:
1890 mode: change-log
1891 left-margin: 8
1892 fill-column: 74
1893 version-control: never
1894 End: