opcodes/ChangeLog

   1 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
   2
   3         * micromips-opc.c (COD): Rename throughout to...
   4         (CM): New define, update to use INSN_COPROC_MOVE.
   5         (LCD): Rename throughout to...
   6         (LC): New define, update to use INSN_LOAD_COPROC.
   7         * mips-opc.c: Likewise.
   8
   9 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
  10
  11         * micromips-opc.c (COD, LCD) New macros.
  12         (cfc1, ctc1): Remove FP_S attribute.
  13         (dmfc1, mfc1, mfhc1): Add LCD attribute.
  14         (dmtc1, mtc1, mthc1): Add COD attribute.
  15         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
  16
  17 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
  18             Alexander Ivchenko  <alexander.ivchenko@intel.com>
  19             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
  20             Sergey Lega  <sergey.s.lega@intel.com>
  21             Anna Tikhonova  <anna.tikhonova@intel.com>
  22             Ilya Tocar  <ilya.tocar@intel.com>
  23             Andrey Turetskiy  <andrey.turetskiy@intel.com>
  24             Ilya Verbin  <ilya.verbin@intel.com>
  25             Kirill Yukhin  <kirill.yukhin@intel.com>
  26             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
  27
  28         * i386-dis-evex.h: Updated.
  29         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
  30         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
  31         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
  32         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
  33         PREFIX_EVEX_0F3A67.
  34         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
  35         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
  36         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
  37         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
  38         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
  39         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
  40         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
  41         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
  42         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
  43         (prefix_table): Add entries for new instructions.
  44         (vex_len_table): Ditto.
  45         (vex_w_table): Ditto.
  46         (OP_E_memory): Update xmmq_mode handling.
  47         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
  48         (cpu_flags): Add CpuAVX512DQ.
  49         * i386-init.h: Regenerared.
  50         * i386-opc.h (CpuAVX512DQ): New.
  51         (i386_cpu_flags): Add cpuavx512dq.
  52         * i386-opc.tbl: Add AVX512DQ instructions.
  53         * i386-tbl.h: Regenerate.
  54
  55 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
  56             Alexander Ivchenko  <alexander.ivchenko@intel.com>
  57             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
  58             Sergey Lega  <sergey.s.lega@intel.com>
  59             Anna Tikhonova  <anna.tikhonova@intel.com>
  60             Ilya Tocar  <ilya.tocar@intel.com>
  61             Andrey Turetskiy  <andrey.turetskiy@intel.com>
  62             Ilya Verbin  <ilya.verbin@intel.com>
  63             Kirill Yukhin  <kirill.yukhin@intel.com>
  64             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
  65
  66         * i386-dis-evex.h: Add new instructions (prefixes bellow).
  67         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
  68         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
  69         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
  70         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
  71         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
  72         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
  73         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
  74         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
  75         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
  76         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
  77         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
  78         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
  79         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
  80         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
  81         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
  82         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
  83         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
  84         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
  85         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
  86         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
  87         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
  88         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
  89         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
  90         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
  91         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
  92         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
  93         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
  94         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
  95         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
  96         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
  97         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
  98         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
  99         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 100         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 101         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 102         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 103         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 104         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 105         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 106         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 107         (prefix_table): Add entries for new instructions.
 108         (vex_table) : Ditto.
 109         (vex_len_table): Ditto.
 110         (vex_w_table): Ditto.
 111         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 112         mask_bd_mode handling.
 113         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 114         handling.
 115         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 116         handling.
 117         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 118         (OP_EX): Add dqw_swap_mode handling.
 119         (OP_VEX): Add mask_bd_mode handling.
 120         (OP_Mask): Add mask_bd_mode handling.
 121         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 122         (cpu_flags): Add CpuAVX512BW.
 123         * i386-init.h: Regenerated.
 124         * i386-opc.h (CpuAVX512BW): New.
 125         (i386_cpu_flags): Add cpuavx512bw.
 126         * i386-opc.tbl: Add AVX512BW instructions.
 127         * i386-tbl.h: Regenerate.
 128
 129 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 130             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 131             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 132             Sergey Lega  <sergey.s.lega@intel.com>
 133             Anna Tikhonova  <anna.tikhonova@intel.com>
 134             Ilya Tocar  <ilya.tocar@intel.com>
 135             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 136             Ilya Verbin  <ilya.verbin@intel.com>
 137             Kirill Yukhin  <kirill.yukhin@intel.com>
 138             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 139
 140         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 141         * i386-tbl.h: Regenerate.
 142
 143 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 144             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 145             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 146             Sergey Lega  <sergey.s.lega@intel.com>
 147             Anna Tikhonova  <anna.tikhonova@intel.com>
 148             Ilya Tocar  <ilya.tocar@intel.com>
 149             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 150             Ilya Verbin  <ilya.verbin@intel.com>
 151             Kirill Yukhin  <kirill.yukhin@intel.com>
 152             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 153
 154         * i386-dis.c (intel_operand_size): Support 128/256 length in
 155         vex_vsib_q_w_dq_mode.
 156         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 157         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 158         (cpu_flags): Add CpuAVX512VL.
 159         * i386-init.h: Regenerated.
 160         * i386-opc.h (CpuAVX512VL): New.
 161         (i386_cpu_flags): Add cpuavx512vl.
 162         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 163         * i386-opc.tbl: Add AVX512VL instructions.
 164         * i386-tbl.h: Regenerate.
 165
 166 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 167
 168         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 169         * or1k-opinst.c: Regenerate.
 170
 171 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 172
 173         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 174         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 175
 176 2014-07-04  Alan Modra  <amodra@gmail.com>
 177
 178         * configure.ac: Rename from configure.in.
 179         * Makefile.in: Regenerate.
 180         * config.in: Regenerate.
 181
 182 2014-07-04  Alan Modra  <amodra@gmail.com>
 183
 184         * configure.in: Include bfd/version.m4.
 185         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 186         (BFD_VERSION): Delete.
 187         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 188         * configure: Regenerate.
 189         * Makefile.in: Regenerate.
 190
 191 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 192             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 193             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 194             Soundararajan  <Sounderarajan.D@atmel.com>
 195
 196         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 197         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 198         machine is not avrtiny.
 199
 200 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 201
 202         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 203         constants.
 204
 205 2014-06-12  Alan Modra  <amodra@gmail.com>
 206
 207         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 208         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 209
 210 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         * i386-dis.c (fwait_prefix): New.
 213         (ckprefix): Set fwait_prefix.
 214         (print_insn): Properly print prefixes before fwait.
 215
 216 2014-06-07  Alan Modra  <amodra@gmail.com>
 217
 218         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 219
 220 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 221
 222         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 223         bfd's development.sh.
 224         * Makefile.in, configure: Regenerate.
 225
 226 2014-06-03  Nick Clifton  <nickc@redhat.com>
 227
 228         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 229         decide when extended addressing is being used.
 230
 231 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 232
 233         * sparc-opc.c (cas): Disable for LEON.
 234         (casl): Likewise.
 235
 236 2014-05-20  Alan Modra  <amodra@gmail.com>
 237
 238         * m68k-dis.c: Don't include setjmp.h.
 239
 240 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 241
 242         * i386-dis.c (ADDR16_PREFIX): Removed.
 243         (ADDR32_PREFIX): Likewise.
 244         (DATA16_PREFIX): Likewise.
 245         (DATA32_PREFIX): Likewise.
 246         (prefix_name): Updated.
 247         (print_insn): Simplify data and address size prefixes processing.
 248
 249 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 250
 251         * or1k-desc.c: Regenerated.
 252         * or1k-desc.h: Likewise.
 253         * or1k-opc.c: Likewise.
 254         * or1k-opc.h: Likewise.
 255         * or1k-opinst.c: Likewise.
 256
 257 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 258
 259         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 260         (I34): New define.
 261         (I36): New define.
 262         (I66): New define.
 263         (I68): New define.
 264         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 265         mips64r5.
 266         (parse_mips_dis_option): Update MSA and virtualization support to
 267         allow mips64r3 and mips64r5.
 268
 269 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 270
 271         * mips-opc.c (G3): Remove I4.
 272
 273 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 274
 275         PR binutils/16893
 276         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 277         (end_codep): Likewise.
 278         (mandatory_prefix): Likewise.
 279         (active_seg_prefix): Likewise.
 280         (ckprefix): Set active_seg_prefix to the active segment register
 281         prefix.
 282         (seg_prefix): Removed.
 283         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 284         for prefix index.  Ignore the index if it is invalid and the
 285         mandatory prefix isn't required.
 286         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 287         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 288         in used_prefixes here.  Don't print unused prefixes.  Check
 289         active_seg_prefix for the active segment register prefix.
 290         Restore the DFLAG bit in sizeflag if the data size prefix is
 291         unused.  Check the unused mandatory PREFIX_XXX prefixes
 292         (append_seg): Only print the segment register which gets used.
 293         (OP_E_memory): Check active_seg_prefix for the segment register
 294         prefix.
 295         (OP_OFF): Likewise.
 296         (OP_OFF64): Likewise.
 297         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 298
 299 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 300
 301         PR binutils/16886
 302         * config.in: Regenerated.
 303         * configure: Likewise.
 304         * configure.in: Check if sigsetjmp is available.
 305         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 306         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 307         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 308         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 309         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 310         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 311         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 312         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 313         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 314         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 315         (OPCODES_SIGSETJMP): Likewise.
 316         (OPCODES_SIGLONGJMP): Likewise.
 317         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 318         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 319         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 320         * xtensa-dis.c (dis_private): Replace jmp_buf with
 321         OPCODES_SIGJMP_BUF.
 322         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 323         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 324         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 325         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 326         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 327
 328 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         PR binutils/16891
 331         * i386-dis.c (print_insn): Handle prefixes before fwait.
 332
 333 2014-04-26  Alan Modra  <amodra@gmail.com>
 334
 335         * po/POTFILES.in: Regenerate.
 336
 337 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 338
 339         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 340         to allow the MIPS XPA ASE.
 341         (parse_mips_dis_option): Process the -Mxpa option.
 342         * mips-opc.c (XPA): New define.
 343         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 344         locations of the ctc0 and cfc0 instructions.
 345
 346 2014-04-22  Christian Svensson  <blue@cmd.nu>
 347
 348         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 349         * configure.in: Likewise.
 350         * disassemble.c: Likewise.
 351         * or1k-asm.c: New file.
 352         * or1k-desc.c: New file.
 353         * or1k-desc.h: New file.
 354         * or1k-dis.c: New file.
 355         * or1k-ibld.c: New file.
 356         * or1k-opc.c: New file.
 357         * or1k-opc.h: New file.
 358         * or1k-opinst.c: New file.
 359         * Makefile.in: Regenerate.
 360         * configure: Regenerate.
 361         * openrisc-asm.c: Delete.
 362         * openrisc-desc.c: Delete.
 363         * openrisc-desc.h: Delete.
 364         * openrisc-dis.c: Delete.
 365         * openrisc-ibld.c: Delete.
 366         * openrisc-opc.c: Delete.
 367         * openrisc-opc.h: Delete.
 368         * or32-dis.c: Delete.
 369         * or32-opc.c: Delete.
 370
 371 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 372
 373         * i386-dis.c (rm_table): Add encls, enclu.
 374         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 375         (cpu_flags): Add CpuSE1.
 376         * i386-opc.h (enum): Add CpuSE1.
 377         (i386_cpu_flags): Add cpuse1.
 378         * i386-opc.tbl: Add encls, enclu.
 379         * i386-init.h: Regenerated.
 380         * i386-tbl.h: Likewise.
 381
 382 2014-04-02  Anthony Green  <green@moxielogic.com>
 383
 384         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 385         instructions, sex.b and sex.s.
 386
 387 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 388
 389         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 390         instructions.
 391
 392 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 393
 394         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 395         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 396         vscatterqps.
 397         * i386-tbl.h: Regenerate.
 398
 399 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 400
 401         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 402         %hstick_enable added.
 403
 404 2014-03-19  Nick Clifton  <nickc@redhat.com>
 405
 406         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 407         field of 3.
 408         (sbwl, ubwl, SCALE): Likewise.
 409         * rx-decode.c: Regenerate.
 410
 411 2014-03-12  Alan Modra  <amodra@gmail.com>
 412
 413         * Makefile.in: Regenerate.
 414
 415 2014-03-05  Alan Modra  <amodra@gmail.com>
 416
 417         Update copyright years.
 418
 419 2014-03-04  Heiher  <r@hev.cc>
 420
 421         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 422
 423 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 424
 425         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 426         so that they come after the Loongson extensions.
 427
 428 2014-03-03  Alan Modra  <amodra@gmail.com>
 429
 430         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 431
 432 2014-02-28  Alan Modra  <amodra@gmail.com>
 433
 434         * msp430-decode.c: Regenerate.
 435
 436 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 437
 438         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 439         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 440
 441 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 442
 443         * aarch64-opc.c (print_register_offset_address): Call
 444         get_int_reg_name to prepare the register name.
 445
 446 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 447
 448         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 449         * i386-tbl.h: Regenerate.
 450
 451 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 452
 453         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 454         (cpu_flags): Add CpuPREFETCHWT1.
 455         * i386-init.h: Regenerate.
 456         * i386-opc.h (CpuPREFETCHWT1): New.
 457         (i386_cpu_flags): Add cpuprefetchwt1.
 458         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 459         * i386-tbl.h: Regenerate.
 460
 461 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 462
 463         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 464         to CpuAVX512F.
 465         * i386-tbl.h: Regenerate.
 466
 467 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 470         (output_opcode_modifier): Likewise.
 471         (output_operand_type): Likewise.
 472         * i386-init.h: Regenerated.
 473         * i386-tbl.h: Likewise.
 474
 475 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 476
 477         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 478         MOD_0FC7_REG_5.
 479         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 480         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 481         (prefix_table): Add clflusopt.
 482         (mod_table): Add xrstors, xsavec, xsaves.
 483         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 484         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 485         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 486         * i386-init.h: Regenerate.
 487         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 488         xsaves64, xsavec, xsavec64.
 489         * i386-tbl.h: Regenerate.
 490
 491 2014-02-10  Alan Modra  <amodra@gmail.com>
 492
 493         * po/POTFILES.in: Regenerate.
 494         * po/opcodes.pot: Regenerate.
 495
 496 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 497             Jan Beulich  <jbeulich@suse.com>
 498
 499         PR binutils/16490
 500         * i386-dis.c (OP_E_memory): Fix shift computation for
 501         vex_vsib_q_w_dq_mode.
 502
 503 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 504             Roland McGrath  <mcgrathr@google.com>
 505
 506         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 507         last_rex_prefix is -1.
 508
 509 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 510
 511         * i386-gen.c (process_copyright): Update copyright year to 2014.
 512
 513 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 514
 515         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 516
 517 For older changes see ChangeLog-2013
 518 \f
 519 Copyright (C) 2014 Free Software Foundation, Inc.
 520
 521 Copying and distribution of this file, with or without modification,
 522 are permitted in any medium without royalty provided the copyright
 523 notice and this notice are preserved.
 524
 525 Local Variables:
 526 mode: change-log
 527 left-margin: 8
 528 fill-column: 74
 529 version-control: never
 530 End: