opcodes/ChangeLog

   1 2021-03-29  Alan Modra  <amodra@gmail.com>
   2
   3         * arc-dis.c (extract_operand_value): Correct NULL cast.
   4         * frv-opc.h: Regenerate.
   5
   6 2021-03-26  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
   9         MMX form.
  10         * i386-tbl.h: Re-generate.
  11
  12 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
  13
  14         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
  15         immediate in br.n instruction.
  16
  17 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-dis.c (XMGatherD, VexGatherD): New.
  20         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
  21         (print_insn): Check masking for S/G insns.
  22         (OP_E_memory): New local variable check_gather. Extend mandatory
  23         SIB check. Check register conflicts for (EVEX-encoded) gathers.
  24         Extend check for disallowed 16-bit addressing.
  25         (OP_VEX): New local variables modrm_reg and sib_index. Convert
  26         if()s to switch(). Check register conflicts for (VEX-encoded)
  27         gathers. Drop no longer reachable cases.
  28         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
  29         vgatherdp*.
  30
  31 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
  34         zeroing-masking without masking.
  35
  36 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-opc.tbl (invlpgb): Fix multi-operand form.
  39         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
  40         single-operand forms as deprecated.
  41         * i386-tbl.h: Re-generate.
  42
  43 2021-03-25  Alan Modra  <amodra@gmail.com>
  44
  45         PR 27647
  46         * ppc-opc.c (XLOCB_MASK): Delete.
  47         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
  48         XLBH_MASK.
  49         (powerpc_opcodes): Accept a BH field on all extended forms of
  50         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
  51
  52 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-gen.c (output_i386_opcode): Drop processing of
  55         opcode_length. Calculate length from base_opcode. Adjust prefix
  56         encoding determination.
  57         (process_i386_opcodes): Drop output of fake opcode_length.
  58         * i386-opc.h (struct insn_template): Drop opcode_length field.
  59         * i386-opc.tbl: Drop opcode length field from all templates.
  60         * i386-tbl.h: Re-generate.
  61
  62 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-gen.c (process_i386_opcode_modifier): Return void. New
  65         parameter "prefix". Drop local variable "regular_encoding".
  66         Record prefix setting / check for consistency.
  67         (output_i386_opcode): Parse opcode_length and base_opcode
  68         earlier. Derive prefix encoding. Drop no longer applicable
  69         consistency checking. Adjust process_i386_opcode_modifier()
  70         invocation.
  71         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  72         invocation.
  73         * i386-tbl.h: Re-generate.
  74
  75 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  76
  77         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
  78         check.
  79         * i386-opc.h (Prefix_*): Move #define-s.
  80         * i386-opc.tbl: Move pseudo prefix enumerator values to
  81         extension opcode field. Introduce pseudopfx template.
  82         * i386-tbl.h: Re-generate.
  83
  84 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
  87         comment.
  88         * i386-tbl.h: Re-generate.
  89
  90 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.h (struct insn_template): Move cpu_flags field past
  93         opcode_modifier one.
  94         * i386-tbl.h: Re-generate.
  95
  96 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
  99         * i386-opc.h (OpcodeSpace): New enumerator.
 100         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 101         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 102         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 103         (struct i386_opcode_modifier): New field opcodespace. Shrink
 104         opcodeprefix field.
 105         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 106         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 107         OpcodePrefix uses.
 108         * i386-tbl.h: Re-generate.
 109
 110 2021-03-22  Martin Liska  <mliska@suse.cz>
 111
 112         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 113         * arc-dis.c (parse_option): Likewise.
 114         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 115         * cris-dis.c (print_with_operands): Likewise.
 116         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 117         * i386-dis.c (print_insn): Likewise.
 118         * ia64-gen.c (fetch_insn_class): Likewise.
 119         (parse_resource_users): Likewise.
 120         (in_iclass): Likewise.
 121         (lookup_specifier): Likewise.
 122         (insert_opcode_dependencies): Likewise.
 123         * mips-dis.c (parse_mips_ase_option): Likewise.
 124         (parse_mips_dis_option): Likewise.
 125         * s390-dis.c (disassemble_init_s390): Likewise.
 126         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 127
 128 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 129
 130         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 131
 132 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 133
 134         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 135         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 136
 137 2021-03-12  Alan Modra  <amodra@gmail.com>
 138
 139         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 140
 141 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-dis.c (OP_XMM): Re-order checks.
 144
 145 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-dis.c (putop): Drop need_vex check when also checking
 148         vex.evex.
 149         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 150         checking vex.b.
 151
 152 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 155         checks. Move case label past broadcast check.
 156
 157 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 158
 159         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 160         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 161         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 162         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 163         EVEX_W_0F38C7_M_0_L_2): Delete.
 164         (REG_EVEX_0F38C7_M_0_L_2): New.
 165         (intel_operand_size): Handle VEX and EVEX the same for
 166         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 167         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 168         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 169         vex_vsib_q_w_d_mode uses.
 170         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 171         0F38A1, and 0F38A3 entries.
 172         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 173         entry.
 174         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 175         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 176         0F38A3 entries.
 177
 178 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 179
 180         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 181         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 182         MOD_VEX_0FXOP_09_12): Rename to ...
 183         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 184         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 185         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 186         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 187         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 188         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 189         (reg_table): Adjust comments.
 190         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 191         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 192         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 193         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 194         (vex_len_table): Adjust opcode 0A_12 entry.
 195         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 196         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 197         (rm_table): Move hreset entry.
 198
 199 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 200
 201         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 202         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 203         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 204         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 205         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 206         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 207         (get_valid_dis386): Also handle 512-bit vector length when
 208         vectoring into vex_len_table[].
 209         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 210         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 211         entries.
 212         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 213         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 214         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 215         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 216         entries.
 217
 218 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 219
 220         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 221         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 222         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 223         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 224         entries.
 225         * i386-dis-evex-len.h (evex_len_table): Likewise.
 226         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 227
 228 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 229
 230         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 231         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 232         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 233         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 234         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 235         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 236         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 237         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 238         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 239         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 240         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 241         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 242         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 243         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 244         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 245         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 246         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 247         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 248         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 249         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 250         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 251         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 252         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 253         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 254         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 255         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 256         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 257         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 258         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 259         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 260         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 261         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 262         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 263         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 264         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 265         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 266         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 267         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 268         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 269         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 270         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 271         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 272         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 273         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 274         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 275         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 276         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 277         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 278         EVEX_W_0F3A43_L_n): New.
 279         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 280         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 281         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 282         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 283         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 284         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 285         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 286         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 287         0F385B, 0F38C6, and 0F38C7 entries.
 288         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 289         0F38C6 and 0F38C7.
 290         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 291         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 292         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 293         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 294
 295 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 296
 297         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 298         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 299         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 300         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 301         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 302         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 303         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 304         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 305         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 306         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 307         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 308         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 309         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 310         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 311         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 312         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 313         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 314         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 315         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 316         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 317         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 318         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 319         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 320         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 321         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 322         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 323         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 324         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 325         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 326         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 327         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 328         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 329         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 330         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 331         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 332         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 333         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 334         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 335         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 336         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 337         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 338         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 339         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 340         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 341         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 342         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 343         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 344         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 345         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 346         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 347         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 348         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 349         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 350         VEX_W_0F99_P_2_LEN_0): Delete.
 351         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 352         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 353         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 354         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 355         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 356         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 357         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 358         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 359         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 360         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 361         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 362         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 363         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 364         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 365         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 366         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 367         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 368         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 369         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 370         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 371         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 372         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 373         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 374         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 375         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 376         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 377         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 378         (prefix_table): No longer link to vex_len_table[] for opcodes
 379         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 380         0F92, 0F93, 0F98, and 0F99.
 381         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 382         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 383         0F98, and 0F99.
 384         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 385         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 386         0F98, and 0F99.
 387         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 388         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 389         0F98, and 0F99.
 390         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 391         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 392         0F98, and 0F99.
 393
 394 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 395
 396         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 397         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 398         REG_VEX_0F73_M_0 respectively.
 399         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 400         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 401         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 402         MOD_VEX_0F73_REG_7): Delete.
 403         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 404         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 405         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 406         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 407         PREFIX_VEX_0F3AF0_L_0 respectively.
 408         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 409         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 410         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 411         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 412         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 413         VEX_LEN_0F38F7): New.
 414         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 415         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 416         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 417         0F38F3.
 418         (prefix_table): No longer link to vex_len_table[] for opcodes
 419         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 420         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 421         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 422         0F38F6, 0F38F7, and 0F3AF0.
 423         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 424         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 425         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 426         0F73.
 427
 428 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 429
 430         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 431         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 432         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 433         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 434         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 435         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 436         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 437         73.
 438         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 439         0F72, and 0F73.
 440         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 441         0F73.
 442
 443 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 444
 445         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 446         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 447         (reg_table): Don't link to mod_table[] where not needed. Add
 448         PREFIX_IGNORED to nop entries.
 449         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 450         (mod_table): Add nop entries next to prefetch ones. Drop
 451         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 452         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 453         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 454         PREFIX_OPCODE from endbr* entries.
 455         (get_valid_dis386): Also consider entry's name when zapping
 456         vindex.
 457         (print_insn): Handle PREFIX_IGNORED.
 458
 459 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 460
 461         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 462         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 463         element.
 464         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 465         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 466         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 467         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 468         (struct i386_opcode_modifier): Delete notrackprefixok,
 469         islockable, hleprefixok, and repprefixok fields. Add prefixok
 470         field.
 471         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 472         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 473         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 474         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 475         Replace HLEPrefixOk.
 476         * opcodes/i386-tbl.h: Re-generate.
 477
 478 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 479
 480         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 481         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 482         64-bit form.
 483         * opcodes/i386-tbl.h: Re-generate.
 484
 485 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 488         for {} instead of {0}. Don't look for '0'.
 489         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 490         size specifiers.
 491
 492 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 493
 494         PR 27158
 495         * riscv-dis.c (print_insn_args): Updated encoding macros.
 496         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 497         (match_c_addi16sp): Updated encoding macros.
 498         (match_c_lui): Likewise.
 499         (match_c_lui_with_hint): Likewise.
 500         (match_c_addi4spn): Likewise.
 501         (match_c_slli): Likewise.
 502         (match_slli_as_c_slli): Likewise.
 503         (match_c_slli64): Likewise.
 504         (match_srxi_as_c_srxi): Likewise.
 505         (riscv_insn_types): Added .insn css/cl/cs.
 506
 507 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 508
 509         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 510         (default_priv_spec): Updated type to riscv_spec_class.
 511         (parse_riscv_dis_option): Updated.
 512         * riscv-opc.c: Moved stuff and make the file tidy.
 513
 514 2021-02-17  Alan Modra  <amodra@gmail.com>
 515
 516         * wasm32-dis.c: Include limits.h.
 517         (CHAR_BIT): Provide backup define.
 518         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 519         Correct signed overflow checking.
 520
 521 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 524         * i386-tbl.h: Re-generate.
 525
 526 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 529         Oword.
 530         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 531
 532 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 533
 534         * s390-mkopc.c (main): Accept arch14 as cpu string.
 535         * s390-opc.txt: Add new arch14 instructions.
 536
 537 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 538
 539         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 540         favour of LIBINTL.
 541         * configure: Regenerated.
 542
 543 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 544
 545         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 546         * tic54x-opc.c (regs): Rename to ...
 547         (tic54x_regs): ... this.
 548         (mmregs): Rename to ...
 549         (tic54x_mmregs): ... this.
 550         (condition_codes): Rename to ...
 551         (tic54x_condition_codes): ... this.
 552         (cc2_codes): Rename to ...
 553         (tic54x_cc2_codes): ... this.
 554         (cc3_codes): Rename to ...
 555         (tic54x_cc3_codes): ... this.
 556         (status_bits): Rename to ...
 557         (tic54x_status_bits): ... this.
 558         (misc_symbols): Rename to ...
 559         (tic54x_misc_symbols): ... this.
 560
 561 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 562
 563         * riscv-opc.c (MASK_RVB_IMM): Removed.
 564         (riscv_opcodes): Removed zb* instructions.
 565         (riscv_ext_version_table): Removed versions for zb*.
 566
 567 2021-01-26  Alan Modra  <amodra@gmail.com>
 568
 569         * i386-gen.c (parse_template): Ensure entire template_instance
 570         is initialised.
 571
 572 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 573
 574         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 575         (riscv_fpr_names_abi): Likewise.
 576         (riscv_opcodes): Likewise.
 577         (riscv_insn_types): Likewise.
 578
 579 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 580
 581         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 582
 583 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 584
 585         * riscv-dis.c: Comments tidy and improvement.
 586         * riscv-opc.c: Likewise.
 587
 588 2021-01-13  Alan Modra  <amodra@gmail.com>
 589
 590         * Makefile.in: Regenerate.
 591
 592 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 593
 594         PR binutils/26792
 595         * configure.ac: Use GNU_MAKE_JOBSERVER.
 596         * aclocal.m4: Regenerated.
 597         * configure: Likewise.
 598
 599 2021-01-12  Nick Clifton  <nickc@redhat.com>
 600
 601         * po/sr.po: Updated Serbian translation.
 602
 603 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         PR ld/27173
 606         * configure: Regenerated.
 607
 608 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 609
 610         * aarch64-asm-2.c: Regenerate.
 611         * aarch64-dis-2.c: Likewise.
 612         * aarch64-opc-2.c: Likewise.
 613         * aarch64-opc.c (aarch64_print_operand):
 614         Delete handling of AARCH64_OPND_CSRE_CSR.
 615         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 616         (CSRE): Likewise.
 617         (_CSRE_INSN): Likewise.
 618         (aarch64_opcode_table): Delete csr.
 619
 620 2021-01-11  Nick Clifton  <nickc@redhat.com>
 621
 622         * po/de.po: Updated German translation.
 623         * po/fr.po: Updated French translation.
 624         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 625         * po/sv.po: Updated Swedish translation.
 626         * po/uk.po: Updated Ukranian translation.
 627
 628 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 629
 630         * configure: Regenerated.
 631
 632 2021-01-09  Nick Clifton  <nickc@redhat.com>
 633
 634         * configure: Regenerate.
 635         * po/opcodes.pot: Regenerate.
 636
 637 2021-01-09  Nick Clifton  <nickc@redhat.com>
 638
 639         * 2.36 release branch crated.
 640
 641 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 642
 643         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 644         (DW, (XRC_MASK): Define.
 645         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 646
 647 2021-01-09  Alan Modra  <amodra@gmail.com>
 648
 649         * configure: Regenerate.
 650
 651 2021-01-08  Nick Clifton  <nickc@redhat.com>
 652
 653         * po/sv.po: Updated Swedish translation.
 654
 655 2021-01-08  Nick Clifton  <nickc@redhat.com>
 656
 657         PR 27129
 658         * aarch64-dis.c (determine_disassembling_preference): Move call to
 659         aarch64_match_operands_constraint outside of the assertion.
 660         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 661         Replace with a return of FALSE.
 662
 663         PR 27139
 664         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 665         core system register.
 666
 667 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 668
 669         * configure: Regenerate.
 670
 671 2021-01-07  Nick Clifton  <nickc@redhat.com>
 672
 673         * po/fr.po: Updated French translation.
 674
 675 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 676
 677         * m68k-opc.c (chkl): Change minimum architecture requirement to
 678         m68020.
 679
 680 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 681
 682         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 683
 684 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 685             Jim Wilson  <jimw@sifive.com>
 686             Andrew Waterman  <andrew@sifive.com>
 687             Maxim Blinov  <maxim.blinov@embecosm.com>
 688             Kito Cheng  <kito.cheng@sifive.com>
 689             Nelson Chu  <nelson.chu@sifive.com>
 690
 691         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 692         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 693
 694 2021-01-01  Alan Modra  <amodra@gmail.com>
 695
 696         Update year range in copyright notice of all files.
 697
 698 For older changes see ChangeLog-2020
 699 \f
 700 Copyright (C) 2021 Free Software Foundation, Inc.
 701
 702 Copying and distribution of this file, with or without modification,
 703 are permitted in any medium without royalty provided the copyright
 704 notice and this notice are preserved.
 705
 706 Local Variables:
 707 mode: change-log
 708 left-margin: 8
 709 fill-column: 74
 710 version-control: never
 711 End: