1 2020-05-11 Alan Modra <amodra@gmail.com>
2 Peter Bergner <bergner@linux.ibm.com>
4 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
6 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
7 YMSK2, XA6a, XA6ap, XB6a entries.
8 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
9 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
11 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
12 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
13 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
14 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
15 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
16 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
17 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
18 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
19 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
20 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
21 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
22 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
23 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
24 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
26 2020-05-11 Alan Modra <amodra@gmail.com>
28 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
29 (insert_xts, extract_xts): New functions.
30 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
31 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
32 (VXRC_MASK, VXSH_MASK): Define.
33 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
34 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
35 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
36 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
37 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
38 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
39 xxblendvh, xxblendvw, xxblendvd, xxpermx.
41 2020-05-11 Alan Modra <amodra@gmail.com>
43 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
44 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
45 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
46 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
47 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
49 2020-05-11 Alan Modra <amodra@gmail.com>
51 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
52 (XTP, DQXP, DQXP_MASK): Define.
53 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
54 (prefix_opcodes): Add plxvp and pstxvp.
56 2020-05-11 Alan Modra <amodra@gmail.com>
58 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
59 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
60 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
62 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
64 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
66 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
68 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
70 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
72 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
74 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
76 2020-05-11 Alan Modra <amodra@gmail.com>
78 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
80 2020-05-11 Alan Modra <amodra@gmail.com>
82 * ppc-dis.c (ppc_opts): Add "power10" entry.
83 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
84 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
86 2020-05-11 Nick Clifton <nickc@redhat.com>
88 * po/fr.po: Updated French translation.
90 2020-04-30 Alex Coplan <alex.coplan@arm.com>
92 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
93 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
94 (operand_general_constraint_met_p): validate
95 AARCH64_OPND_UNDEFINED.
96 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
98 * aarch64-asm-2.c: Regenerated.
99 * aarch64-dis-2.c: Regenerated.
100 * aarch64-opc-2.c: Regenerated.
102 2020-04-29 Nick Clifton <nickc@redhat.com>
105 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
108 2020-04-29 Nick Clifton <nickc@redhat.com>
110 * po/sv.po: Updated Swedish translation.
112 2020-04-29 Nick Clifton <nickc@redhat.com>
115 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
116 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
117 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
120 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
123 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
124 cmpi only on m68020up and cpu32.
126 2020-04-20 Sudakshina Das <sudi.das@arm.com>
128 * aarch64-asm.c (aarch64_ins_none): New.
129 * aarch64-asm.h (ins_none): New declaration.
130 * aarch64-dis.c (aarch64_ext_none): New.
131 * aarch64-dis.h (ext_none): New declaration.
132 * aarch64-opc.c (aarch64_print_operand): Update case for
133 AARCH64_OPND_BARRIER_PSB.
134 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
135 (AARCH64_OPERANDS): Update inserter/extracter for
136 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
137 * aarch64-asm-2.c: Regenerated.
138 * aarch64-dis-2.c: Regenerated.
139 * aarch64-opc-2.c: Regenerated.
141 2020-04-20 Sudakshina Das <sudi.das@arm.com>
143 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
144 (aarch64_feature_ras, RAS): Likewise.
145 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
146 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
147 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
148 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
149 * aarch64-asm-2.c: Regenerated.
150 * aarch64-dis-2.c: Regenerated.
151 * aarch64-opc-2.c: Regenerated.
153 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
155 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
156 (print_insn_neon): Support disassembly of conditional
159 2020-02-16 David Faust <david.faust@oracle.com>
161 * bpf-desc.c: Regenerate.
162 * bpf-desc.h: Likewise.
163 * bpf-opc.c: Regenerate.
164 * bpf-opc.h: Likewise.
166 2020-04-07 Lili Cui <lili.cui@intel.com>
168 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
169 (prefix_table): New instructions (see prefixes above).
171 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
172 CPU_ANY_TSXLDTRK_FLAGS.
173 (cpu_flags): Add CpuTSXLDTRK.
174 * i386-opc.h (enum): Add CpuTSXLDTRK.
175 (i386_cpu_flags): Add cputsxldtrk.
176 * i386-opc.tbl: Add XSUSPLDTRK insns.
177 * i386-init.h: Regenerate.
178 * i386-tbl.h: Likewise.
180 2020-04-02 Lili Cui <lili.cui@intel.com>
182 * i386-dis.c (prefix_table): New instructions serialize.
183 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
184 CPU_ANY_SERIALIZE_FLAGS.
185 (cpu_flags): Add CpuSERIALIZE.
186 * i386-opc.h (enum): Add CpuSERIALIZE.
187 (i386_cpu_flags): Add cpuserialize.
188 * i386-opc.tbl: Add SERIALIZE insns.
189 * i386-init.h: Regenerate.
190 * i386-tbl.h: Likewise.
192 2020-03-26 Alan Modra <amodra@gmail.com>
194 * disassemble.h (opcodes_assert): Declare.
195 (OPCODES_ASSERT): Define.
196 * disassemble.c: Don't include assert.h. Include opintl.h.
197 (opcodes_assert): New function.
198 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
199 (bfd_h8_disassemble): Reduce size of data array. Correctly
200 calculate maxlen. Omit insn decoding when insn length exceeds
201 maxlen. Exit from nibble loop when looking for E, before
202 accessing next data byte. Move processing of E outside loop.
203 Replace tests of maxlen in loop with assertions.
205 2020-03-26 Alan Modra <amodra@gmail.com>
207 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
209 2020-03-25 Alan Modra <amodra@gmail.com>
211 * z80-dis.c (suffix): Init mybuf.
213 2020-03-22 Alan Modra <amodra@gmail.com>
215 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
216 successflly read from section.
218 2020-03-22 Alan Modra <amodra@gmail.com>
220 * arc-dis.c (find_format): Use ISO C string concatenation rather
221 than line continuation within a string. Don't access needs_limm
222 before testing opcode != NULL.
224 2020-03-22 Alan Modra <amodra@gmail.com>
226 * ns32k-dis.c (print_insn_arg): Update comment.
227 (print_insn_ns32k): Reduce size of index_offset array, and
228 initialize, passing -1 to print_insn_arg for args that are not
229 an index. Don't exit arg loop early. Abort on bad arg number.
231 2020-03-22 Alan Modra <amodra@gmail.com>
233 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
234 * s12z-opc.c: Formatting.
235 (operands_f): Return an int.
236 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
237 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
238 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
239 (exg_sex_discrim): Likewise.
240 (create_immediate_operand, create_bitfield_operand),
241 (create_register_operand_with_size, create_register_all_operand),
242 (create_register_all16_operand, create_simple_memory_operand),
243 (create_memory_operand, create_memory_auto_operand): Don't
244 segfault on malloc failure.
245 (z_ext24_decode): Return an int status, negative on fail, zero
247 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
248 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
249 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
250 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
251 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
252 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
253 (loop_primitive_decode, shift_decode, psh_pul_decode),
254 (bit_field_decode): Similarly.
255 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
256 to return value, update callers.
257 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
258 Don't segfault on NULL operand.
259 (decode_operation): Return OP_INVALID on first fail.
260 (decode_s12z): Check all reads, returning -1 on fail.
262 2020-03-20 Alan Modra <amodra@gmail.com>
264 * metag-dis.c (print_insn_metag): Don't ignore status from
267 2020-03-20 Alan Modra <amodra@gmail.com>
269 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
270 Initialize parts of buffer not written when handling a possible
271 2-byte insn at end of section. Don't attempt decoding of such
272 an insn by the 4-byte machinery.
274 2020-03-20 Alan Modra <amodra@gmail.com>
276 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
277 partially filled buffer. Prevent lookup of 4-byte insns when
278 only VLE 2-byte insns are possible due to section size. Print
279 ".word" rather than ".long" for 2-byte leftovers.
281 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
284 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
286 2020-03-13 Jan Beulich <jbeulich@suse.com>
288 * i386-dis.c (X86_64_0D): Rename to ...
289 (X86_64_0E): ... this.
291 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
293 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
294 * Makefile.in: Regenerated.
296 2020-03-09 Jan Beulich <jbeulich@suse.com>
298 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
300 * i386-tbl.h: Re-generate.
302 2020-03-09 Jan Beulich <jbeulich@suse.com>
304 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
305 vprot*, vpsha*, and vpshl*.
306 * i386-tbl.h: Re-generate.
308 2020-03-09 Jan Beulich <jbeulich@suse.com>
310 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
311 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
312 * i386-tbl.h: Re-generate.
314 2020-03-09 Jan Beulich <jbeulich@suse.com>
316 * i386-gen.c (set_bitfield): Ignore zero-length field names.
317 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
318 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
319 * i386-tbl.h: Re-generate.
321 2020-03-09 Jan Beulich <jbeulich@suse.com>
323 * i386-gen.c (struct template_arg, struct template_instance,
324 struct template_param, struct template, templates,
325 parse_template, expand_templates): New.
326 (process_i386_opcodes): Various local variables moved to
327 expand_templates. Call parse_template and expand_templates.
328 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
329 * i386-tbl.h: Re-generate.
331 2020-03-06 Jan Beulich <jbeulich@suse.com>
333 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
334 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
335 register and memory source templates. Replace VexW= by VexW*
337 * i386-tbl.h: Re-generate.
339 2020-03-06 Jan Beulich <jbeulich@suse.com>
341 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
342 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
343 * i386-tbl.h: Re-generate.
345 2020-03-06 Jan Beulich <jbeulich@suse.com>
347 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
348 * i386-tbl.h: Re-generate.
350 2020-03-06 Jan Beulich <jbeulich@suse.com>
352 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
353 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
354 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
355 VexW0 on SSE2AVX variants.
356 (vmovq): Drop NoRex64 from XMM/XMM variants.
357 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
358 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
359 applicable use VexW0.
360 * i386-tbl.h: Re-generate.
362 2020-03-06 Jan Beulich <jbeulich@suse.com>
364 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
365 * i386-opc.h (Rex64): Delete.
366 (struct i386_opcode_modifier): Remove rex64 field.
367 * i386-opc.tbl (crc32): Drop Rex64.
368 Replace Rex64 with Size64 everywhere else.
369 * i386-tbl.h: Re-generate.
371 2020-03-06 Jan Beulich <jbeulich@suse.com>
373 * i386-dis.c (OP_E_memory): Exclude recording of used address
374 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
375 addressed memory operands for MPX insns.
377 2020-03-06 Jan Beulich <jbeulich@suse.com>
379 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
380 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
381 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
382 (ptwrite): Split into non-64-bit and 64-bit forms.
383 * i386-tbl.h: Re-generate.
385 2020-03-06 Jan Beulich <jbeulich@suse.com>
387 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
389 * i386-tbl.h: Re-generate.
391 2020-03-04 Jan Beulich <jbeulich@suse.com>
393 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
394 (prefix_table): Move vmmcall here. Add vmgexit.
395 (rm_table): Replace vmmcall entry by prefix_table[] escape.
396 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
397 (cpu_flags): Add CpuSEV_ES entry.
398 * i386-opc.h (CpuSEV_ES): New.
399 (union i386_cpu_flags): Add cpusev_es field.
400 * i386-opc.tbl (vmgexit): New.
401 * i386-init.h, i386-tbl.h: Re-generate.
403 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
405 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
407 * i386-opc.h (IGNORESIZE): New.
408 (DEFAULTSIZE): Likewise.
409 (IgnoreSize): Removed.
410 (DefaultSize): Likewise.
412 (i386_opcode_modifier): Replace ignoresize/defaultsize with
414 * i386-opc.tbl (IgnoreSize): New.
415 (DefaultSize): Likewise.
416 * i386-tbl.h: Regenerated.
418 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
421 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
424 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
427 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
428 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
429 * i386-tbl.h: Regenerated.
431 2020-02-26 Alan Modra <amodra@gmail.com>
433 * aarch64-asm.c: Indent labels correctly.
434 * aarch64-dis.c: Likewise.
435 * aarch64-gen.c: Likewise.
436 * aarch64-opc.c: Likewise.
437 * alpha-dis.c: Likewise.
438 * i386-dis.c: Likewise.
439 * nds32-asm.c: Likewise.
440 * nfp-dis.c: Likewise.
441 * visium-dis.c: Likewise.
443 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
445 * arc-regs.h (int_vector_base): Make it available for all ARC
448 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
450 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
453 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
455 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
456 c.mv/c.li if rs1 is zero.
458 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
460 * i386-gen.c (cpu_flag_init): Replace CpuABM with
461 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
463 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
464 * i386-opc.h (CpuABM): Removed.
466 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
467 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
468 popcnt. Remove CpuABM from lzcnt.
469 * i386-init.h: Regenerated.
470 * i386-tbl.h: Likewise.
472 2020-02-17 Jan Beulich <jbeulich@suse.com>
474 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
475 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
476 VexW1 instead of open-coding them.
477 * i386-tbl.h: Re-generate.
479 2020-02-17 Jan Beulich <jbeulich@suse.com>
481 * i386-opc.tbl (AddrPrefixOpReg): Define.
482 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
483 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
484 templates. Drop NoRex64.
485 * i386-tbl.h: Re-generate.
487 2020-02-17 Jan Beulich <jbeulich@suse.com>
490 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
491 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
492 into Intel syntax instance (with Unpsecified) and AT&T one
494 (vcvtneps2bf16): Likewise, along with folding the two so far
496 * i386-tbl.h: Re-generate.
498 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
500 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
503 2020-02-17 Alan Modra <amodra@gmail.com>
505 * i386-gen.c (cpu_flag_init): Correct last change.
507 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
509 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
512 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
514 * i386-opc.tbl (movsx): Remove Intel syntax comments.
517 2020-02-14 Jan Beulich <jbeulich@suse.com>
520 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
521 destination for Cpu64-only variant.
522 (movzx): Fold patterns.
523 * i386-tbl.h: Re-generate.
525 2020-02-13 Jan Beulich <jbeulich@suse.com>
527 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
528 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
529 CPU_ANY_SSE4_FLAGS entry.
530 * i386-init.h: Re-generate.
532 2020-02-12 Jan Beulich <jbeulich@suse.com>
534 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
535 with Unspecified, making the present one AT&T syntax only.
536 * i386-tbl.h: Re-generate.
538 2020-02-12 Jan Beulich <jbeulich@suse.com>
540 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
541 * i386-tbl.h: Re-generate.
543 2020-02-12 Jan Beulich <jbeulich@suse.com>
546 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
547 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
548 Amd64 and Intel64 templates.
549 (call, jmp): Likewise for far indirect variants. Dro
551 * i386-tbl.h: Re-generate.
553 2020-02-11 Jan Beulich <jbeulich@suse.com>
555 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
556 * i386-opc.h (ShortForm): Delete.
557 (struct i386_opcode_modifier): Remove shortform field.
558 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
559 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
560 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
561 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
563 * i386-tbl.h: Re-generate.
565 2020-02-11 Jan Beulich <jbeulich@suse.com>
567 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
568 fucompi): Drop ShortForm from operand-less templates.
569 * i386-tbl.h: Re-generate.
571 2020-02-11 Alan Modra <amodra@gmail.com>
573 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
574 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
575 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
576 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
577 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
579 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
581 * arm-dis.c (print_insn_cde): Define 'V' parse character.
582 (cde_opcodes): Add VCX* instructions.
584 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
585 Matthew Malcomson <matthew.malcomson@arm.com>
587 * arm-dis.c (struct cdeopcode32): New.
588 (CDE_OPCODE): New macro.
589 (cde_opcodes): New disassembly table.
590 (regnames): New option to table.
591 (cde_coprocs): New global variable.
592 (print_insn_cde): New
593 (print_insn_thumb32): Use print_insn_cde.
594 (parse_arm_disassembler_options): Parse coprocN args.
596 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
599 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
601 * i386-opc.h (AMD64): Removed.
605 (INTEL64ONLY): Likewise.
606 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
607 * i386-opc.tbl (Amd64): New.
609 (Intel64Only): Likewise.
610 Replace AMD64 with Amd64. Update sysenter/sysenter with
611 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
612 * i386-tbl.h: Regenerated.
614 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
617 * z80-dis.c: Add support for GBZ80 opcodes.
619 2020-02-04 Alan Modra <amodra@gmail.com>
621 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
623 2020-02-03 Alan Modra <amodra@gmail.com>
625 * m32c-ibld.c: Regenerate.
627 2020-02-01 Alan Modra <amodra@gmail.com>
629 * frv-ibld.c: Regenerate.
631 2020-01-31 Jan Beulich <jbeulich@suse.com>
633 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
634 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
635 (OP_E_memory): Replace xmm_mdq_mode case label by
636 vex_scalar_w_dq_mode one.
637 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
639 2020-01-31 Jan Beulich <jbeulich@suse.com>
641 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
642 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
643 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
644 (intel_operand_size): Drop vex_w_dq_mode case label.
646 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
648 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
649 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
651 2020-01-30 Alan Modra <amodra@gmail.com>
653 * m32c-ibld.c: Regenerate.
655 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
657 * bpf-opc.c: Regenerate.
659 2020-01-30 Jan Beulich <jbeulich@suse.com>
661 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
662 (dis386): Use them to replace C2/C3 table entries.
663 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
664 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
665 ones. Use Size64 instead of DefaultSize on Intel64 ones.
666 * i386-tbl.h: Re-generate.
668 2020-01-30 Jan Beulich <jbeulich@suse.com>
670 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
672 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
674 * i386-tbl.h: Re-generate.
676 2020-01-30 Alan Modra <amodra@gmail.com>
678 * tic4x-dis.c (tic4x_dp): Make unsigned.
680 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
681 Jan Beulich <jbeulich@suse.com>
684 * i386-dis.c (MOVSXD_Fixup): New function.
685 (movsxd_mode): New enum.
686 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
687 (intel_operand_size): Handle movsxd_mode.
688 (OP_E_register): Likewise.
690 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
691 register on movsxd. Add movsxd with 16-bit destination register
692 for AMD64 and Intel64 ISAs.
693 * i386-tbl.h: Regenerated.
695 2020-01-27 Tamar Christina <tamar.christina@arm.com>
698 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
699 * aarch64-asm-2.c: Regenerate
700 * aarch64-dis-2.c: Likewise.
701 * aarch64-opc-2.c: Likewise.
703 2020-01-21 Jan Beulich <jbeulich@suse.com>
705 * i386-opc.tbl (sysret): Drop DefaultSize.
706 * i386-tbl.h: Re-generate.
708 2020-01-21 Jan Beulich <jbeulich@suse.com>
710 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
712 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
713 * i386-tbl.h: Re-generate.
715 2020-01-20 Nick Clifton <nickc@redhat.com>
717 * po/de.po: Updated German translation.
718 * po/pt_BR.po: Updated Brazilian Portuguese translation.
719 * po/uk.po: Updated Ukranian translation.
721 2020-01-20 Alan Modra <amodra@gmail.com>
723 * hppa-dis.c (fput_const): Remove useless cast.
725 2020-01-20 Alan Modra <amodra@gmail.com>
727 * arm-dis.c (print_insn_arm): Wrap 'T' value.
729 2020-01-18 Nick Clifton <nickc@redhat.com>
731 * configure: Regenerate.
732 * po/opcodes.pot: Regenerate.
734 2020-01-18 Nick Clifton <nickc@redhat.com>
736 Binutils 2.34 branch created.
738 2020-01-17 Christian Biesinger <cbiesinger@google.com>
740 * opintl.h: Fix spelling error (seperate).
742 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
744 * i386-opc.tbl: Add {vex} pseudo prefix.
745 * i386-tbl.h: Regenerated.
747 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
750 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
751 (neon_opcodes): Likewise.
752 (select_arm_features): Make sure we enable MVE bits when selecting
753 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
756 2020-01-16 Jan Beulich <jbeulich@suse.com>
758 * i386-opc.tbl: Drop stale comment from XOP section.
760 2020-01-16 Jan Beulich <jbeulich@suse.com>
762 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
763 (extractps): Add VexWIG to SSE2AVX forms.
764 * i386-tbl.h: Re-generate.
766 2020-01-16 Jan Beulich <jbeulich@suse.com>
768 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
769 Size64 from and use VexW1 on SSE2AVX forms.
770 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
771 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
772 * i386-tbl.h: Re-generate.
774 2020-01-15 Alan Modra <amodra@gmail.com>
776 * tic4x-dis.c (tic4x_version): Make unsigned long.
777 (optab, optab_special, registernames): New file scope vars.
778 (tic4x_print_register): Set up registernames rather than
779 malloc'd registertable.
780 (tic4x_disassemble): Delete optable and optable_special. Use
781 optab and optab_special instead. Throw away old optab,
782 optab_special and registernames when info->mach changes.
784 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
787 * z80-dis.c (suffix): Use .db instruction to generate double
790 2020-01-14 Alan Modra <amodra@gmail.com>
792 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
793 values to unsigned before shifting.
795 2020-01-13 Thomas Troeger <tstroege@gmx.de>
797 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
799 (print_insn_thumb16, print_insn_thumb32): Likewise.
800 (print_insn): Initialize the insn info.
801 * i386-dis.c (print_insn): Initialize the insn info fields, and
804 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
806 * arc-opc.c (C_NE): Make it required.
808 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
810 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
811 reserved register name.
813 2020-01-13 Alan Modra <amodra@gmail.com>
815 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
816 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
818 2020-01-13 Alan Modra <amodra@gmail.com>
820 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
821 result of wasm_read_leb128 in a uint64_t and check that bits
822 are not lost when copying to other locals. Use uint32_t for
823 most locals. Use PRId64 when printing int64_t.
825 2020-01-13 Alan Modra <amodra@gmail.com>
827 * score-dis.c: Formatting.
828 * score7-dis.c: Formatting.
830 2020-01-13 Alan Modra <amodra@gmail.com>
832 * score-dis.c (print_insn_score48): Use unsigned variables for
833 unsigned values. Don't left shift negative values.
834 (print_insn_score32): Likewise.
835 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
837 2020-01-13 Alan Modra <amodra@gmail.com>
839 * tic4x-dis.c (tic4x_print_register): Remove dead code.
841 2020-01-13 Alan Modra <amodra@gmail.com>
843 * fr30-ibld.c: Regenerate.
845 2020-01-13 Alan Modra <amodra@gmail.com>
847 * xgate-dis.c (print_insn): Don't left shift signed value.
848 (ripBits): Formatting, use 1u.
850 2020-01-10 Alan Modra <amodra@gmail.com>
852 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
853 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
855 2020-01-10 Alan Modra <amodra@gmail.com>
857 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
858 and XRREG value earlier to avoid a shift with negative exponent.
859 * m10200-dis.c (disassemble): Similarly.
861 2020-01-09 Nick Clifton <nickc@redhat.com>
864 * z80-dis.c (ld_ii_ii): Use correct cast.
866 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
869 * z80-dis.c (ld_ii_ii): Use character constant when checking
872 2020-01-09 Jan Beulich <jbeulich@suse.com>
874 * i386-dis.c (SEP_Fixup): New.
876 (dis386_twobyte): Use it for sysenter/sysexit.
877 (enum x86_64_isa): Change amd64 enumerator to value 1.
878 (OP_J): Compare isa64 against intel64 instead of amd64.
879 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
881 * i386-tbl.h: Re-generate.
883 2020-01-08 Alan Modra <amodra@gmail.com>
885 * z8k-dis.c: Include libiberty.h
886 (instr_data_s): Make max_fetched unsigned.
887 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
888 Don't exceed byte_info bounds.
889 (output_instr): Make num_bytes unsigned.
890 (unpack_instr): Likewise for nibl_count and loop.
891 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
893 * z8k-opc.h: Regenerate.
895 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
897 * arc-tbl.h (llock): Use 'LLOCK' as class.
899 (scond): Use 'SCOND' as class.
901 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
904 2020-01-06 Alan Modra <amodra@gmail.com>
906 * m32c-ibld.c: Regenerate.
908 2020-01-06 Alan Modra <amodra@gmail.com>
911 * z80-dis.c (suffix): Don't use a local struct buffer copy.
912 Peek at next byte to prevent recursion on repeated prefix bytes.
913 Ensure uninitialised "mybuf" is not accessed.
914 (print_insn_z80): Don't zero n_fetch and n_used here,..
915 (print_insn_z80_buf): ..do it here instead.
917 2020-01-04 Alan Modra <amodra@gmail.com>
919 * m32r-ibld.c: Regenerate.
921 2020-01-04 Alan Modra <amodra@gmail.com>
923 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
925 2020-01-04 Alan Modra <amodra@gmail.com>
927 * crx-dis.c (match_opcode): Avoid shift left of signed value.
929 2020-01-04 Alan Modra <amodra@gmail.com>
931 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
933 2020-01-03 Jan Beulich <jbeulich@suse.com>
935 * aarch64-tbl.h (aarch64_opcode_table): Use
936 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
938 2020-01-03 Jan Beulich <jbeulich@suse.com>
940 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
941 forms of SUDOT and USDOT.
943 2020-01-03 Jan Beulich <jbeulich@suse.com>
945 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
947 * opcodes/aarch64-dis-2.c: Re-generate.
949 2020-01-03 Jan Beulich <jbeulich@suse.com>
951 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
953 * opcodes/aarch64-dis-2.c: Re-generate.
955 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
957 * z80-dis.c: Add support for eZ80 and Z80 instructions.
959 2020-01-01 Alan Modra <amodra@gmail.com>
961 Update year range in copyright notice of all files.
963 For older changes see ChangeLog-2019
965 Copyright (C) 2020 Free Software Foundation, Inc.
967 Copying and distribution of this file, with or without modification,
968 are permitted in any medium without royalty provided the copyright
969 notice and this notice are preserved.
975 version-control: never