1 2020-03-22 Alan Modra <amodra@gmail.com>
3 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
4 * s12z-opc.c: Formatting.
5 (operands_f): Return an int.
6 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
7 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
8 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
9 (exg_sex_discrim): Likewise.
10 (create_immediate_operand, create_bitfield_operand),
11 (create_register_operand_with_size, create_register_all_operand),
12 (create_register_all16_operand, create_simple_memory_operand),
13 (create_memory_operand, create_memory_auto_operand): Don't
14 segfault on malloc failure.
15 (z_ext24_decode): Return an int status, negative on fail, zero
17 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
18 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
19 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
20 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
21 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
22 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
23 (loop_primitive_decode, shift_decode, psh_pul_decode),
24 (bit_field_decode): Similarly.
25 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
26 to return value, update callers.
27 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
28 Don't segfault on NULL operand.
29 (decode_operation): Return OP_INVALID on first fail.
30 (decode_s12z): Check all reads, returning -1 on fail.
32 2020-03-20 Alan Modra <amodra@gmail.com>
34 * metag-dis.c (print_insn_metag): Don't ignore status from
37 2020-03-20 Alan Modra <amodra@gmail.com>
39 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
40 Initialize parts of buffer not written when handling a possible
41 2-byte insn at end of section. Don't attempt decoding of such
42 an insn by the 4-byte machinery.
44 2020-03-20 Alan Modra <amodra@gmail.com>
46 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
47 partially filled buffer. Prevent lookup of 4-byte insns when
48 only VLE 2-byte insns are possible due to section size. Print
49 ".word" rather than ".long" for 2-byte leftovers.
51 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
54 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
56 2020-03-13 Jan Beulich <jbeulich@suse.com>
58 * i386-dis.c (X86_64_0D): Rename to ...
59 (X86_64_0E): ... this.
61 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
63 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
64 * Makefile.in: Regenerated.
66 2020-03-09 Jan Beulich <jbeulich@suse.com>
68 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
70 * i386-tbl.h: Re-generate.
72 2020-03-09 Jan Beulich <jbeulich@suse.com>
74 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
75 vprot*, vpsha*, and vpshl*.
76 * i386-tbl.h: Re-generate.
78 2020-03-09 Jan Beulich <jbeulich@suse.com>
80 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
81 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
82 * i386-tbl.h: Re-generate.
84 2020-03-09 Jan Beulich <jbeulich@suse.com>
86 * i386-gen.c (set_bitfield): Ignore zero-length field names.
87 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
88 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
89 * i386-tbl.h: Re-generate.
91 2020-03-09 Jan Beulich <jbeulich@suse.com>
93 * i386-gen.c (struct template_arg, struct template_instance,
94 struct template_param, struct template, templates,
95 parse_template, expand_templates): New.
96 (process_i386_opcodes): Various local variables moved to
97 expand_templates. Call parse_template and expand_templates.
98 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
99 * i386-tbl.h: Re-generate.
101 2020-03-06 Jan Beulich <jbeulich@suse.com>
103 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
104 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
105 register and memory source templates. Replace VexW= by VexW*
107 * i386-tbl.h: Re-generate.
109 2020-03-06 Jan Beulich <jbeulich@suse.com>
111 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
112 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
113 * i386-tbl.h: Re-generate.
115 2020-03-06 Jan Beulich <jbeulich@suse.com>
117 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
118 * i386-tbl.h: Re-generate.
120 2020-03-06 Jan Beulich <jbeulich@suse.com>
122 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
123 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
124 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
125 VexW0 on SSE2AVX variants.
126 (vmovq): Drop NoRex64 from XMM/XMM variants.
127 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
128 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
129 applicable use VexW0.
130 * i386-tbl.h: Re-generate.
132 2020-03-06 Jan Beulich <jbeulich@suse.com>
134 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
135 * i386-opc.h (Rex64): Delete.
136 (struct i386_opcode_modifier): Remove rex64 field.
137 * i386-opc.tbl (crc32): Drop Rex64.
138 Replace Rex64 with Size64 everywhere else.
139 * i386-tbl.h: Re-generate.
141 2020-03-06 Jan Beulich <jbeulich@suse.com>
143 * i386-dis.c (OP_E_memory): Exclude recording of used address
144 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
145 addressed memory operands for MPX insns.
147 2020-03-06 Jan Beulich <jbeulich@suse.com>
149 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
150 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
151 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
152 (ptwrite): Split into non-64-bit and 64-bit forms.
153 * i386-tbl.h: Re-generate.
155 2020-03-06 Jan Beulich <jbeulich@suse.com>
157 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
159 * i386-tbl.h: Re-generate.
161 2020-03-04 Jan Beulich <jbeulich@suse.com>
163 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
164 (prefix_table): Move vmmcall here. Add vmgexit.
165 (rm_table): Replace vmmcall entry by prefix_table[] escape.
166 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
167 (cpu_flags): Add CpuSEV_ES entry.
168 * i386-opc.h (CpuSEV_ES): New.
169 (union i386_cpu_flags): Add cpusev_es field.
170 * i386-opc.tbl (vmgexit): New.
171 * i386-init.h, i386-tbl.h: Re-generate.
173 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
175 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
177 * i386-opc.h (IGNORESIZE): New.
178 (DEFAULTSIZE): Likewise.
179 (IgnoreSize): Removed.
180 (DefaultSize): Likewise.
182 (i386_opcode_modifier): Replace ignoresize/defaultsize with
184 * i386-opc.tbl (IgnoreSize): New.
185 (DefaultSize): Likewise.
186 * i386-tbl.h: Regenerated.
188 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
191 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
194 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
197 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
198 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
199 * i386-tbl.h: Regenerated.
201 2020-02-26 Alan Modra <amodra@gmail.com>
203 * aarch64-asm.c: Indent labels correctly.
204 * aarch64-dis.c: Likewise.
205 * aarch64-gen.c: Likewise.
206 * aarch64-opc.c: Likewise.
207 * alpha-dis.c: Likewise.
208 * i386-dis.c: Likewise.
209 * nds32-asm.c: Likewise.
210 * nfp-dis.c: Likewise.
211 * visium-dis.c: Likewise.
213 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
215 * arc-regs.h (int_vector_base): Make it available for all ARC
218 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
220 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
223 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
225 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
226 c.mv/c.li if rs1 is zero.
228 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
230 * i386-gen.c (cpu_flag_init): Replace CpuABM with
231 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
233 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
234 * i386-opc.h (CpuABM): Removed.
236 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
237 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
238 popcnt. Remove CpuABM from lzcnt.
239 * i386-init.h: Regenerated.
240 * i386-tbl.h: Likewise.
242 2020-02-17 Jan Beulich <jbeulich@suse.com>
244 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
245 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
246 VexW1 instead of open-coding them.
247 * i386-tbl.h: Re-generate.
249 2020-02-17 Jan Beulich <jbeulich@suse.com>
251 * i386-opc.tbl (AddrPrefixOpReg): Define.
252 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
253 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
254 templates. Drop NoRex64.
255 * i386-tbl.h: Re-generate.
257 2020-02-17 Jan Beulich <jbeulich@suse.com>
260 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
261 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
262 into Intel syntax instance (with Unpsecified) and AT&T one
264 (vcvtneps2bf16): Likewise, along with folding the two so far
266 * i386-tbl.h: Re-generate.
268 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
270 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
273 2020-02-17 Alan Modra <amodra@gmail.com>
275 * i386-gen.c (cpu_flag_init): Correct last change.
277 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
279 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
282 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
284 * i386-opc.tbl (movsx): Remove Intel syntax comments.
287 2020-02-14 Jan Beulich <jbeulich@suse.com>
290 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
291 destination for Cpu64-only variant.
292 (movzx): Fold patterns.
293 * i386-tbl.h: Re-generate.
295 2020-02-13 Jan Beulich <jbeulich@suse.com>
297 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
298 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
299 CPU_ANY_SSE4_FLAGS entry.
300 * i386-init.h: Re-generate.
302 2020-02-12 Jan Beulich <jbeulich@suse.com>
304 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
305 with Unspecified, making the present one AT&T syntax only.
306 * i386-tbl.h: Re-generate.
308 2020-02-12 Jan Beulich <jbeulich@suse.com>
310 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
311 * i386-tbl.h: Re-generate.
313 2020-02-12 Jan Beulich <jbeulich@suse.com>
316 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
317 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
318 Amd64 and Intel64 templates.
319 (call, jmp): Likewise for far indirect variants. Dro
321 * i386-tbl.h: Re-generate.
323 2020-02-11 Jan Beulich <jbeulich@suse.com>
325 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
326 * i386-opc.h (ShortForm): Delete.
327 (struct i386_opcode_modifier): Remove shortform field.
328 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
329 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
330 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
331 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
333 * i386-tbl.h: Re-generate.
335 2020-02-11 Jan Beulich <jbeulich@suse.com>
337 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
338 fucompi): Drop ShortForm from operand-less templates.
339 * i386-tbl.h: Re-generate.
341 2020-02-11 Alan Modra <amodra@gmail.com>
343 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
344 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
345 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
346 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
347 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
349 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
351 * arm-dis.c (print_insn_cde): Define 'V' parse character.
352 (cde_opcodes): Add VCX* instructions.
354 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
355 Matthew Malcomson <matthew.malcomson@arm.com>
357 * arm-dis.c (struct cdeopcode32): New.
358 (CDE_OPCODE): New macro.
359 (cde_opcodes): New disassembly table.
360 (regnames): New option to table.
361 (cde_coprocs): New global variable.
362 (print_insn_cde): New
363 (print_insn_thumb32): Use print_insn_cde.
364 (parse_arm_disassembler_options): Parse coprocN args.
366 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
369 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
371 * i386-opc.h (AMD64): Removed.
375 (INTEL64ONLY): Likewise.
376 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
377 * i386-opc.tbl (Amd64): New.
379 (Intel64Only): Likewise.
380 Replace AMD64 with Amd64. Update sysenter/sysenter with
381 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
382 * i386-tbl.h: Regenerated.
384 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
387 * z80-dis.c: Add support for GBZ80 opcodes.
389 2020-02-04 Alan Modra <amodra@gmail.com>
391 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
393 2020-02-03 Alan Modra <amodra@gmail.com>
395 * m32c-ibld.c: Regenerate.
397 2020-02-01 Alan Modra <amodra@gmail.com>
399 * frv-ibld.c: Regenerate.
401 2020-01-31 Jan Beulich <jbeulich@suse.com>
403 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
404 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
405 (OP_E_memory): Replace xmm_mdq_mode case label by
406 vex_scalar_w_dq_mode one.
407 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
409 2020-01-31 Jan Beulich <jbeulich@suse.com>
411 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
412 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
413 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
414 (intel_operand_size): Drop vex_w_dq_mode case label.
416 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
418 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
419 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
421 2020-01-30 Alan Modra <amodra@gmail.com>
423 * m32c-ibld.c: Regenerate.
425 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
427 * bpf-opc.c: Regenerate.
429 2020-01-30 Jan Beulich <jbeulich@suse.com>
431 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
432 (dis386): Use them to replace C2/C3 table entries.
433 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
434 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
435 ones. Use Size64 instead of DefaultSize on Intel64 ones.
436 * i386-tbl.h: Re-generate.
438 2020-01-30 Jan Beulich <jbeulich@suse.com>
440 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
442 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
444 * i386-tbl.h: Re-generate.
446 2020-01-30 Alan Modra <amodra@gmail.com>
448 * tic4x-dis.c (tic4x_dp): Make unsigned.
450 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
451 Jan Beulich <jbeulich@suse.com>
454 * i386-dis.c (MOVSXD_Fixup): New function.
455 (movsxd_mode): New enum.
456 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
457 (intel_operand_size): Handle movsxd_mode.
458 (OP_E_register): Likewise.
460 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
461 register on movsxd. Add movsxd with 16-bit destination register
462 for AMD64 and Intel64 ISAs.
463 * i386-tbl.h: Regenerated.
465 2020-01-27 Tamar Christina <tamar.christina@arm.com>
468 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
469 * aarch64-asm-2.c: Regenerate
470 * aarch64-dis-2.c: Likewise.
471 * aarch64-opc-2.c: Likewise.
473 2020-01-21 Jan Beulich <jbeulich@suse.com>
475 * i386-opc.tbl (sysret): Drop DefaultSize.
476 * i386-tbl.h: Re-generate.
478 2020-01-21 Jan Beulich <jbeulich@suse.com>
480 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
482 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
483 * i386-tbl.h: Re-generate.
485 2020-01-20 Nick Clifton <nickc@redhat.com>
487 * po/de.po: Updated German translation.
488 * po/pt_BR.po: Updated Brazilian Portuguese translation.
489 * po/uk.po: Updated Ukranian translation.
491 2020-01-20 Alan Modra <amodra@gmail.com>
493 * hppa-dis.c (fput_const): Remove useless cast.
495 2020-01-20 Alan Modra <amodra@gmail.com>
497 * arm-dis.c (print_insn_arm): Wrap 'T' value.
499 2020-01-18 Nick Clifton <nickc@redhat.com>
501 * configure: Regenerate.
502 * po/opcodes.pot: Regenerate.
504 2020-01-18 Nick Clifton <nickc@redhat.com>
506 Binutils 2.34 branch created.
508 2020-01-17 Christian Biesinger <cbiesinger@google.com>
510 * opintl.h: Fix spelling error (seperate).
512 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
514 * i386-opc.tbl: Add {vex} pseudo prefix.
515 * i386-tbl.h: Regenerated.
517 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
520 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
521 (neon_opcodes): Likewise.
522 (select_arm_features): Make sure we enable MVE bits when selecting
523 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
526 2020-01-16 Jan Beulich <jbeulich@suse.com>
528 * i386-opc.tbl: Drop stale comment from XOP section.
530 2020-01-16 Jan Beulich <jbeulich@suse.com>
532 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
533 (extractps): Add VexWIG to SSE2AVX forms.
534 * i386-tbl.h: Re-generate.
536 2020-01-16 Jan Beulich <jbeulich@suse.com>
538 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
539 Size64 from and use VexW1 on SSE2AVX forms.
540 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
541 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
542 * i386-tbl.h: Re-generate.
544 2020-01-15 Alan Modra <amodra@gmail.com>
546 * tic4x-dis.c (tic4x_version): Make unsigned long.
547 (optab, optab_special, registernames): New file scope vars.
548 (tic4x_print_register): Set up registernames rather than
549 malloc'd registertable.
550 (tic4x_disassemble): Delete optable and optable_special. Use
551 optab and optab_special instead. Throw away old optab,
552 optab_special and registernames when info->mach changes.
554 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
557 * z80-dis.c (suffix): Use .db instruction to generate double
560 2020-01-14 Alan Modra <amodra@gmail.com>
562 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
563 values to unsigned before shifting.
565 2020-01-13 Thomas Troeger <tstroege@gmx.de>
567 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
569 (print_insn_thumb16, print_insn_thumb32): Likewise.
570 (print_insn): Initialize the insn info.
571 * i386-dis.c (print_insn): Initialize the insn info fields, and
574 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
576 * arc-opc.c (C_NE): Make it required.
578 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
580 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
581 reserved register name.
583 2020-01-13 Alan Modra <amodra@gmail.com>
585 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
586 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
588 2020-01-13 Alan Modra <amodra@gmail.com>
590 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
591 result of wasm_read_leb128 in a uint64_t and check that bits
592 are not lost when copying to other locals. Use uint32_t for
593 most locals. Use PRId64 when printing int64_t.
595 2020-01-13 Alan Modra <amodra@gmail.com>
597 * score-dis.c: Formatting.
598 * score7-dis.c: Formatting.
600 2020-01-13 Alan Modra <amodra@gmail.com>
602 * score-dis.c (print_insn_score48): Use unsigned variables for
603 unsigned values. Don't left shift negative values.
604 (print_insn_score32): Likewise.
605 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
607 2020-01-13 Alan Modra <amodra@gmail.com>
609 * tic4x-dis.c (tic4x_print_register): Remove dead code.
611 2020-01-13 Alan Modra <amodra@gmail.com>
613 * fr30-ibld.c: Regenerate.
615 2020-01-13 Alan Modra <amodra@gmail.com>
617 * xgate-dis.c (print_insn): Don't left shift signed value.
618 (ripBits): Formatting, use 1u.
620 2020-01-10 Alan Modra <amodra@gmail.com>
622 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
623 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
625 2020-01-10 Alan Modra <amodra@gmail.com>
627 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
628 and XRREG value earlier to avoid a shift with negative exponent.
629 * m10200-dis.c (disassemble): Similarly.
631 2020-01-09 Nick Clifton <nickc@redhat.com>
634 * z80-dis.c (ld_ii_ii): Use correct cast.
636 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
639 * z80-dis.c (ld_ii_ii): Use character constant when checking
642 2020-01-09 Jan Beulich <jbeulich@suse.com>
644 * i386-dis.c (SEP_Fixup): New.
646 (dis386_twobyte): Use it for sysenter/sysexit.
647 (enum x86_64_isa): Change amd64 enumerator to value 1.
648 (OP_J): Compare isa64 against intel64 instead of amd64.
649 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
651 * i386-tbl.h: Re-generate.
653 2020-01-08 Alan Modra <amodra@gmail.com>
655 * z8k-dis.c: Include libiberty.h
656 (instr_data_s): Make max_fetched unsigned.
657 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
658 Don't exceed byte_info bounds.
659 (output_instr): Make num_bytes unsigned.
660 (unpack_instr): Likewise for nibl_count and loop.
661 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
663 * z8k-opc.h: Regenerate.
665 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
667 * arc-tbl.h (llock): Use 'LLOCK' as class.
669 (scond): Use 'SCOND' as class.
671 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
674 2020-01-06 Alan Modra <amodra@gmail.com>
676 * m32c-ibld.c: Regenerate.
678 2020-01-06 Alan Modra <amodra@gmail.com>
681 * z80-dis.c (suffix): Don't use a local struct buffer copy.
682 Peek at next byte to prevent recursion on repeated prefix bytes.
683 Ensure uninitialised "mybuf" is not accessed.
684 (print_insn_z80): Don't zero n_fetch and n_used here,..
685 (print_insn_z80_buf): ..do it here instead.
687 2020-01-04 Alan Modra <amodra@gmail.com>
689 * m32r-ibld.c: Regenerate.
691 2020-01-04 Alan Modra <amodra@gmail.com>
693 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
695 2020-01-04 Alan Modra <amodra@gmail.com>
697 * crx-dis.c (match_opcode): Avoid shift left of signed value.
699 2020-01-04 Alan Modra <amodra@gmail.com>
701 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
703 2020-01-03 Jan Beulich <jbeulich@suse.com>
705 * aarch64-tbl.h (aarch64_opcode_table): Use
706 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
708 2020-01-03 Jan Beulich <jbeulich@suse.com>
710 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
711 forms of SUDOT and USDOT.
713 2020-01-03 Jan Beulich <jbeulich@suse.com>
715 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
717 * opcodes/aarch64-dis-2.c: Re-generate.
719 2020-01-03 Jan Beulich <jbeulich@suse.com>
721 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
723 * opcodes/aarch64-dis-2.c: Re-generate.
725 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
727 * z80-dis.c: Add support for eZ80 and Z80 instructions.
729 2020-01-01 Alan Modra <amodra@gmail.com>
731 Update year range in copyright notice of all files.
733 For older changes see ChangeLog-2019
735 Copyright (C) 2020 Free Software Foundation, Inc.
737 Copying and distribution of this file, with or without modification,
738 are permitted in any medium without royalty provided the copyright
739 notice and this notice are preserved.
745 version-control: never