1 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
3 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
5 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
7 * arc-dis.c (enforced_isa_mask): Declare.
9 (parse_cpu_option): New function.
10 (parse_disassembler_options): Use it.
11 (print_insn_arc): Use enforced_isa_mask.
12 (print_arc_disassembler_options): Document new options.
14 2017-05-24 Yao Qi <yao.qi@linaro.org>
16 * alpha-dis.c: Include disassemble.h, don't include
18 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
19 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
20 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
21 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
22 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
23 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
24 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
25 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
26 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
27 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
28 * moxie-dis.c, msp430-dis.c, mt-dis.c:
29 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
30 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
31 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
32 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
33 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
34 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
35 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
36 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
37 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
38 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
39 * z80-dis.c, z8k-dis.c: Likewise.
40 * disassemble.h: New file.
42 2017-05-24 Yao Qi <yao.qi@linaro.org>
44 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
45 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
47 2017-05-24 Yao Qi <yao.qi@linaro.org>
49 * disassemble.c (disassembler): Add arguments a, big and mach.
52 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
54 * i386-dis.c (NOTRACK_Fixup): New.
56 (NOTRACK_PREFIX): Likewise.
57 (last_active_prefix): Likewise.
58 (reg_table): Use NOTRACK on indirect call and jmp.
59 (ckprefix): Set last_active_prefix.
60 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
61 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
62 * i386-opc.h (NoTrackPrefixOk): New.
63 (i386_opcode_modifier): Add notrackprefixok.
64 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
66 * i386-tbl.h: Regenerated.
68 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
70 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
72 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
74 (print_insn_sparc): Handle new operand types.
75 * sparc-opc.c (MASK_M8): Define.
88 (v9andleon): Likewise.
92 (sparc_opcode_archs): Add entry for "m8".
93 (sparc_opcodes): Add OSA2017 and M8 instructions
94 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
96 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
97 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
98 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
99 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
100 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
101 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
102 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
103 ASI_CORE_SELECT_COMMIT_NHT.
105 2017-05-18 Alan Modra <amodra@gmail.com>
107 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
108 * aarch64-dis.c: Likewise.
109 * aarch64-gen.c: Likewise.
110 * aarch64-opc.c: Likewise.
112 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
113 Matthew Fortune <matthew.fortune@imgtec.com>
115 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
116 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
117 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
118 (print_insn_arg) <OP_REG28>: Add handler.
119 (validate_insn_args) <OP_REG28>: Handle.
120 (print_mips16_insn_arg): Handle MIPS16 instructions that require
121 32-bit encoding and 9-bit immediates.
122 (print_insn_mips16): Handle MIPS16 instructions that require
123 32-bit encoding and MFC0/MTC0 operand decoding.
124 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
125 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
126 (RD_C0, WR_C0, E2, E2MT): New macros.
127 (mips16_opcodes): Add entries for MIPS16e2 instructions:
128 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
129 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
130 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
131 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
132 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
133 instructions, "swl", "swr", "sync" and its "sync_acquire",
134 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
135 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
136 regular/extended entries for original MIPS16 ISA revision
137 instructions whose extended forms are subdecoded in the MIPS16e2
138 ISA revision: "li", "sll" and "srl".
140 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
142 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
143 reference in CP0 move operand decoding.
145 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
147 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
149 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
151 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
153 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
154 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
155 "sync_rmb" and "sync_wmb" as aliases.
156 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
157 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
159 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
161 * arc-dis.c (parse_option): Update quarkse_em option..
162 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
164 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
166 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
168 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
170 2017-05-01 Michael Clark <michaeljclark@mac.com>
172 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
175 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
177 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
178 and branches and not synthetic data instructions.
180 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
182 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
184 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
186 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
187 * arc-opc.c (insert_r13el): New function.
189 * arc-tbl.h: Add new enter/leave variants.
191 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
193 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
195 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
197 * mips-dis.c (print_mips_disassembler_options): Add
200 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
202 * mips16-opc.c (AL): New macro.
203 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
204 of "ld" and "lw" as aliases.
206 2017-04-24 Tamar Christina <tamar.christina@arm.com>
208 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
211 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
212 Alan Modra <amodra@gmail.com>
214 * ppc-opc.c (ELEV): Define.
215 (vle_opcodes): Add se_rfgi and e_sc.
216 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
219 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
221 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
223 2017-04-21 Nick Clifton <nickc@redhat.com>
226 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
229 2017-04-13 Alan Modra <amodra@gmail.com>
231 * epiphany-desc.c: Regenerate.
232 * fr30-desc.c: Regenerate.
233 * frv-desc.c: Regenerate.
234 * ip2k-desc.c: Regenerate.
235 * iq2000-desc.c: Regenerate.
236 * lm32-desc.c: Regenerate.
237 * m32c-desc.c: Regenerate.
238 * m32r-desc.c: Regenerate.
239 * mep-desc.c: Regenerate.
240 * mt-desc.c: Regenerate.
241 * or1k-desc.c: Regenerate.
242 * xc16x-desc.c: Regenerate.
243 * xstormy16-desc.c: Regenerate.
245 2017-04-11 Alan Modra <amodra@gmail.com>
247 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
248 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
249 PPC_OPCODE_TMR for e6500.
250 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
251 (PPCVEC3): Define as PPC_OPCODE_POWER9.
252 (PPCVSX2): Define as PPC_OPCODE_POWER8.
253 (PPCVSX3): Define as PPC_OPCODE_POWER9.
254 (PPCHTM): Define as PPC_OPCODE_POWER8.
255 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
257 2017-04-10 Alan Modra <amodra@gmail.com>
259 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
260 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
261 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
262 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
264 2017-04-09 Pip Cet <pipcet@gmail.com>
266 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
267 appropriate floating-point precision directly.
269 2017-04-07 Alan Modra <amodra@gmail.com>
271 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
272 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
273 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
274 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
275 vector instructions with E6500 not PPCVEC2.
277 2017-04-06 Pip Cet <pipcet@gmail.com>
279 * Makefile.am: Add wasm32-dis.c.
280 * configure.ac: Add wasm32-dis.c to wasm32 target.
281 * disassemble.c: Add wasm32 disassembler code.
282 * wasm32-dis.c: New file.
283 * Makefile.in: Regenerate.
284 * configure: Regenerate.
285 * po/POTFILES.in: Regenerate.
286 * po/opcodes.pot: Regenerate.
288 2017-04-05 Pedro Alves <palves@redhat.com>
290 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
291 * arm-dis.c (parse_arm_disassembler_options): Constify.
292 * ppc-dis.c (powerpc_init_dialect): Constify local.
293 * vax-dis.c (parse_disassembler_options): Constify.
295 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
297 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
300 2017-03-30 Pip Cet <pipcet@gmail.com>
302 * configure.ac: Add (empty) bfd_wasm32_arch target.
303 * configure: Regenerate
304 * po/opcodes.pot: Regenerate.
306 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
308 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
310 * opcodes/sparc-opc.c (asi_table): New ASIs.
312 2017-03-29 Alan Modra <amodra@gmail.com>
314 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
316 (lookup_powerpc): Don't special case -1 dialect. Handle
318 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
319 lookup_powerpc call, pass it on second.
321 2017-03-27 Alan Modra <amodra@gmail.com>
324 * ppc-dis.c (struct ppc_mopt): Comment.
325 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
327 2017-03-27 Rinat Zelig <rinat@mellanox.com>
329 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
330 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
331 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
332 (insert_nps_misc_imm_offset): New function.
333 (extract_nps_misc imm_offset): New function.
334 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
335 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
337 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
339 * s390-mkopc.c (main): Remove vx2 check.
340 * s390-opc.txt: Remove vx2 instruction flags.
342 2017-03-21 Rinat Zelig <rinat@mellanox.com>
344 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
345 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
346 (insert_nps_imm_offset): New function.
347 (extract_nps_imm_offset): New function.
348 (insert_nps_imm_entry): New function.
349 (extract_nps_imm_entry): New function.
351 2017-03-17 Alan Modra <amodra@gmail.com>
354 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
355 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
356 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
358 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
360 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
364 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
366 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
368 2017-03-13 Andrew Waterman <andrew@sifive.com>
370 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
375 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
377 * i386-gen.c (opcode_modifiers): Replace S with Load.
378 * i386-opc.h (S): Removed.
380 (i386_opcode_modifier): Replace s with load.
381 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
382 and {evex}. Replace S with Load.
383 * i386-tbl.h: Regenerated.
385 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
387 * i386-opc.tbl: Use CpuCET on rdsspq.
388 * i386-tbl.h: Regenerated.
390 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
392 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
393 <vsx>: Do not use PPC_OPCODE_VSX3;
395 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
397 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
399 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
401 * i386-dis.c (REG_0F1E_MOD_3): New enum.
402 (MOD_0F1E_PREFIX_1): Likewise.
403 (MOD_0F38F5_PREFIX_2): Likewise.
404 (MOD_0F38F6_PREFIX_0): Likewise.
405 (RM_0F1E_MOD_3_REG_7): Likewise.
406 (PREFIX_MOD_0_0F01_REG_5): Likewise.
407 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
408 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
409 (PREFIX_0F1E): Likewise.
410 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
411 (PREFIX_0F38F5): Likewise.
412 (dis386_twobyte): Use PREFIX_0F1E.
413 (reg_table): Add REG_0F1E_MOD_3.
414 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
415 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
416 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
417 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
418 (three_byte_table): Use PREFIX_0F38F5.
419 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
420 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
421 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
422 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
423 PREFIX_MOD_3_0F01_REG_5_RM_2.
424 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
425 (cpu_flags): Add CpuCET.
426 * i386-opc.h (CpuCET): New enum.
427 (CpuUnused): Commented out.
428 (i386_cpu_flags): Add cpucet.
429 * i386-opc.tbl: Add Intel CET instructions.
430 * i386-init.h: Regenerated.
431 * i386-tbl.h: Likewise.
433 2017-03-06 Alan Modra <amodra@gmail.com>
436 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
437 (extract_raq, extract_ras, extract_rbx): New functions.
438 (powerpc_operands): Use opposite corresponding insert function.
440 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
441 register restriction.
443 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
445 * disassemble.c Include "safe-ctype.h".
446 (disassemble_init_for_target): Handle s390 init.
447 (remove_whitespace_and_extra_commas): New function.
448 (disassembler_options_cmp): Likewise.
449 * arm-dis.c: Include "libiberty.h".
451 (regnames): Use long disassembler style names.
452 Add force-thumb and no-force-thumb options.
453 (NUM_ARM_REGNAMES): Rename from this...
454 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
455 (get_arm_regname_num_options): Delete.
456 (set_arm_regname_option): Likewise.
457 (get_arm_regnames): Likewise.
458 (parse_disassembler_options): Likewise.
459 (parse_arm_disassembler_option): Rename from this...
460 (parse_arm_disassembler_options): ...to this. Make static.
461 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
462 (print_insn): Use parse_arm_disassembler_options.
463 (disassembler_options_arm): New function.
464 (print_arm_disassembler_options): Handle updated regnames.
465 * ppc-dis.c: Include "libiberty.h".
466 (ppc_opts): Add "32" and "64" entries.
467 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
468 (powerpc_init_dialect): Add break to switch statement.
469 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
470 (disassembler_options_powerpc): New function.
471 (print_ppc_disassembler_options): Use ARRAY_SIZE.
472 Remove printing of "32" and "64".
473 * s390-dis.c: Include "libiberty.h".
474 (init_flag): Remove unneeded variable.
475 (struct s390_options_t): New structure type.
476 (options): New structure.
477 (init_disasm): Rename from this...
478 (disassemble_init_s390): ...to this. Add initializations for
479 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
480 (print_insn_s390): Delete call to init_disasm.
481 (disassembler_options_s390): New function.
482 (print_s390_disassembler_options): Print using information from
484 * po/opcodes.pot: Regenerate.
486 2017-02-28 Jan Beulich <jbeulich@suse.com>
488 * i386-dis.c (PCMPESTR_Fixup): New.
489 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
490 (prefix_table): Use PCMPESTR_Fixup.
491 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
493 (vex_w_table): Delete VPCMPESTR{I,M} entries.
494 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
495 Split 64-bit and non-64-bit variants.
496 * opcodes/i386-tbl.h: Re-generate.
498 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
500 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
501 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
502 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
503 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
504 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
505 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
506 (OP_SVE_V_HSD): New macros.
507 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
508 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
509 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
510 (aarch64_opcode_table): Add new SVE instructions.
511 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
512 for rotation operands. Add new SVE operands.
513 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
514 (ins_sve_quad_index): Likewise.
515 (ins_imm_rotate): Split into...
516 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
517 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
518 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
520 (aarch64_ins_sve_addr_ri_s4): New function.
521 (aarch64_ins_sve_quad_index): Likewise.
522 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
523 * aarch64-asm-2.c: Regenerate.
524 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
525 (ext_sve_quad_index): Likewise.
526 (ext_imm_rotate): Split into...
527 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
528 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
529 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
531 (aarch64_ext_sve_addr_ri_s4): New function.
532 (aarch64_ext_sve_quad_index): Likewise.
533 (aarch64_ext_sve_index): Allow quad indices.
534 (do_misc_decoding): Likewise.
535 * aarch64-dis-2.c: Regenerate.
536 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
538 (OPD_F_OD_MASK): Widen by one bit.
539 (OPD_F_NO_ZR): Bump accordingly.
540 (get_operand_field_width): New function.
541 * aarch64-opc.c (fields): Add new SVE fields.
542 (operand_general_constraint_met_p): Handle new SVE operands.
543 (aarch64_print_operand): Likewise.
544 * aarch64-opc-2.c: Regenerate.
546 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
548 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
549 (aarch64_feature_compnum): ...this.
550 (SIMD_V8_3): Replace with...
552 (CNUM_INSN): New macro.
553 (aarch64_opcode_table): Use it for the complex number instructions.
555 2017-02-24 Jan Beulich <jbeulich@suse.com>
557 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
559 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
561 Add support for associating SPARC ASIs with an architecture level.
562 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
563 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
564 decoding of SPARC ASIs.
566 2017-02-23 Jan Beulich <jbeulich@suse.com>
568 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
569 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
571 2017-02-21 Jan Beulich <jbeulich@suse.com>
573 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
574 1 (instead of to itself). Correct typo.
576 2017-02-14 Andrew Waterman <andrew@sifive.com>
578 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
581 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
583 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
584 (aarch64_sys_reg_supported_p): Handle them.
586 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
588 * arc-opc.c (UIMM6_20R): Define.
589 (SIMM12_20): Use above.
590 (SIMM12_20R): Define.
591 (SIMM3_5_S): Use above.
592 (UIMM7_A32_11R_S): Define.
593 (UIMM7_9_S): Use above.
594 (UIMM3_13R_S): Define.
595 (SIMM11_A32_7_S): Use above.
597 (UIMM10_A32_8_S): Use above.
598 (UIMM8_8R_S): Define.
600 (arc_relax_opcodes): Use all above defines.
602 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
604 * arc-regs.h: Distinguish some of the registers different on
605 ARC700 and HS38 cpus.
607 2017-02-14 Alan Modra <amodra@gmail.com>
610 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
611 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
613 2017-02-11 Stafford Horne <shorne@gmail.com>
614 Alan Modra <amodra@gmail.com>
616 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
617 Use insn_bytes_value and insn_int_value directly instead. Don't
618 free allocated memory until function exit.
620 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
622 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
624 2017-02-03 Nick Clifton <nickc@redhat.com>
627 * aarch64-opc.c (print_register_list): Ensure that the register
628 list index will fir into the tb buffer.
629 (print_register_offset_address): Likewise.
630 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
632 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
635 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
636 instructions when the previous fetch packet ends with a 32-bit
639 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
641 * pru-opc.c: Remove vague reference to a future GDB port.
643 2017-01-20 Nick Clifton <nickc@redhat.com>
645 * po/ga.po: Updated Irish translation.
647 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
649 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
651 2017-01-13 Yao Qi <yao.qi@linaro.org>
653 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
654 if FETCH_DATA returns 0.
655 (m68k_scan_mask): Likewise.
656 (print_insn_m68k): Update code to handle -1 return value.
658 2017-01-13 Yao Qi <yao.qi@linaro.org>
660 * m68k-dis.c (enum print_insn_arg_error): New.
661 (NEXTBYTE): Replace -3 with
662 PRINT_INSN_ARG_MEMORY_ERROR.
663 (NEXTULONG): Likewise.
664 (NEXTSINGLE): Likewise.
665 (NEXTDOUBLE): Likewise.
666 (NEXTDOUBLE): Likewise.
667 (NEXTPACKED): Likewise.
668 (FETCH_ARG): Likewise.
669 (FETCH_DATA): Update comments.
670 (print_insn_arg): Update comments. Replace magic numbers with
672 (match_insn_m68k): Likewise.
674 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
676 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
677 * i386-dis-evex.h (evex_table): Updated.
678 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
679 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
680 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
681 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
682 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
683 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
684 * i386-init.h: Regenerate.
687 2017-01-12 Yao Qi <yao.qi@linaro.org>
689 * msp430-dis.c (msp430_singleoperand): Return -1 if
690 msp430dis_opcode_signed returns false.
691 (msp430_doubleoperand): Likewise.
692 (msp430_branchinstr): Return -1 if
693 msp430dis_opcode_unsigned returns false.
694 (msp430x_calla_instr): Likewise.
695 (print_insn_msp430): Likewise.
697 2017-01-05 Nick Clifton <nickc@redhat.com>
700 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
701 could not be matched.
702 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
705 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
707 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
708 (aarch64_opcode_table): Use RCPC_INSN.
710 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
712 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
714 * riscv-opcodes/all-opcodes: Likewise.
716 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
718 * riscv-dis.c (print_insn_args): Add fall through comment.
720 2017-01-03 Nick Clifton <nickc@redhat.com>
722 * po/sr.po: New Serbian translation.
723 * configure.ac (ALL_LINGUAS): Add sr.
724 * configure: Regenerate.
726 2017-01-02 Alan Modra <amodra@gmail.com>
728 * epiphany-desc.h: Regenerate.
729 * epiphany-opc.h: Regenerate.
730 * fr30-desc.h: Regenerate.
731 * fr30-opc.h: Regenerate.
732 * frv-desc.h: Regenerate.
733 * frv-opc.h: Regenerate.
734 * ip2k-desc.h: Regenerate.
735 * ip2k-opc.h: Regenerate.
736 * iq2000-desc.h: Regenerate.
737 * iq2000-opc.h: Regenerate.
738 * lm32-desc.h: Regenerate.
739 * lm32-opc.h: Regenerate.
740 * m32c-desc.h: Regenerate.
741 * m32c-opc.h: Regenerate.
742 * m32r-desc.h: Regenerate.
743 * m32r-opc.h: Regenerate.
744 * mep-desc.h: Regenerate.
745 * mep-opc.h: Regenerate.
746 * mt-desc.h: Regenerate.
747 * mt-opc.h: Regenerate.
748 * or1k-desc.h: Regenerate.
749 * or1k-opc.h: Regenerate.
750 * xc16x-desc.h: Regenerate.
751 * xc16x-opc.h: Regenerate.
752 * xstormy16-desc.h: Regenerate.
753 * xstormy16-opc.h: Regenerate.
755 2017-01-02 Alan Modra <amodra@gmail.com>
757 Update year range in copyright notice of all files.
759 For older changes see ChangeLog-2016
761 Copyright (C) 2017 Free Software Foundation, Inc.
763 Copying and distribution of this file, with or without modification,
764 are permitted in any medium without royalty provided the copyright
765 notice and this notice are preserved.
771 version-control: never