1 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
2 Lili Cui <lili.cui@intel.com>
4 * i386-dis.c (PREFIX_VEX_0F3850): New.
5 (PREFIX_VEX_0F3851): Likewise.
6 (PREFIX_VEX_0F3852): Likewise.
7 (PREFIX_VEX_0F3853): Likewise.
8 (VEX_W_0F3850_P_2): Likewise.
9 (VEX_W_0F3851_P_2): Likewise.
10 (VEX_W_0F3852_P_2): Likewise.
11 (VEX_W_0F3853_P_2): Likewise.
12 (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
13 PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
14 (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
15 VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
16 (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
17 * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
18 CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
19 CPU_ANY_AVX_VNNI_FLAGS.
20 (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
21 * i386-opc.h (CpuAVX_VNNI): New.
22 (CpuVEX_PREFIX): Likewise.
23 (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
24 * i386-opc.tbl: Add Intel AVX VNNI instructions.
25 * i386-init.h: Regenerated.
26 * i386-tbl.h: Likewise.
28 2020-10-14 Lili Cui <lili.cui@intel.com>
29 H.J. Lu <hongjiu.lu@intel.com>
31 * i386-dis.c (PREFIX_0F3A0F): New.
32 (MOD_0F3A0F_PREFIX_1): Likewise.
33 (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
34 (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
35 (prefix_table): Add PREFIX_0F3A0F.
36 (mod_table): Add MOD_0F3A0F_PREFIX_1.
37 (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
38 (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
39 * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
41 (cpu_flags): Add CpuHRESET.
42 (output_i386_opcode): Allow 4 byte base_opcode.
43 * i386-opc.h (enum): Add CpuHRESET.
44 (i386_cpu_flags): Add cpuhreset.
45 * i386-opc.tbl: Add Intel HRESET instruction.
46 * i386-init.h: Regenerate.
47 * i386-tbl.h: Likewise.
49 2020-10-14 Lili Cui <lili.cui@intel.com>
51 * i386-dis.c (enum): Add
52 PREFIX_MOD_3_0F01_REG_5_RM_4,
53 PREFIX_MOD_3_0F01_REG_5_RM_5,
54 PREFIX_MOD_3_0F01_REG_5_RM_6,
55 PREFIX_MOD_3_0F01_REG_5_RM_7,
56 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
57 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
58 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
59 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
60 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
61 (prefix_table): New instructions (see prefixes above).
63 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
65 (cpu_flags): Add CpuUINTR.
66 * i386-opc.h (enum): Add CpuUINTR.
67 (i386_cpu_flags): Add cpuuintr.
68 * i386-opc.tbl: Add UINTR insns.
69 * i386-init.h: Regenerate.
70 * i386-tbl.h: Likewise.
72 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
74 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
75 non-VEX/EVEX/prefix encoding.
76 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
78 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
79 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
80 * i386-tbl.h: Regenerated.
82 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
84 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
86 * i386-opc.h (VexOpcode): Renamed to ...
89 (PREFIX_0X66): Likewise.
90 (PREFIX_0XF2): Likewise.
91 (PREFIX_0XF3): Likewise.
92 * i386-opc.tbl (Prefix_0X66): New.
93 (Prefix_0XF2): Likewise.
94 (Prefix_0XF3): Likewise.
95 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
96 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
97 * i386-tbl.h: Regenerated.
99 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
101 * cgen-asm.c: Fix spelling mistakes.
102 * cgen-dis.c: Fix spelling mistakes.
103 * tic30-dis.c: Fix spelling mistakes.
105 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
108 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
110 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
113 * i386-dis.c (print_insn): Clear modrm if not needed.
114 (putop): Check need_modrm for modrm.mod != 3. Don't check
115 need_modrm for modrm.mod == 3.
117 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
119 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
120 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
121 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
122 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
123 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
124 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
125 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
126 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
127 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
128 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
129 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
130 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
131 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
132 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
134 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
136 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
138 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
140 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
141 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
143 2020-09-26 Alan Modra <amodra@gmail.com>
145 * csky-opc.h: Formatting.
146 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
147 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
149 (get_register_number): Likewise.
150 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
152 2020-09-24 Lili Cui <lili.cui@intel.com>
155 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
157 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
159 * csky-dis.c (csky_output_operand): Enclose body of if in curly
162 2020-09-24 Lili Cui <lili.cui@intel.com>
164 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
165 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
166 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
167 X86_64_0F01_REG_1_RM_7_P_2.
168 (prefix_table): Likewise.
169 (x86_64_table): Likewise.
170 (rm_table): Likewise.
171 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
172 and CPU_ANY_TDX_FLAGS.
173 (cpu_flags): Add CpuTDX.
174 * i386-opc.h (enum): Add CpuTDX.
175 (i386_cpu_flags): Add cputdx.
176 * i386-opc.tbl: Add TDX insns.
177 * i386-init.h: Regenerate.
178 * i386-tbl.h: Likewise.
180 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
182 * csky-dis.c (using_abi): New.
183 (parse_csky_dis_options): New function.
184 (get_gr_name): New function.
185 (get_cr_name): New function.
186 (csky_output_operand): Use get_gr_name and get_cr_name to
187 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
188 (print_insn_csky): Parse disassembler options.
189 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
190 (GENARAL_REG_BANK): Define.
191 (REG_SUPPORT_ALL): Define.
192 (REG_SUPPORT_ALL): New.
194 (REG_SUPPORT_A): Define.
195 (REG_SUPPORT_B): Define.
196 (REG_SUPPORT_C): Define.
197 (REG_SUPPORT_D): Define.
198 (REG_SUPPORT_E): Define.
199 (csky_abiv1_general_regs): New.
200 (csky_abiv1_control_regs): New.
201 (csky_abiv2_general_regs): New.
202 (csky_abiv2_control_regs): New.
203 (get_register_name): New function.
204 (get_register_number): New function.
205 (csky_get_general_reg_name): New function.
206 (csky_get_general_regno): New function.
207 (csky_get_control_reg_name): New function.
208 (csky_get_control_regno): New function.
209 (csky_v2_opcodes): Prefer two oprerans format for bclri and
210 bseti, strengthen the operands legality check of addc, zext
213 2020-09-23 Lili Cui <lili.cui@intel.com>
215 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
216 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
217 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
218 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
219 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
220 (reg_table): New instructions (see prefixes above).
221 (prefix_table): Likewise.
222 (three_byte_table): Likewise.
223 (mod_table): Likewise
224 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
225 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
226 (cpu_flags): Likewise.
227 (operand_type_init): Likewise.
228 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
229 (i386_cpu_flags): Add cpukl and cpuwide_kl.
230 * i386-opc.tbl: Add KL and WIDE_KL insns.
231 * i386-init.h: Regenerate.
232 * i386-tbl.h: Likewise.
234 2020-09-21 Alan Modra <amodra@gmail.com>
236 * rx-dis.c (flag_names): Add missing comma.
237 (register_names, flag_names, double_register_names),
238 (double_register_high_names, double_register_low_names),
239 (double_control_register_names, double_condition_names): Remove
242 2020-09-18 David Faust <david.faust@oracle.com>
244 * bpf-desc.c: Regenerate.
245 * bpf-desc.h: Likewise.
246 * bpf-opc.c: Likewise.
247 * bpf-opc.h: Likewise.
249 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
251 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
254 2020-09-16 Alan Modra <amodra@gmail.com>
256 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
258 2020-09-10 Nick Clifton <nickc@redhat.com>
260 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
261 for hidden, local, no-type symbols.
262 (disassemble_init_powerpc): Point the symbol_is_valid field in the
263 info structure at the new function.
265 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
267 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
268 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
271 2020-09-10 Nick Clifton <nickc@redhat.com>
273 * csky-dis.c (csky_output_operand): Coerce the immediate values to
274 long before printing.
276 2020-09-10 Alan Modra <amodra@gmail.com>
278 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
280 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
282 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
285 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
287 * csky-dis.c (csky_output_operand): Add handlers for
288 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
289 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
290 to support FPUV3 instructions.
291 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
292 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
293 OPRND_TYPE_DFLOAT_FMOVI.
294 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
295 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
296 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
297 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
298 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
299 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
300 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
301 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
302 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
303 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
304 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
305 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
306 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
307 (csky_v2_opcodes): Add FPUV3 instructions.
309 2020-09-08 Alex Coplan <alex.coplan@arm.com>
311 * aarch64-dis.c (print_operands): Pass CPU features to
312 aarch64_print_operand().
313 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
314 preferred disassembly of system registers.
315 (SR_RNG): Refactor to use new SR_FEAT2 macro.
321 (SR_EXPAND_ELx): New.
322 (SR_EXPAND_EL12): New.
323 (aarch64_sys_regs): Specify which registers are only on
324 A-profile, add R-profile system registers.
328 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
331 2020-09-08 Alex Coplan <alex.coplan@arm.com>
333 * aarch64-tbl.h (aarch64_feature_v8_r): New.
336 (aarch64_opcode_table): Add dfb.
337 * aarch64-opc-2.c: Regenerate.
338 * aarch64-asm-2.c: Regenerate.
339 * aarch64-dis-2.c: Regenerate.
341 2020-09-08 Alex Coplan <alex.coplan@arm.com>
343 * aarch64-dis.c (arch_variant): New.
344 (determine_disassembling_preference): Disassemble according to
346 (select_aarch64_variant): New.
347 (print_insn_aarch64): Set feature set.
349 2020-09-02 Alan Modra <amodra@gmail.com>
351 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
352 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
353 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
354 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
355 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
356 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
357 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
358 for value parameter and update code to suit.
359 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
360 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
362 2020-09-02 Alan Modra <amodra@gmail.com>
364 * i386-dis.c (OP_E_memory): Don't cast to signed type when
366 (get32, get32s): Use unsigned types in shift expressions.
368 2020-09-02 Alan Modra <amodra@gmail.com>
370 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
372 2020-09-02 Alan Modra <amodra@gmail.com>
374 * crx-dis.c: Whitespace.
375 (print_arg): Use unsigned type for longdisp and mask variables,
376 and for left shift constant.
378 2020-09-02 Alan Modra <amodra@gmail.com>
380 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
381 * bpf-ibld.c: Regenerate.
382 * epiphany-ibld.c: Regenerate.
383 * fr30-ibld.c: Regenerate.
384 * frv-ibld.c: Regenerate.
385 * ip2k-ibld.c: Regenerate.
386 * iq2000-ibld.c: Regenerate.
387 * lm32-ibld.c: Regenerate.
388 * m32c-ibld.c: Regenerate.
389 * m32r-ibld.c: Regenerate.
390 * mep-ibld.c: Regenerate.
391 * mt-ibld.c: Regenerate.
392 * or1k-ibld.c: Regenerate.
393 * xc16x-ibld.c: Regenerate.
394 * xstormy16-ibld.c: Regenerate.
396 2020-09-02 Alan Modra <amodra@gmail.com>
398 * bfin-dis.c (MASKBITS): Use SIGNBIT.
400 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
402 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
403 to CSKYV2_ISA_3E3R3 instruction set.
405 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
407 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
409 2020-09-01 Alan Modra <amodra@gmail.com>
411 * mep-ibld.c: Regenerate.
413 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
415 * csky-dis.c (csky_output_operand): Assign dis_info.value for
418 2020-08-30 Alan Modra <amodra@gmail.com>
420 * cr16-dis.c: Formatting.
421 (parameter): Delete struct typedef. Use dwordU instead
423 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
425 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
427 2020-08-29 Alan Modra <amodra@gmail.com>
430 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
431 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
433 2020-08-28 Alan Modra <amodra@gmail.com>
437 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
438 (extract_normal): Likewise.
439 (insert_normal): Likewise, and move past zero length test.
440 (put_insn_int_value): Handle mask for zero length, use 1UL.
441 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
442 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
443 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
444 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
446 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
448 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
449 (csky_dis_info): Add member isa.
450 (csky_find_inst_info): Skip instructions that do not belong to
452 (csky_get_disassembler): Get infomation from attribute section.
453 (print_insn_csky): Set defualt ISA flag.
454 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
455 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
456 isa_flag32'type to unsigned 64 bits.
458 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
460 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
462 2020-08-26 David Faust <david.faust@oracle.com>
464 * bpf-desc.c: Regenerate.
465 * bpf-desc.h: Likewise.
466 * bpf-opc.c: Likewise.
467 * bpf-opc.h: Likewise.
468 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
469 ISA when appropriate.
471 2020-08-25 Alan Modra <amodra@gmail.com>
474 * vax-dis.c (parse_disassembler_options): Always add at least one
475 to entry_addr_total_slots.
477 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
479 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
480 in other CPUs to speed up disassembling.
481 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
482 Change plsli.u16 to plsli.16, change sync's operand format.
484 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
486 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
488 2020-08-21 Nick Clifton <nickc@redhat.com>
490 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
493 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
495 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
497 2020-08-19 Alan Modra <amodra@gmail.com>
499 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
502 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
504 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
505 <xvcvbf16spn>: ...to this.
507 2020-08-12 Alex Coplan <alex.coplan@arm.com>
509 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
511 2020-08-12 Nick Clifton <nickc@redhat.com>
513 * po/sr.po: Updated Serbian translation.
515 2020-08-11 Alan Modra <amodra@gmail.com>
517 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
519 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
521 * aarch64-opc.c (aarch64_print_operand):
522 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
523 (aarch64_sys_reg_supported_p): Function removed.
524 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
525 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
528 2020-08-10 Alan Modra <amodra@gmail.com>
530 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
533 2020-08-10 Alan Modra <amodra@gmail.com>
535 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
536 Enable icbt for power5, miso for power8.
538 2020-08-10 Alan Modra <amodra@gmail.com>
540 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
541 mtvsrd, and similarly for mfvsrd.
543 2020-08-04 Christian Groessler <chris@groessler.org>
544 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
546 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
547 opcodes (special "out" to absolute address).
548 * z8k-opc.h: Regenerate.
550 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
553 * i386-opc.h (Prefix_Disp8): New.
554 (Prefix_Disp16): Likewise.
555 (Prefix_Disp32): Likewise.
556 (Prefix_Load): Likewise.
557 (Prefix_Store): Likewise.
558 (Prefix_VEX): Likewise.
559 (Prefix_VEX3): Likewise.
560 (Prefix_EVEX): Likewise.
561 (Prefix_REX): Likewise.
562 (Prefix_NoOptimize): Likewise.
563 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
564 * i386-tbl.h: Regenerated.
566 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
568 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
569 default case with abort() instead of printing an error message and
570 continuing, to avoid a maybe-uninitialized warning.
572 2020-07-24 Nick Clifton <nickc@redhat.com>
574 * po/de.po: Updated German translation.
576 2020-07-21 Jan Beulich <jbeulich@suse.com>
578 * i386-dis.c (OP_E_memory): Revert previous change.
580 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
583 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
584 without base nor index registers.
586 2020-07-15 Jan Beulich <jbeulich@suse.com>
588 * i386-dis.c (putop): Move 'V' and 'W' handling.
590 2020-07-15 Jan Beulich <jbeulich@suse.com>
592 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
593 construct for push/pop of register.
594 (putop): Honor cond when handling 'P'. Drop handling of plain
597 2020-07-15 Jan Beulich <jbeulich@suse.com>
599 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
600 description. Drop '&' description. Use P for push of immediate,
601 pushf/popf, enter, and leave. Use %LP for lret/retf.
602 (dis386_twobyte): Use P for push/pop of fs/gs.
603 (reg_table): Use P for push/pop. Use @ for near call/jmp.
604 (x86_64_table): Use P for far call/jmp.
605 (putop): Drop handling of 'U' and '&'. Move and adjust handling
606 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
608 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
609 and dqw_mode (unconditional).
611 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
614 * i386-dis.c (OP_E_memory): Without base nor index registers,
615 32-bit displacement to 64 bits.
617 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
619 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
620 faulty double register pair is detected.
622 2020-07-14 Jan Beulich <jbeulich@suse.com>
624 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
626 2020-07-14 Jan Beulich <jbeulich@suse.com>
628 * i386-dis.c (OP_R, Rm): Delete.
629 (MOD_0F24, MOD_0F26): Rename to ...
630 (X86_64_0F24, X86_64_0F26): ... respectively.
631 (dis386): Update 'L' and 'Z' comments.
632 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
634 (mod_table): Move opcode 0F24 and 0F26 entries ...
635 (x86_64_table): ... here.
636 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
639 2020-07-14 Jan Beulich <jbeulich@suse.com>
641 * i386-dis.c (Rd, Rdq, MaskR): Delete.
642 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
643 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
644 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
645 MOD_EVEX_0F387C): New enumerators.
646 (reg_table): Use Edq for rdssp.
647 (prefix_table): Use Edq for incssp.
648 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
649 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
650 ktest*, and kshift*. Use Edq / MaskE for kmov*.
651 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
652 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
653 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
654 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
655 0F3828_P_1 and 0F3838_P_1.
656 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
657 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
659 2020-07-14 Jan Beulich <jbeulich@suse.com>
661 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
662 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
663 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
664 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
665 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
666 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
667 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
668 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
669 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
670 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
671 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
672 (reg_table, prefix_table, three_byte_table, vex_table,
673 vex_len_table, mod_table, rm_table): Replace / remove respective
675 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
676 of PREFIX_DATA in used_prefixes.
678 2020-07-14 Jan Beulich <jbeulich@suse.com>
680 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
681 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
682 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
683 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
684 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
685 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
686 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
687 VEX_W_0F3A33_L_0): Delete.
688 (dis386): Adjust "BW" description.
689 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
690 0F3A31, 0F3A32, and 0F3A33.
691 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
693 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
696 2020-07-14 Jan Beulich <jbeulich@suse.com>
698 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
699 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
700 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
701 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
702 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
703 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
704 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
705 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
706 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
707 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
708 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
709 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
710 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
711 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
712 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
713 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
714 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
715 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
716 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
717 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
718 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
719 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
720 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
721 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
722 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
723 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
724 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
725 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
726 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
727 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
728 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
729 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
730 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
731 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
732 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
733 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
734 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
735 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
736 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
737 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
738 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
739 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
740 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
741 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
742 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
743 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
744 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
745 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
746 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
747 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
748 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
749 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
750 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
751 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
752 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
753 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
754 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
755 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
756 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
757 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
758 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
759 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
760 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
761 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
762 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
763 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
764 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
765 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
766 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
767 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
768 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
769 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
770 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
771 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
772 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
773 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
774 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
775 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
776 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
777 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
778 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
779 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
780 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
781 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
782 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
783 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
784 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
785 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
786 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
787 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
788 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
789 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
790 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
791 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
792 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
793 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
794 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
795 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
796 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
797 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
798 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
799 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
800 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
801 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
802 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
803 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
804 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
805 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
806 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
807 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
808 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
809 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
810 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
811 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
812 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
813 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
814 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
815 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
816 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
817 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
818 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
819 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
820 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
821 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
822 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
823 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
824 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
825 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
826 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
827 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
828 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
829 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
830 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
831 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
832 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
833 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
834 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
835 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
836 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
837 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
838 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
839 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
840 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
841 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
842 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
843 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
844 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
845 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
846 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
847 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
848 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
849 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
850 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
851 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
852 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
853 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
854 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
855 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
856 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
857 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
858 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
859 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
860 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
861 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
862 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
863 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
864 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
865 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
866 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
867 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
868 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
869 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
870 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
871 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
872 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
873 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
874 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
875 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
876 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
877 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
878 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
879 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
880 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
881 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
882 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
883 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
884 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
885 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
886 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
887 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
888 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
889 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
890 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
891 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
892 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
893 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
894 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
895 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
896 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
897 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
898 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
899 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
900 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
901 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
902 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
903 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
904 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
905 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
906 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
907 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
908 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
909 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
910 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
911 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
912 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
913 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
914 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
915 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
916 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
917 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
918 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
919 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
920 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
921 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
922 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
923 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
924 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
925 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
926 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
927 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
928 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
929 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
930 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
931 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
932 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
933 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
934 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
935 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
936 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
937 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
938 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
939 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
940 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
941 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
942 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
943 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
944 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
945 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
946 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
947 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
948 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
949 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
950 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
951 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
952 EVEX_W_0F3A72_P_2): Rename to ...
953 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
954 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
955 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
956 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
957 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
958 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
959 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
960 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
961 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
962 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
963 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
964 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
965 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
966 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
967 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
968 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
969 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
970 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
971 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
972 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
973 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
974 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
975 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
976 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
977 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
978 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
979 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
980 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
981 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
982 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
983 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
984 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
985 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
986 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
987 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
988 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
989 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
990 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
991 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
992 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
993 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
994 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
995 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
996 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
997 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
998 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
999 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1000 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1001 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1002 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1003 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1004 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1005 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1006 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1007 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1008 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1009 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1010 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1011 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1012 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1013 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1014 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1015 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1016 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1017 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1018 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1019 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1020 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1021 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1022 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1023 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1024 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1026 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1027 vex_w_table, mod_table): Replace / remove respective entries.
1028 (print_insn): Move up dp->prefix_requirement handling. Handle
1030 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1031 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1032 Replace / remove respective entries.
1034 2020-07-14 Jan Beulich <jbeulich@suse.com>
1036 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1037 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1038 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1039 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1040 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1042 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1043 0F2C, 0F2D, 0F2E, and 0F2F.
1044 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1047 2020-07-14 Jan Beulich <jbeulich@suse.com>
1049 * i386-dis.c (OP_VexR, VexScalarR): New.
1050 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1051 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1052 need_vex_reg): Delete.
1053 (prefix_table): Replace VexScalar by VexScalarR and
1054 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1055 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1056 (vex_len_table): Replace EXqVexScalarS by EXqS.
1057 (get_valid_dis386): Don't set need_vex_reg.
1058 (print_insn): Don't initialize need_vex_reg.
1059 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1060 q_scalar_swap_mode cases.
1061 (OP_EX): Don't check for d_scalar_swap_mode and
1063 (OP_VEX): Done check need_vex_reg.
1064 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1065 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1066 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1068 2020-07-14 Jan Beulich <jbeulich@suse.com>
1070 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1071 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1072 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1073 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1074 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1075 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1076 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1077 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1078 (vex_table): Replace Vex128 by Vex.
1079 (vex_len_table): Likewise. Adjust referenced enum names.
1080 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1081 referenced enum names.
1082 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1083 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1085 2020-07-14 Jan Beulich <jbeulich@suse.com>
1087 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1088 (putop): Handle "DQ". Don't handle "LW" anymore.
1089 (prefix_table, mod_table): Replace %LW by %DQ.
1090 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1092 2020-07-14 Jan Beulich <jbeulich@suse.com>
1094 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1095 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1096 d_scalar_swap_mode case handling. Move shift adjsutment into
1097 the case its applicable to.
1099 2020-07-14 Jan Beulich <jbeulich@suse.com>
1101 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1102 (EXbScalar, EXwScalar): Fold to ...
1103 (EXbwUnit): ... this.
1104 (b_scalar_mode, w_scalar_mode): Fold to ...
1105 (bw_unit_mode): ... this.
1106 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1107 w_scalar_mode handling by bw_unit_mode one.
1108 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1110 * i386-dis-evex-prefix.h: ... here.
1112 2020-07-14 Jan Beulich <jbeulich@suse.com>
1114 * i386-dis.c (PCMPESTR_Fixup): Delete.
1115 (dis386): Adjust "LQ" description.
1116 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1117 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1118 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1119 vpcmpestrm, and vpcmpestri.
1120 (putop): Honor "cond" when handling LQ.
1121 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1122 vcvtsi2ss and vcvtusi2ss.
1123 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1124 vcvtsi2sd and vcvtusi2sd.
1126 2020-07-14 Jan Beulich <jbeulich@suse.com>
1128 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1129 (simd_cmp_op): Add const.
1130 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1131 (CMP_Fixup): Handle VEX case.
1132 (prefix_table): Replace VCMP by CMP.
1133 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1135 2020-07-14 Jan Beulich <jbeulich@suse.com>
1137 * i386-dis.c (MOVBE_Fixup): Delete.
1139 (prefix_table): Use Mv for movbe entries.
1141 2020-07-14 Jan Beulich <jbeulich@suse.com>
1143 * i386-dis.c (CRC32_Fixup): Delete.
1144 (prefix_table): Use Eb/Ev for crc32 entries.
1146 2020-07-14 Jan Beulich <jbeulich@suse.com>
1148 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1149 Conditionalize invocations of "USED_REX (0)".
1151 2020-07-14 Jan Beulich <jbeulich@suse.com>
1153 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1154 CH, DH, BH, AX, DX): Delete.
1155 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1156 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1157 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1159 2020-07-10 Lili Cui <lili.cui@intel.com>
1161 * i386-dis.c (TMM): New.
1164 (MVexSIBMEM): Likewise.
1165 (tmm_mode): Likewise.
1166 (vex_sibmem_mode): Likewise.
1167 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1168 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1169 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1170 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1171 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1172 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1173 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1174 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1175 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1176 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1177 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1178 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1179 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1180 (PREFIX_VEX_0F3849_X86_64): Likewise.
1181 (PREFIX_VEX_0F384B_X86_64): Likewise.
1182 (PREFIX_VEX_0F385C_X86_64): Likewise.
1183 (PREFIX_VEX_0F385E_X86_64): Likewise.
1184 (X86_64_VEX_0F3849): Likewise.
1185 (X86_64_VEX_0F384B): Likewise.
1186 (X86_64_VEX_0F385C): Likewise.
1187 (X86_64_VEX_0F385E): Likewise.
1188 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1189 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1190 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1191 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1192 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1193 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1194 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1195 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1196 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1197 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1198 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1199 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1200 (VEX_W_0F3849_X86_64_P_0): Likewise.
1201 (VEX_W_0F3849_X86_64_P_2): Likewise.
1202 (VEX_W_0F3849_X86_64_P_3): Likewise.
1203 (VEX_W_0F384B_X86_64_P_1): Likewise.
1204 (VEX_W_0F384B_X86_64_P_2): Likewise.
1205 (VEX_W_0F384B_X86_64_P_3): Likewise.
1206 (VEX_W_0F385C_X86_64_P_1): Likewise.
1207 (VEX_W_0F385E_X86_64_P_0): Likewise.
1208 (VEX_W_0F385E_X86_64_P_1): Likewise.
1209 (VEX_W_0F385E_X86_64_P_2): Likewise.
1210 (VEX_W_0F385E_X86_64_P_3): Likewise.
1211 (names_tmm): Likewise.
1212 (att_names_tmm): Likewise.
1213 (intel_operand_size): Handle void_mode.
1214 (OP_XMM): Handle tmm_mode.
1217 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1218 CpuAMX_BF16 and CpuAMX_TILE.
1219 (operand_type_shorthands): Add RegTMM.
1220 (operand_type_init): Likewise.
1221 (operand_types): Add Tmmword.
1222 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1223 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1224 * i386-opc.h (CpuAMX_INT8): New.
1225 (CpuAMX_BF16): Likewise.
1226 (CpuAMX_TILE): Likewise.
1228 (Tmmword): Likewise.
1229 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1230 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1231 (i386_operand_type): Add tmmword.
1232 * i386-opc.tbl: Add AMX instructions.
1233 * i386-reg.tbl: Add AMX registers.
1234 * i386-init.h: Regenerated.
1235 * i386-tbl.h: Likewise.
1237 2020-07-08 Jan Beulich <jbeulich@suse.com>
1239 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1240 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1242 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1243 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1245 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1246 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1247 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1248 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1249 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1250 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1251 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1252 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1253 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1254 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1255 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1256 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1257 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1258 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1259 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1260 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1261 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1262 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1263 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1264 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1265 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1266 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1267 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1268 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1269 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1270 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1271 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1272 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1273 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1274 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1275 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1276 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1277 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1278 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1279 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1280 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1281 (reg_table): Re-order XOP entries. Adjust their operands.
1282 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1283 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1284 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1285 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1286 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1287 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1288 entries by references ...
1289 (vex_len_table): ... to resepctive new entries here. For several
1290 new and existing entries reference ...
1291 (vex_w_table): ... new entries here.
1292 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1294 2020-07-08 Jan Beulich <jbeulich@suse.com>
1296 * i386-dis.c (XMVexScalarI4): Define.
1297 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1298 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1299 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1300 (vex_len_table): Move scalar FMA4 entries ...
1301 (prefix_table): ... here.
1302 (OP_REG_VexI4): Handle scalar_mode.
1303 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1304 * i386-tbl.h: Re-generate.
1306 2020-07-08 Jan Beulich <jbeulich@suse.com>
1308 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1309 Vex_2src_2): Delete.
1310 (OP_VexW, VexW): New.
1311 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1312 for shifts and rotates by register.
1314 2020-07-08 Jan Beulich <jbeulich@suse.com>
1316 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1317 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1318 OP_EX_VexReg): Delete.
1319 (OP_VexI4, VexI4): New.
1320 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1321 (prefix_table): ... here.
1322 (print_insn): Drop setting of vex_w_done.
1324 2020-07-08 Jan Beulich <jbeulich@suse.com>
1326 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1327 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1328 (xop_table): Replace operands of 4-operand insns.
1329 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1331 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1333 * arc-opc.c (insert_rbd): New function.
1336 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1339 2020-07-07 Jan Beulich <jbeulich@suse.com>
1341 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1342 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1343 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1344 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1346 (putop): Handle "BW".
1347 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1348 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1350 * i386-dis-evex-prefix.h: ... here.
1352 2020-07-06 Jan Beulich <jbeulich@suse.com>
1354 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1355 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1356 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1357 VEX_W_0FXOP_09_83): New enumerators.
1358 (xop_table): Reference the above.
1359 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1360 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1361 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1362 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1364 2020-07-06 Jan Beulich <jbeulich@suse.com>
1366 * i386-dis.c (EVEX_W_0F3838_P_1,
1367 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1368 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1369 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1370 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1371 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1372 (putop): Centralize management of last[]. Delete SAVE_LAST.
1373 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1374 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1375 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1376 * i386-dis-evex-prefix.h: here.
1378 2020-07-06 Jan Beulich <jbeulich@suse.com>
1380 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1381 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1382 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1383 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1385 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1386 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1387 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1388 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1389 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1390 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1391 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1392 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1393 these, respectively.
1394 * i386-dis-evex-len.h: Adjust comments.
1395 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1396 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1397 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1398 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1399 MOD_EVEX_0F385B_P_2_W_1 table entries.
1400 * i386-dis-evex-w.h: Reference mod_table[] for
1401 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1404 2020-07-06 Jan Beulich <jbeulich@suse.com>
1406 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1407 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1409 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1410 Likewise. Mark 256-bit entries invalid.
1412 2020-07-06 Jan Beulich <jbeulich@suse.com>
1414 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1415 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1416 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1417 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1418 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1419 PREFIX_EVEX_0F382B): Delete.
1420 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1421 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1422 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1423 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1424 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1426 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1427 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1428 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1429 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1431 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1432 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1433 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1434 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1435 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1436 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1437 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1438 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1439 PREFIX_EVEX_0F382B): Remove table entries.
1440 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1441 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1442 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1444 2020-07-06 Jan Beulich <jbeulich@suse.com>
1446 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1447 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1449 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1450 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1451 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1452 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1455 2020-07-06 Jan Beulich <jbeulich@suse.com>
1457 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1458 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1459 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1460 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1461 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1462 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1463 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1464 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1465 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1468 2020-07-06 Jan Beulich <jbeulich@suse.com>
1470 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1471 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1472 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1474 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1476 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1478 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1480 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1482 2020-07-06 Jan Beulich <jbeulich@suse.com>
1484 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1485 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1486 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1487 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1488 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1489 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1490 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1491 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1492 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1493 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1494 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1495 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1496 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1497 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1498 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1499 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1500 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1501 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1502 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1503 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1504 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1505 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1506 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1507 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1508 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1509 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1510 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1511 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1512 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1513 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1514 (prefix_table): Add EXxEVexR to FMA table entries.
1515 (OP_Rounding): Move abort() invocation.
1516 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1517 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1518 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1519 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1520 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1521 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1522 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1523 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1524 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1525 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1527 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1528 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1529 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1530 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1531 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1532 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1533 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1534 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1535 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1536 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1537 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1538 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1539 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1540 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1541 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1542 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1543 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1544 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1545 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1546 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1547 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1548 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1549 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1550 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1551 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1552 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1553 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1554 Delete table entries.
1555 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1556 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1557 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1560 2020-07-06 Jan Beulich <jbeulich@suse.com>
1562 * i386-dis.c (EXqScalarS): Delete.
1563 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1564 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1566 2020-07-06 Jan Beulich <jbeulich@suse.com>
1568 * i386-dis.c (safe-ctype.h): Include.
1569 (EXdScalar, EXqScalar): Delete.
1570 (d_scalar_mode, q_scalar_mode): Delete.
1571 (prefix_table, vex_len_table): Use EXxmm_md in place of
1572 EXdScalar and EXxmm_mq in place of EXqScalar.
1573 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1574 d_scalar_mode and q_scalar_mode.
1575 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1576 (vmovsd): Use EXxmm_mq.
1578 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1581 * arc-dis.c: Fix spelling mistake.
1582 * po/opcodes.pot: Regenerate.
1584 2020-07-06 Nick Clifton <nickc@redhat.com>
1586 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1587 * po/uk.po: Updated Ukranian translation.
1589 2020-07-04 Nick Clifton <nickc@redhat.com>
1591 * configure: Regenerate.
1592 * po/opcodes.pot: Regenerate.
1594 2020-07-04 Nick Clifton <nickc@redhat.com>
1596 Binutils 2.35 branch created.
1598 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1600 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1601 * i386-opc.h (VexSwapSources): New.
1602 (i386_opcode_modifier): Add vexswapsources.
1603 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1604 with two source operands swapped.
1605 * i386-tbl.h: Regenerated.
1607 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1609 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1610 unprivileged CSR can also be initialized.
1612 2020-06-29 Alan Modra <amodra@gmail.com>
1614 * arm-dis.c: Use C style comments.
1615 * cr16-opc.c: Likewise.
1616 * ft32-dis.c: Likewise.
1617 * moxie-opc.c: Likewise.
1618 * tic54x-dis.c: Likewise.
1619 * s12z-opc.c: Remove useless comment.
1620 * xgate-dis.c: Likewise.
1622 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1624 * i386-opc.tbl: Add a blank line.
1626 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1628 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1629 (VecSIB128): Renamed to ...
1631 (VecSIB256): Renamed to ...
1633 (VecSIB512): Renamed to ...
1635 (VecSIB): Renamed to ...
1637 (i386_opcode_modifier): Replace vecsib with sib.
1638 * i386-opc.tbl (VecSIB128): New.
1639 (VecSIB256): Likewise.
1640 (VecSIB512): Likewise.
1641 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1642 and VecSIB512, respectively.
1644 2020-06-26 Jan Beulich <jbeulich@suse.com>
1646 * i386-dis.c: Adjust description of I macro.
1647 (x86_64_table): Drop use of I.
1648 (float_mem): Replace use of I.
1649 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1651 2020-06-26 Jan Beulich <jbeulich@suse.com>
1653 * i386-dis.c: (print_insn): Avoid straight assignment to
1654 priv.orig_sizeflag when processing -M sub-options.
1656 2020-06-25 Jan Beulich <jbeulich@suse.com>
1658 * i386-dis.c: Adjust description of J macro.
1659 (dis386, x86_64_table, mod_table): Replace J.
1660 (putop): Remove handling of J.
1662 2020-06-25 Jan Beulich <jbeulich@suse.com>
1664 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1666 2020-06-25 Jan Beulich <jbeulich@suse.com>
1668 * i386-dis.c: Adjust description of "LQ" macro.
1669 (dis386_twobyte): Use LQ for sysret.
1670 (putop): Adjust handling of LQ.
1672 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1674 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1675 * riscv-dis.c: Include elfxx-riscv.h.
1677 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1679 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1681 2020-06-17 Lili Cui <lili.cui@intel.com>
1683 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1685 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1688 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1689 * i386-opc.tbl: Likewise.
1690 * i386-tbl.h: Regenerated.
1692 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1694 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1696 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1698 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1699 (SR_CORE): Likewise.
1700 (SR_FEAT): Likewise.
1702 (SR_V8_1): Likewise.
1703 (SR_V8_2): Likewise.
1704 (SR_V8_3): Likewise.
1705 (SR_V8_4): Likewise.
1708 (SR_SSBS): Likewise.
1710 (SR_ID_PFR2): Likewise.
1711 (SR_PROFILE): Likewise.
1712 (SR_MEMTAG): Likewise.
1713 (SR_SCXTNUM): Likewise.
1714 (aarch64_sys_regs): Refactor to store feature information in the table.
1715 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1716 that now describe their own features.
1717 (aarch64_pstatefield_supported_p): Likewise.
1719 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1721 * i386-dis.c (prefix_table): Fix a typo in comments.
1723 2020-06-09 Jan Beulich <jbeulich@suse.com>
1725 * i386-dis.c (rex_ignored): Delete.
1726 (ckprefix): Drop rex_ignored initialization.
1727 (get_valid_dis386): Drop setting of rex_ignored.
1728 (print_insn): Drop checking of rex_ignored. Don't record data
1729 size prefix as used with VEX-and-alike encodings.
1731 2020-06-09 Jan Beulich <jbeulich@suse.com>
1733 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1734 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1735 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1736 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1737 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1738 VEX_0F12, and VEX_0F16.
1739 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1740 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1741 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1742 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1743 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1744 MOD_VEX_0F16_PREFIX_2 entries.
1746 2020-06-09 Jan Beulich <jbeulich@suse.com>
1748 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1749 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1750 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1751 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1752 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1753 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1754 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1755 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1756 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1757 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1758 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1759 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1760 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1761 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1762 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1763 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1764 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1765 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1766 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1767 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1768 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1769 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1770 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1771 EVEX_W_0FC6_P_2): Delete.
1772 (print_insn): Add EVEX.W vs embedded prefix consistency check
1773 to prefix validation.
1774 * i386-dis-evex.h (evex_table): Don't further descend for
1775 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1776 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1778 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1779 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1780 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1781 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1782 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1783 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1784 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1785 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1786 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1787 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1788 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1789 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1790 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1791 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1792 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1793 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1794 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1795 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1796 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1797 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1798 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1799 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1800 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1801 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1802 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1803 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1804 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1806 2020-06-09 Jan Beulich <jbeulich@suse.com>
1808 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1809 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1810 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1812 (print_insn): Drop pointless check against bad_opcode. Split
1813 prefix validation into legacy and VEX-and-alike parts.
1814 (putop): Re-work 'X' macro handling.
1816 2020-06-09 Jan Beulich <jbeulich@suse.com>
1818 * i386-dis.c (MOD_0F51): Rename to ...
1819 (MOD_0F50): ... this.
1821 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1823 * arm-dis.c (arm_opcodes): Add dfb.
1824 (thumb32_opcodes): Add dfb.
1826 2020-06-08 Jan Beulich <jbeulich@suse.com>
1828 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1830 2020-06-06 Alan Modra <amodra@gmail.com>
1832 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1834 2020-06-05 Alan Modra <amodra@gmail.com>
1836 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1837 size is large enough.
1839 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1841 * disassemble.c (disassemble_init_for_target): Set endian_code for
1843 * bpf-desc.c: Regenerate.
1844 * bpf-opc.c: Likewise.
1845 * bpf-dis.c: Likewise.
1847 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1849 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1850 (cgen_put_insn_value): Likewise.
1851 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1852 * cgen-dis.in (print_insn): Likewise.
1853 * cgen-ibld.in (insert_1): Likewise.
1854 (insert_1): Likewise.
1855 (insert_insn_normal): Likewise.
1856 (extract_1): Likewise.
1857 * bpf-dis.c: Regenerate.
1858 * bpf-ibld.c: Likewise.
1859 * bpf-ibld.c: Likewise.
1860 * cgen-dis.in: Likewise.
1861 * cgen-ibld.in: Likewise.
1862 * cgen-opc.c: Likewise.
1863 * epiphany-dis.c: Likewise.
1864 * epiphany-ibld.c: Likewise.
1865 * fr30-dis.c: Likewise.
1866 * fr30-ibld.c: Likewise.
1867 * frv-dis.c: Likewise.
1868 * frv-ibld.c: Likewise.
1869 * ip2k-dis.c: Likewise.
1870 * ip2k-ibld.c: Likewise.
1871 * iq2000-dis.c: Likewise.
1872 * iq2000-ibld.c: Likewise.
1873 * lm32-dis.c: Likewise.
1874 * lm32-ibld.c: Likewise.
1875 * m32c-dis.c: Likewise.
1876 * m32c-ibld.c: Likewise.
1877 * m32r-dis.c: Likewise.
1878 * m32r-ibld.c: Likewise.
1879 * mep-dis.c: Likewise.
1880 * mep-ibld.c: Likewise.
1881 * mt-dis.c: Likewise.
1882 * mt-ibld.c: Likewise.
1883 * or1k-dis.c: Likewise.
1884 * or1k-ibld.c: Likewise.
1885 * xc16x-dis.c: Likewise.
1886 * xc16x-ibld.c: Likewise.
1887 * xstormy16-dis.c: Likewise.
1888 * xstormy16-ibld.c: Likewise.
1890 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1892 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1893 (print_insn_): Handle instruction endian.
1894 * bpf-dis.c: Regenerate.
1895 * bpf-desc.c: Regenerate.
1896 * epiphany-dis.c: Likewise.
1897 * epiphany-desc.c: Likewise.
1898 * fr30-dis.c: Likewise.
1899 * fr30-desc.c: Likewise.
1900 * frv-dis.c: Likewise.
1901 * frv-desc.c: Likewise.
1902 * ip2k-dis.c: Likewise.
1903 * ip2k-desc.c: Likewise.
1904 * iq2000-dis.c: Likewise.
1905 * iq2000-desc.c: Likewise.
1906 * lm32-dis.c: Likewise.
1907 * lm32-desc.c: Likewise.
1908 * m32c-dis.c: Likewise.
1909 * m32c-desc.c: Likewise.
1910 * m32r-dis.c: Likewise.
1911 * m32r-desc.c: Likewise.
1912 * mep-dis.c: Likewise.
1913 * mep-desc.c: Likewise.
1914 * mt-dis.c: Likewise.
1915 * mt-desc.c: Likewise.
1916 * or1k-dis.c: Likewise.
1917 * or1k-desc.c: Likewise.
1918 * xc16x-dis.c: Likewise.
1919 * xc16x-desc.c: Likewise.
1920 * xstormy16-dis.c: Likewise.
1921 * xstormy16-desc.c: Likewise.
1923 2020-06-03 Nick Clifton <nickc@redhat.com>
1925 * po/sr.po: Updated Serbian translation.
1927 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1929 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1930 (riscv_get_priv_spec_class): Likewise.
1932 2020-06-01 Alan Modra <amodra@gmail.com>
1934 * bpf-desc.c: Regenerate.
1936 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1937 David Faust <david.faust@oracle.com>
1939 * bpf-desc.c: Regenerate.
1940 * bpf-opc.h: Likewise.
1941 * bpf-opc.c: Likewise.
1942 * bpf-dis.c: Likewise.
1944 2020-05-28 Alan Modra <amodra@gmail.com>
1946 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1949 2020-05-28 Alan Modra <amodra@gmail.com>
1951 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1953 (print_insn_ns32k): Revert last change.
1955 2020-05-28 Nick Clifton <nickc@redhat.com>
1957 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1960 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1962 Fix extraction of signed constants in nios2 disassembler (again).
1964 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1965 extractions of signed fields.
1967 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1969 * s390-opc.txt: Relocate vector load/store instructions with
1970 additional alignment parameter and change architecture level
1971 constraint from z14 to z13.
1973 2020-05-21 Alan Modra <amodra@gmail.com>
1975 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1976 * sparc-dis.c: Likewise.
1977 * tic4x-dis.c: Likewise.
1978 * xtensa-dis.c: Likewise.
1979 * bpf-desc.c: Regenerate.
1980 * epiphany-desc.c: Regenerate.
1981 * fr30-desc.c: Regenerate.
1982 * frv-desc.c: Regenerate.
1983 * ip2k-desc.c: Regenerate.
1984 * iq2000-desc.c: Regenerate.
1985 * lm32-desc.c: Regenerate.
1986 * m32c-desc.c: Regenerate.
1987 * m32r-desc.c: Regenerate.
1988 * mep-asm.c: Regenerate.
1989 * mep-desc.c: Regenerate.
1990 * mt-desc.c: Regenerate.
1991 * or1k-desc.c: Regenerate.
1992 * xc16x-desc.c: Regenerate.
1993 * xstormy16-desc.c: Regenerate.
1995 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1997 * riscv-opc.c (riscv_ext_version_table): The table used to store
1998 all information about the supported spec and the corresponding ISA
1999 versions. Currently, only Zicsr is supported to verify the
2000 correctness of Z sub extension settings. Others will be supported
2001 in the future patches.
2002 (struct isa_spec_t, isa_specs): List for all supported ISA spec
2003 classes and the corresponding strings.
2004 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
2005 spec class by giving a ISA spec string.
2006 * riscv-opc.c (struct priv_spec_t): New structure.
2007 (struct priv_spec_t priv_specs): List for all supported privilege spec
2008 classes and the corresponding strings.
2009 (riscv_get_priv_spec_class): New function. Get the corresponding
2010 privilege spec class by giving a spec string.
2011 (riscv_get_priv_spec_name): New function. Get the corresponding
2012 privilege spec string by giving a CSR version class.
2013 * riscv-dis.c: Updated since DECLARE_CSR is changed.
2014 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2015 according to the chosen version. Build a hash table riscv_csr_hash to
2016 store the valid CSR for the chosen pirv verison. Dump the direct
2017 CSR address rather than it's name if it is invalid.
2018 (parse_riscv_dis_option_without_args): New function. Parse the options
2020 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2021 parse the options without arguments first, and then handle the options
2022 with arguments. Add the new option -Mpriv-spec, which has argument.
2023 * riscv-dis.c (print_riscv_disassembler_options): Add description
2024 about the new OBJDUMP option.
2026 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
2028 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2029 WC values on POWER10 sync, dcbf and wait instructions.
2030 (insert_pl, extract_pl): New functions.
2031 (L2OPT, LS, WC): Use insert_ls and extract_ls.
2032 (LS3): New , 3-bit L for sync.
2033 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2034 (SC2, PL): New, 2-bit SC and PL for sync and wait.
2035 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2036 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2037 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2038 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2039 <wait>: Enable PL operand on POWER10.
2040 <dcbf>: Enable L3OPT operand on POWER10.
2041 <sync>: Enable SC2 operand on POWER10.
2043 2020-05-19 Stafford Horne <shorne@gmail.com>
2046 * or1k-asm.c: Regenerate.
2047 * or1k-desc.c: Regenerate.
2048 * or1k-desc.h: Regenerate.
2049 * or1k-dis.c: Regenerate.
2050 * or1k-ibld.c: Regenerate.
2051 * or1k-opc.c: Regenerate.
2052 * or1k-opc.h: Regenerate.
2053 * or1k-opinst.c: Regenerate.
2055 2020-05-11 Alan Modra <amodra@gmail.com>
2057 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2060 2020-05-11 Alan Modra <amodra@gmail.com>
2062 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2063 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2065 2020-05-11 Alan Modra <amodra@gmail.com>
2067 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2069 2020-05-11 Alan Modra <amodra@gmail.com>
2071 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2072 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2074 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2076 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2079 2020-05-11 Alan Modra <amodra@gmail.com>
2081 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2082 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2083 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2084 (prefix_opcodes): Add xxeval.
2086 2020-05-11 Alan Modra <amodra@gmail.com>
2088 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2089 xxgenpcvwm, xxgenpcvdm.
2091 2020-05-11 Alan Modra <amodra@gmail.com>
2093 * ppc-opc.c (MP, VXVAM_MASK): Define.
2094 (VXVAPS_MASK): Use VXVA_MASK.
2095 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2096 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2097 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2098 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2100 2020-05-11 Alan Modra <amodra@gmail.com>
2101 Peter Bergner <bergner@linux.ibm.com>
2103 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2105 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2106 YMSK2, XA6a, XA6ap, XB6a entries.
2107 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2108 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2110 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2111 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2112 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2113 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2114 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2115 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2116 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2117 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2118 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2119 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2120 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2121 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2122 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2123 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2125 2020-05-11 Alan Modra <amodra@gmail.com>
2127 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2128 (insert_xts, extract_xts): New functions.
2129 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2130 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2131 (VXRC_MASK, VXSH_MASK): Define.
2132 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2133 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2134 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2135 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2136 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2137 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2138 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2140 2020-05-11 Alan Modra <amodra@gmail.com>
2142 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2143 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2144 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2145 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2146 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2148 2020-05-11 Alan Modra <amodra@gmail.com>
2150 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2151 (XTP, DQXP, DQXP_MASK): Define.
2152 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2153 (prefix_opcodes): Add plxvp and pstxvp.
2155 2020-05-11 Alan Modra <amodra@gmail.com>
2157 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2158 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2159 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2161 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2163 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2165 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2167 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2169 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2171 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2173 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2175 2020-05-11 Alan Modra <amodra@gmail.com>
2177 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2179 2020-05-11 Alan Modra <amodra@gmail.com>
2181 * ppc-dis.c (ppc_opts): Add "power10" entry.
2182 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2183 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2185 2020-05-11 Nick Clifton <nickc@redhat.com>
2187 * po/fr.po: Updated French translation.
2189 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2191 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2192 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2193 (operand_general_constraint_met_p): validate
2194 AARCH64_OPND_UNDEFINED.
2195 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2197 * aarch64-asm-2.c: Regenerated.
2198 * aarch64-dis-2.c: Regenerated.
2199 * aarch64-opc-2.c: Regenerated.
2201 2020-04-29 Nick Clifton <nickc@redhat.com>
2204 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2207 2020-04-29 Nick Clifton <nickc@redhat.com>
2209 * po/sv.po: Updated Swedish translation.
2211 2020-04-29 Nick Clifton <nickc@redhat.com>
2214 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2215 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2216 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2219 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2222 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2223 cmpi only on m68020up and cpu32.
2225 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2227 * aarch64-asm.c (aarch64_ins_none): New.
2228 * aarch64-asm.h (ins_none): New declaration.
2229 * aarch64-dis.c (aarch64_ext_none): New.
2230 * aarch64-dis.h (ext_none): New declaration.
2231 * aarch64-opc.c (aarch64_print_operand): Update case for
2232 AARCH64_OPND_BARRIER_PSB.
2233 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2234 (AARCH64_OPERANDS): Update inserter/extracter for
2235 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2236 * aarch64-asm-2.c: Regenerated.
2237 * aarch64-dis-2.c: Regenerated.
2238 * aarch64-opc-2.c: Regenerated.
2240 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2242 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2243 (aarch64_feature_ras, RAS): Likewise.
2244 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2245 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2246 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2247 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2248 * aarch64-asm-2.c: Regenerated.
2249 * aarch64-dis-2.c: Regenerated.
2250 * aarch64-opc-2.c: Regenerated.
2252 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2254 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2255 (print_insn_neon): Support disassembly of conditional
2258 2020-02-16 David Faust <david.faust@oracle.com>
2260 * bpf-desc.c: Regenerate.
2261 * bpf-desc.h: Likewise.
2262 * bpf-opc.c: Regenerate.
2263 * bpf-opc.h: Likewise.
2265 2020-04-07 Lili Cui <lili.cui@intel.com>
2267 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2268 (prefix_table): New instructions (see prefixes above).
2269 (rm_table): Likewise
2270 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2271 CPU_ANY_TSXLDTRK_FLAGS.
2272 (cpu_flags): Add CpuTSXLDTRK.
2273 * i386-opc.h (enum): Add CpuTSXLDTRK.
2274 (i386_cpu_flags): Add cputsxldtrk.
2275 * i386-opc.tbl: Add XSUSPLDTRK insns.
2276 * i386-init.h: Regenerate.
2277 * i386-tbl.h: Likewise.
2279 2020-04-02 Lili Cui <lili.cui@intel.com>
2281 * i386-dis.c (prefix_table): New instructions serialize.
2282 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2283 CPU_ANY_SERIALIZE_FLAGS.
2284 (cpu_flags): Add CpuSERIALIZE.
2285 * i386-opc.h (enum): Add CpuSERIALIZE.
2286 (i386_cpu_flags): Add cpuserialize.
2287 * i386-opc.tbl: Add SERIALIZE insns.
2288 * i386-init.h: Regenerate.
2289 * i386-tbl.h: Likewise.
2291 2020-03-26 Alan Modra <amodra@gmail.com>
2293 * disassemble.h (opcodes_assert): Declare.
2294 (OPCODES_ASSERT): Define.
2295 * disassemble.c: Don't include assert.h. Include opintl.h.
2296 (opcodes_assert): New function.
2297 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2298 (bfd_h8_disassemble): Reduce size of data array. Correctly
2299 calculate maxlen. Omit insn decoding when insn length exceeds
2300 maxlen. Exit from nibble loop when looking for E, before
2301 accessing next data byte. Move processing of E outside loop.
2302 Replace tests of maxlen in loop with assertions.
2304 2020-03-26 Alan Modra <amodra@gmail.com>
2306 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2308 2020-03-25 Alan Modra <amodra@gmail.com>
2310 * z80-dis.c (suffix): Init mybuf.
2312 2020-03-22 Alan Modra <amodra@gmail.com>
2314 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2315 successflly read from section.
2317 2020-03-22 Alan Modra <amodra@gmail.com>
2319 * arc-dis.c (find_format): Use ISO C string concatenation rather
2320 than line continuation within a string. Don't access needs_limm
2321 before testing opcode != NULL.
2323 2020-03-22 Alan Modra <amodra@gmail.com>
2325 * ns32k-dis.c (print_insn_arg): Update comment.
2326 (print_insn_ns32k): Reduce size of index_offset array, and
2327 initialize, passing -1 to print_insn_arg for args that are not
2328 an index. Don't exit arg loop early. Abort on bad arg number.
2330 2020-03-22 Alan Modra <amodra@gmail.com>
2332 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2333 * s12z-opc.c: Formatting.
2334 (operands_f): Return an int.
2335 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2336 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2337 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2338 (exg_sex_discrim): Likewise.
2339 (create_immediate_operand, create_bitfield_operand),
2340 (create_register_operand_with_size, create_register_all_operand),
2341 (create_register_all16_operand, create_simple_memory_operand),
2342 (create_memory_operand, create_memory_auto_operand): Don't
2343 segfault on malloc failure.
2344 (z_ext24_decode): Return an int status, negative on fail, zero
2346 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2347 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2348 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2349 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2350 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2351 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2352 (loop_primitive_decode, shift_decode, psh_pul_decode),
2353 (bit_field_decode): Similarly.
2354 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2355 to return value, update callers.
2356 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2357 Don't segfault on NULL operand.
2358 (decode_operation): Return OP_INVALID on first fail.
2359 (decode_s12z): Check all reads, returning -1 on fail.
2361 2020-03-20 Alan Modra <amodra@gmail.com>
2363 * metag-dis.c (print_insn_metag): Don't ignore status from
2366 2020-03-20 Alan Modra <amodra@gmail.com>
2368 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2369 Initialize parts of buffer not written when handling a possible
2370 2-byte insn at end of section. Don't attempt decoding of such
2371 an insn by the 4-byte machinery.
2373 2020-03-20 Alan Modra <amodra@gmail.com>
2375 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2376 partially filled buffer. Prevent lookup of 4-byte insns when
2377 only VLE 2-byte insns are possible due to section size. Print
2378 ".word" rather than ".long" for 2-byte leftovers.
2380 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2383 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2385 2020-03-13 Jan Beulich <jbeulich@suse.com>
2387 * i386-dis.c (X86_64_0D): Rename to ...
2388 (X86_64_0E): ... this.
2390 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2392 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2393 * Makefile.in: Regenerated.
2395 2020-03-09 Jan Beulich <jbeulich@suse.com>
2397 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2399 * i386-tbl.h: Re-generate.
2401 2020-03-09 Jan Beulich <jbeulich@suse.com>
2403 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2404 vprot*, vpsha*, and vpshl*.
2405 * i386-tbl.h: Re-generate.
2407 2020-03-09 Jan Beulich <jbeulich@suse.com>
2409 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2410 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2411 * i386-tbl.h: Re-generate.
2413 2020-03-09 Jan Beulich <jbeulich@suse.com>
2415 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2416 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2417 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2418 * i386-tbl.h: Re-generate.
2420 2020-03-09 Jan Beulich <jbeulich@suse.com>
2422 * i386-gen.c (struct template_arg, struct template_instance,
2423 struct template_param, struct template, templates,
2424 parse_template, expand_templates): New.
2425 (process_i386_opcodes): Various local variables moved to
2426 expand_templates. Call parse_template and expand_templates.
2427 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2428 * i386-tbl.h: Re-generate.
2430 2020-03-06 Jan Beulich <jbeulich@suse.com>
2432 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2433 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2434 register and memory source templates. Replace VexW= by VexW*
2436 * i386-tbl.h: Re-generate.
2438 2020-03-06 Jan Beulich <jbeulich@suse.com>
2440 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2441 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2442 * i386-tbl.h: Re-generate.
2444 2020-03-06 Jan Beulich <jbeulich@suse.com>
2446 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2447 * i386-tbl.h: Re-generate.
2449 2020-03-06 Jan Beulich <jbeulich@suse.com>
2451 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2452 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2453 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2454 VexW0 on SSE2AVX variants.
2455 (vmovq): Drop NoRex64 from XMM/XMM variants.
2456 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2457 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2458 applicable use VexW0.
2459 * i386-tbl.h: Re-generate.
2461 2020-03-06 Jan Beulich <jbeulich@suse.com>
2463 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2464 * i386-opc.h (Rex64): Delete.
2465 (struct i386_opcode_modifier): Remove rex64 field.
2466 * i386-opc.tbl (crc32): Drop Rex64.
2467 Replace Rex64 with Size64 everywhere else.
2468 * i386-tbl.h: Re-generate.
2470 2020-03-06 Jan Beulich <jbeulich@suse.com>
2472 * i386-dis.c (OP_E_memory): Exclude recording of used address
2473 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2474 addressed memory operands for MPX insns.
2476 2020-03-06 Jan Beulich <jbeulich@suse.com>
2478 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2479 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2480 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2481 (ptwrite): Split into non-64-bit and 64-bit forms.
2482 * i386-tbl.h: Re-generate.
2484 2020-03-06 Jan Beulich <jbeulich@suse.com>
2486 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2488 * i386-tbl.h: Re-generate.
2490 2020-03-04 Jan Beulich <jbeulich@suse.com>
2492 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2493 (prefix_table): Move vmmcall here. Add vmgexit.
2494 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2495 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2496 (cpu_flags): Add CpuSEV_ES entry.
2497 * i386-opc.h (CpuSEV_ES): New.
2498 (union i386_cpu_flags): Add cpusev_es field.
2499 * i386-opc.tbl (vmgexit): New.
2500 * i386-init.h, i386-tbl.h: Re-generate.
2502 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2504 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2506 * i386-opc.h (IGNORESIZE): New.
2507 (DEFAULTSIZE): Likewise.
2508 (IgnoreSize): Removed.
2509 (DefaultSize): Likewise.
2510 (MnemonicSize): New.
2511 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2513 * i386-opc.tbl (IgnoreSize): New.
2514 (DefaultSize): Likewise.
2515 * i386-tbl.h: Regenerated.
2517 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2520 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2523 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2526 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2527 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2528 * i386-tbl.h: Regenerated.
2530 2020-02-26 Alan Modra <amodra@gmail.com>
2532 * aarch64-asm.c: Indent labels correctly.
2533 * aarch64-dis.c: Likewise.
2534 * aarch64-gen.c: Likewise.
2535 * aarch64-opc.c: Likewise.
2536 * alpha-dis.c: Likewise.
2537 * i386-dis.c: Likewise.
2538 * nds32-asm.c: Likewise.
2539 * nfp-dis.c: Likewise.
2540 * visium-dis.c: Likewise.
2542 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2544 * arc-regs.h (int_vector_base): Make it available for all ARC
2547 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2549 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2552 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2554 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2555 c.mv/c.li if rs1 is zero.
2557 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2559 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2560 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2562 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2563 * i386-opc.h (CpuABM): Removed.
2565 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2566 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2567 popcnt. Remove CpuABM from lzcnt.
2568 * i386-init.h: Regenerated.
2569 * i386-tbl.h: Likewise.
2571 2020-02-17 Jan Beulich <jbeulich@suse.com>
2573 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2574 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2575 VexW1 instead of open-coding them.
2576 * i386-tbl.h: Re-generate.
2578 2020-02-17 Jan Beulich <jbeulich@suse.com>
2580 * i386-opc.tbl (AddrPrefixOpReg): Define.
2581 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2582 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2583 templates. Drop NoRex64.
2584 * i386-tbl.h: Re-generate.
2586 2020-02-17 Jan Beulich <jbeulich@suse.com>
2589 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2590 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2591 into Intel syntax instance (with Unpsecified) and AT&T one
2593 (vcvtneps2bf16): Likewise, along with folding the two so far
2595 * i386-tbl.h: Re-generate.
2597 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2599 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2600 CPU_ANY_SSE4A_FLAGS.
2602 2020-02-17 Alan Modra <amodra@gmail.com>
2604 * i386-gen.c (cpu_flag_init): Correct last change.
2606 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2608 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2611 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2613 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2616 2020-02-14 Jan Beulich <jbeulich@suse.com>
2619 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2620 destination for Cpu64-only variant.
2621 (movzx): Fold patterns.
2622 * i386-tbl.h: Re-generate.
2624 2020-02-13 Jan Beulich <jbeulich@suse.com>
2626 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2627 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2628 CPU_ANY_SSE4_FLAGS entry.
2629 * i386-init.h: Re-generate.
2631 2020-02-12 Jan Beulich <jbeulich@suse.com>
2633 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2634 with Unspecified, making the present one AT&T syntax only.
2635 * i386-tbl.h: Re-generate.
2637 2020-02-12 Jan Beulich <jbeulich@suse.com>
2639 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2640 * i386-tbl.h: Re-generate.
2642 2020-02-12 Jan Beulich <jbeulich@suse.com>
2645 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2646 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2647 Amd64 and Intel64 templates.
2648 (call, jmp): Likewise for far indirect variants. Dro
2650 * i386-tbl.h: Re-generate.
2652 2020-02-11 Jan Beulich <jbeulich@suse.com>
2654 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2655 * i386-opc.h (ShortForm): Delete.
2656 (struct i386_opcode_modifier): Remove shortform field.
2657 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2658 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2659 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2660 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2662 * i386-tbl.h: Re-generate.
2664 2020-02-11 Jan Beulich <jbeulich@suse.com>
2666 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2667 fucompi): Drop ShortForm from operand-less templates.
2668 * i386-tbl.h: Re-generate.
2670 2020-02-11 Alan Modra <amodra@gmail.com>
2672 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2673 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2674 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2675 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2676 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2678 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2680 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2681 (cde_opcodes): Add VCX* instructions.
2683 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2684 Matthew Malcomson <matthew.malcomson@arm.com>
2686 * arm-dis.c (struct cdeopcode32): New.
2687 (CDE_OPCODE): New macro.
2688 (cde_opcodes): New disassembly table.
2689 (regnames): New option to table.
2690 (cde_coprocs): New global variable.
2691 (print_insn_cde): New
2692 (print_insn_thumb32): Use print_insn_cde.
2693 (parse_arm_disassembler_options): Parse coprocN args.
2695 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2698 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2700 * i386-opc.h (AMD64): Removed.
2701 (Intel64): Likewose.
2703 (INTEL64): Likewise.
2704 (INTEL64ONLY): Likewise.
2705 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2706 * i386-opc.tbl (Amd64): New.
2707 (Intel64): Likewise.
2708 (Intel64Only): Likewise.
2709 Replace AMD64 with Amd64. Update sysenter/sysenter with
2710 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2711 * i386-tbl.h: Regenerated.
2713 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2716 * z80-dis.c: Add support for GBZ80 opcodes.
2718 2020-02-04 Alan Modra <amodra@gmail.com>
2720 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2722 2020-02-03 Alan Modra <amodra@gmail.com>
2724 * m32c-ibld.c: Regenerate.
2726 2020-02-01 Alan Modra <amodra@gmail.com>
2728 * frv-ibld.c: Regenerate.
2730 2020-01-31 Jan Beulich <jbeulich@suse.com>
2732 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2733 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2734 (OP_E_memory): Replace xmm_mdq_mode case label by
2735 vex_scalar_w_dq_mode one.
2736 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2738 2020-01-31 Jan Beulich <jbeulich@suse.com>
2740 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2741 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2742 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2743 (intel_operand_size): Drop vex_w_dq_mode case label.
2745 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2747 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2748 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2750 2020-01-30 Alan Modra <amodra@gmail.com>
2752 * m32c-ibld.c: Regenerate.
2754 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2756 * bpf-opc.c: Regenerate.
2758 2020-01-30 Jan Beulich <jbeulich@suse.com>
2760 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2761 (dis386): Use them to replace C2/C3 table entries.
2762 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2763 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2764 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2765 * i386-tbl.h: Re-generate.
2767 2020-01-30 Jan Beulich <jbeulich@suse.com>
2769 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2771 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2773 * i386-tbl.h: Re-generate.
2775 2020-01-30 Alan Modra <amodra@gmail.com>
2777 * tic4x-dis.c (tic4x_dp): Make unsigned.
2779 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2780 Jan Beulich <jbeulich@suse.com>
2783 * i386-dis.c (MOVSXD_Fixup): New function.
2784 (movsxd_mode): New enum.
2785 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2786 (intel_operand_size): Handle movsxd_mode.
2787 (OP_E_register): Likewise.
2789 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2790 register on movsxd. Add movsxd with 16-bit destination register
2791 for AMD64 and Intel64 ISAs.
2792 * i386-tbl.h: Regenerated.
2794 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2797 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2798 * aarch64-asm-2.c: Regenerate
2799 * aarch64-dis-2.c: Likewise.
2800 * aarch64-opc-2.c: Likewise.
2802 2020-01-21 Jan Beulich <jbeulich@suse.com>
2804 * i386-opc.tbl (sysret): Drop DefaultSize.
2805 * i386-tbl.h: Re-generate.
2807 2020-01-21 Jan Beulich <jbeulich@suse.com>
2809 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2811 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2812 * i386-tbl.h: Re-generate.
2814 2020-01-20 Nick Clifton <nickc@redhat.com>
2816 * po/de.po: Updated German translation.
2817 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2818 * po/uk.po: Updated Ukranian translation.
2820 2020-01-20 Alan Modra <amodra@gmail.com>
2822 * hppa-dis.c (fput_const): Remove useless cast.
2824 2020-01-20 Alan Modra <amodra@gmail.com>
2826 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2828 2020-01-18 Nick Clifton <nickc@redhat.com>
2830 * configure: Regenerate.
2831 * po/opcodes.pot: Regenerate.
2833 2020-01-18 Nick Clifton <nickc@redhat.com>
2835 Binutils 2.34 branch created.
2837 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2839 * opintl.h: Fix spelling error (seperate).
2841 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2843 * i386-opc.tbl: Add {vex} pseudo prefix.
2844 * i386-tbl.h: Regenerated.
2846 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2849 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2850 (neon_opcodes): Likewise.
2851 (select_arm_features): Make sure we enable MVE bits when selecting
2852 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2855 2020-01-16 Jan Beulich <jbeulich@suse.com>
2857 * i386-opc.tbl: Drop stale comment from XOP section.
2859 2020-01-16 Jan Beulich <jbeulich@suse.com>
2861 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2862 (extractps): Add VexWIG to SSE2AVX forms.
2863 * i386-tbl.h: Re-generate.
2865 2020-01-16 Jan Beulich <jbeulich@suse.com>
2867 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2868 Size64 from and use VexW1 on SSE2AVX forms.
2869 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2870 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2871 * i386-tbl.h: Re-generate.
2873 2020-01-15 Alan Modra <amodra@gmail.com>
2875 * tic4x-dis.c (tic4x_version): Make unsigned long.
2876 (optab, optab_special, registernames): New file scope vars.
2877 (tic4x_print_register): Set up registernames rather than
2878 malloc'd registertable.
2879 (tic4x_disassemble): Delete optable and optable_special. Use
2880 optab and optab_special instead. Throw away old optab,
2881 optab_special and registernames when info->mach changes.
2883 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2886 * z80-dis.c (suffix): Use .db instruction to generate double
2889 2020-01-14 Alan Modra <amodra@gmail.com>
2891 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2892 values to unsigned before shifting.
2894 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2896 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2898 (print_insn_thumb16, print_insn_thumb32): Likewise.
2899 (print_insn): Initialize the insn info.
2900 * i386-dis.c (print_insn): Initialize the insn info fields, and
2903 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2905 * arc-opc.c (C_NE): Make it required.
2907 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2909 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2910 reserved register name.
2912 2020-01-13 Alan Modra <amodra@gmail.com>
2914 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2915 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2917 2020-01-13 Alan Modra <amodra@gmail.com>
2919 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2920 result of wasm_read_leb128 in a uint64_t and check that bits
2921 are not lost when copying to other locals. Use uint32_t for
2922 most locals. Use PRId64 when printing int64_t.
2924 2020-01-13 Alan Modra <amodra@gmail.com>
2926 * score-dis.c: Formatting.
2927 * score7-dis.c: Formatting.
2929 2020-01-13 Alan Modra <amodra@gmail.com>
2931 * score-dis.c (print_insn_score48): Use unsigned variables for
2932 unsigned values. Don't left shift negative values.
2933 (print_insn_score32): Likewise.
2934 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2936 2020-01-13 Alan Modra <amodra@gmail.com>
2938 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2940 2020-01-13 Alan Modra <amodra@gmail.com>
2942 * fr30-ibld.c: Regenerate.
2944 2020-01-13 Alan Modra <amodra@gmail.com>
2946 * xgate-dis.c (print_insn): Don't left shift signed value.
2947 (ripBits): Formatting, use 1u.
2949 2020-01-10 Alan Modra <amodra@gmail.com>
2951 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2952 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2954 2020-01-10 Alan Modra <amodra@gmail.com>
2956 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2957 and XRREG value earlier to avoid a shift with negative exponent.
2958 * m10200-dis.c (disassemble): Similarly.
2960 2020-01-09 Nick Clifton <nickc@redhat.com>
2963 * z80-dis.c (ld_ii_ii): Use correct cast.
2965 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2968 * z80-dis.c (ld_ii_ii): Use character constant when checking
2971 2020-01-09 Jan Beulich <jbeulich@suse.com>
2973 * i386-dis.c (SEP_Fixup): New.
2975 (dis386_twobyte): Use it for sysenter/sysexit.
2976 (enum x86_64_isa): Change amd64 enumerator to value 1.
2977 (OP_J): Compare isa64 against intel64 instead of amd64.
2978 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2980 * i386-tbl.h: Re-generate.
2982 2020-01-08 Alan Modra <amodra@gmail.com>
2984 * z8k-dis.c: Include libiberty.h
2985 (instr_data_s): Make max_fetched unsigned.
2986 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2987 Don't exceed byte_info bounds.
2988 (output_instr): Make num_bytes unsigned.
2989 (unpack_instr): Likewise for nibl_count and loop.
2990 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2992 * z8k-opc.h: Regenerate.
2994 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2996 * arc-tbl.h (llock): Use 'LLOCK' as class.
2998 (scond): Use 'SCOND' as class.
3000 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3003 2020-01-06 Alan Modra <amodra@gmail.com>
3005 * m32c-ibld.c: Regenerate.
3007 2020-01-06 Alan Modra <amodra@gmail.com>
3010 * z80-dis.c (suffix): Don't use a local struct buffer copy.
3011 Peek at next byte to prevent recursion on repeated prefix bytes.
3012 Ensure uninitialised "mybuf" is not accessed.
3013 (print_insn_z80): Don't zero n_fetch and n_used here,..
3014 (print_insn_z80_buf): ..do it here instead.
3016 2020-01-04 Alan Modra <amodra@gmail.com>
3018 * m32r-ibld.c: Regenerate.
3020 2020-01-04 Alan Modra <amodra@gmail.com>
3022 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3024 2020-01-04 Alan Modra <amodra@gmail.com>
3026 * crx-dis.c (match_opcode): Avoid shift left of signed value.
3028 2020-01-04 Alan Modra <amodra@gmail.com>
3030 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3032 2020-01-03 Jan Beulich <jbeulich@suse.com>
3034 * aarch64-tbl.h (aarch64_opcode_table): Use
3035 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3037 2020-01-03 Jan Beulich <jbeulich@suse.com>
3039 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3040 forms of SUDOT and USDOT.
3042 2020-01-03 Jan Beulich <jbeulich@suse.com>
3044 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3046 * aarch64-dis-2.c: Re-generate.
3048 2020-01-03 Jan Beulich <jbeulich@suse.com>
3050 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3052 * aarch64-dis-2.c: Re-generate.
3054 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3056 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3058 2020-01-01 Alan Modra <amodra@gmail.com>
3060 Update year range in copyright notice of all files.
3062 For older changes see ChangeLog-2019
3064 Copyright (C) 2020 Free Software Foundation, Inc.
3066 Copying and distribution of this file, with or without modification,
3067 are permitted in any medium without royalty provided the copyright
3068 notice and this notice are preserved.
3074 version-control: never
projects / deliverable / binutils-gdb.git / blob