opcodes/ChangeLog

   1 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
   2
   3         * Makefile.am: Run "make dep-am".
   4         * Makefile.in: Regenerate.
   5         * aclocal.m4: Regenerate.
   6         * configure: Regenerate.
   7         * po/POTFILES.in: Regenerate.
   8         * po/opcodes.pot: Regenerate.
   9
  10 2004-09-11  Andreas Schwab  <schwab@suse.de>
  11
  12         * configure: Rebuild.
  13
  14 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
  15
  16         * ppc-opc.c (L): Make this field not optional.
  17
  18 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
  19
  20         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
  21         Fix parameter to 'm[t|f]csr' insns.
  22
  23 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
  24
  25         * configure.in: Autoupdate to autoconf 2.59.
  26         * aclocal.m4: Rebuild with aclocal 1.4p6.
  27         * configure: Rebuild with autoconf 2.59.
  28         * Makefile.in: Rebuild with automake 1.4p6 (picking up
  29         bfd changes for autoconf 2.59 on the way).
  30         * config.in: Rebuild with autoheader 2.59.
  31
  32 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
  33
  34         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
  35
  36 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
  37
  38         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
  39         (GRPPADLCK2): New define.
  40         (twobyte_has_modrm): True for 0xA6.
  41         (grps): GRPPADLCK2 for opcode 0xA6.
  42
  43 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
  44
  45         Introduce SH2a support.
  46         * sh-opc.h (arch_sh2a_base): Renumber.
  47         (arch_sh2a_nofpu_base): Remove.
  48         (arch_sh_base_mask): Adjust.
  49         (arch_opann_mask): New.
  50         (arch_sh2a, arch_sh2a_nofpu): Adjust.
  51         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
  52         (sh_table): Adjust whitespace.
  53         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
  54         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
  55         instruction list throughout.
  56         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
  57         of arch_sh2a in instruction list throughout.
  58         (arch_sh2e_up): Accomodate above changes.
  59         (arch_sh2_up): Ditto.
  60         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
  61         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
  62         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
  63         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
  64         * sh-opc.h (arch_sh2a_nofpu): New.
  65         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
  66         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
  67         instruction.
  68         2004-01-20  DJ Delorie  <dj@redhat.com>
  69         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
  70         2003-12-29  DJ Delorie  <dj@redhat.com>
  71         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
  72         sh_opcode_info, sh_table): Add sh2a support.
  73         (arch_op32): New, to tag 32-bit opcodes.
  74         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
  75         2003-12-02  Michael Snyder  <msnyder@redhat.com>
  76         * sh-opc.h (arch_sh2a): Add.
  77         * sh-dis.c (arch_sh2a): Handle.
  78         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
  79
  80 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
  81
  82         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
  83
  84 2004-07-22  Nick Clifton  <nickc@redhat.com>
  85
  86         PR/280
  87         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
  88         insns - this is done by objdump itself.
  89         * h8500-dis.c (print_insn_h8500): Likewise.
  90
  91 2004-07-21  Jan Beulich <jbeulich@novell.com>
  92
  93         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
  94         regardless of address size prefix in effect.
  95         (ptr_reg): Size or address registers does not depend on rex64, but
  96         on the presence of an address size override.
  97         (OP_MMX): Use rex.x only for xmm registers.
  98         (OP_EM): Use rex.z only for xmm registers.
  99
 100 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 101
 102         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 103         move/branch operations to the bottom so that VR5400 multimedia
 104         instructions take precedence in disassembly.
 105
 106 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 107
 108         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 109         ISA-specific "break" encoding.
 110
 111 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 112
 113         * arm-opc.h: Fix typo in comment.
 114
 115 2004-07-11  Andreas Schwab  <schwab@suse.de>
 116
 117         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 118
 119 2004-07-09  Andreas Schwab  <schwab@suse.de>
 120
 121         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 122
 123 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 124
 125         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 126         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 127         (crx-dis.lo): New target.
 128         (crx-opc.lo): Likewise.
 129         * Makefile.in: Regenerate.
 130         * configure.in: Handle bfd_crx_arch.
 131         * configure: Regenerate.
 132         * crx-dis.c: New file.
 133         * crx-opc.c: New file.
 134         * disassemble.c (ARCH_crx): Define.
 135         (disassembler): Handle ARCH_crx.
 136
 137 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 138
 139         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 140         * ia64-asmtab.c: Regnerate.
 141
 142 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 143
 144         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 145         (extract_fxm): Don't test dialect.
 146         (XFXFXM_MASK): Include the power4 bit.
 147         (XFXM): Add p4 param.
 148         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 149
 150 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 151
 152         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 153         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 154
 155 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 156
 157         * ppc-opc.c (BH, XLBH_MASK): Define.
 158         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 159
 160 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 161
 162         * i386-dis.c (x_mode): Comment.
 163         (two_source_ops): File scope.
 164         (float_mem): Correct fisttpll and fistpll.
 165         (float_mem_mode): New table.
 166         (dofloat): Use it.
 167         (OP_E): Correct intel mode PTR output.
 168         (ptr_reg): Use open_char and close_char.
 169         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 170         operands.  Set two_source_ops.
 171
 172 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 173
 174         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 175         instead of _raw_size.
 176
 177 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 178
 179         * ia64-gen.c (in_iclass): Handle more postinc st
 180         and ld variants.
 181         * ia64-asmtab.c: Rebuilt.
 182
 183 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 184
 185         * s390-opc.txt: Correct architecture mask for some opcodes.
 186         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 187         in the esa mode as well.
 188
 189 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 190
 191         * sh-dis.c (target_arch): Make unsigned.
 192         (print_insn_sh): Replace (most of) switch with a call to
 193         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 194         * sh-opc.h: Redefine architecture flags values.
 195         Add sh3-nommu architecture.
 196         Reorganise <arch>_up macros so they make more visual sense.
 197         (SH_MERGE_ARCH_SET): Define new macro.
 198         (SH_VALID_BASE_ARCH_SET): Likewise.
 199         (SH_VALID_MMU_ARCH_SET): Likewise.
 200         (SH_VALID_CO_ARCH_SET): Likewise.
 201         (SH_VALID_ARCH_SET): Likewise.
 202         (SH_MERGE_ARCH_SET_VALID): Likewise.
 203         (SH_ARCH_SET_HAS_FPU): Likewise.
 204         (SH_ARCH_SET_HAS_DSP): Likewise.
 205         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 206         (sh_get_arch_from_bfd_mach): Add prototype.
 207         (sh_get_arch_up_from_bfd_mach): Likewise.
 208         (sh_get_bfd_mach_from_arch_set): Likewise.
 209         (sh_merge_bfd_arc): Likewise.
 210
 211 2004-05-24  Peter Barada  <peter@the-baradas.com>
 212
 213         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 214         into new match_insn_m68k function.  Loop over canidate
 215         matches and select first that completely matches.
 216         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 217         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 218         to verify addressing for MAC/EMAC.
 219         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 220         reigster halves since 'fpu' and 'spl' look misleading.
 221         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 222         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 223         first, tighten up match masks.
 224         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 225         'size' from special case code in print_insn_m68k to
 226         determine decode size of insns.
 227
 228 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 229
 230         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 231         well as when -mpower4.
 232
 233 2004-05-13  Nick Clifton  <nickc@redhat.com>
 234
 235         * po/fr.po: Updated French translation.
 236
 237 2004-05-05  Peter Barada  <peter@the-baradas.com>
 238
 239         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 240         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 241         * m68k-op.c: Switch from ColdFire chips to core variants.
 242
 243 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 244
 245         PR 147.
 246         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 247
 248 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 249
 250         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 251         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 252
 253 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 254
 255         * sh-dis.c (print_insn_sh): Print the value in constant pool
 256         as a symbol if it looks like a symbol.
 257
 258 2004-04-22  Peter Barada <peter@the-baradas.com>
 259
 260         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 261         appropriate ColdFire architectures.
 262         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 263         mask addressing.
 264         Add EMAC instructions, fix MAC instructions. Remove
 265         macmw/macml/msacmw/msacml instructions since mask addressing now
 266         supported.
 267
 268 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 269
 270         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 271         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 272         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 273         macro.  Adjust all users.
 274
 275 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 276
 277         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 278         separately.
 279
 280 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 281
 282         * m32r-asm.c: Regenerate.
 283
 284 2004-03-29  Stan Shebs  <shebs@apple.com>
 285
 286         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 287         used.
 288
 289 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 290
 291         * aclocal.m4: Regenerate.
 292         * config.in: Regenerate.
 293         * configure: Regenerate.
 294         * po/POTFILES.in: Regenerate.
 295         * po/opcodes.pot: Regenerate.
 296
 297 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 298
 299         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 300         PPC_OPERANDS_GPR_0.
 301         * ppc-opc.c (RA0): Define.
 302         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 303         (RAOPT): Rename from RAO.  Update all uses.
 304         (powerpc_opcodes): Use RA0 as appropriate.
 305
 306 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 307
 308         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 309
 310 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 311
 312         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 313
 314 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 315
 316         * i386-dis.c (GRPPLOCK): Delete.
 317         (grps): Delete GRPPLOCK entry.
 318
 319 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 320
 321         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 322         (M, Mp): Use OP_M.
 323         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 324         (GRPPADLCK): Define.
 325         (dis386): Use NOP_Fixup on "nop".
 326         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 327         (twobyte_has_modrm): Set for 0xa7.
 328         (padlock_table): Delete.  Move to..
 329         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 330         and clflush.
 331         (print_insn): Revert PADLOCK_SPECIAL code.
 332         (OP_E): Delete sfence, lfence, mfence checks.
 333
 334 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 335
 336         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 337         (INVLPG_Fixup): New function.
 338         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 339
 340 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 341
 342         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 343         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 344         (padlock_table): New struct with PadLock instructions.
 345         (print_insn): Handle PADLOCK_SPECIAL.
 346
 347 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 348
 349         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 350         (OP_E): Twiddle clflush to sfence here.
 351
 352 2004-03-08  Nick Clifton  <nickc@redhat.com>
 353
 354         * po/de.po: Updated German translation.
 355
 356 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 357
 358         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 359         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 360         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 361         accordingly.
 362
 363 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 364
 365         * frv-asm.c: Regenerate.
 366         * frv-desc.c: Regenerate.
 367         * frv-desc.h: Regenerate.
 368         * frv-dis.c: Regenerate.
 369         * frv-ibld.c: Regenerate.
 370         * frv-opc.c: Regenerate.
 371         * frv-opc.h: Regenerate.
 372
 373 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 374
 375         * frv-desc.c, frv-opc.c: Regenerate.
 376
 377 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 378
 379         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 380
 381 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 382
 383         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 384         Also correct mistake in the comment.
 385
 386 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 387
 388         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 389         ensure that double registers have even numbers.
 390         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 391         that reserved instruction 0xfffd does not decode the same
 392         as 0xfdfd (ftrv).
 393         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 394         REG_N refers to a double register.
 395         Add REG_N_B01 nibble type and use it instead of REG_NM
 396         in ftrv.
 397         Adjust the bit patterns in a few comments.
 398
 399 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 400
 401         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 402
 403 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 404
 405         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 406
 407 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 408
 409         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 410
 411 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 412
 413         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 414         mtivor32, mtivor33, mtivor34.
 415
 416 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 417
 418         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 419
 420 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 421
 422         * arm-opc.h Maverick accumulator register opcode fixes.
 423
 424 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 425
 426         * m32r-dis.c: Regenerate.
 427
 428 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 429
 430         * sh-opc.h (sh_table): "fsrra", not "fssra".
 431
 432 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 433
 434         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 435         contraints.
 436
 437 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 438
 439         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 440
 441 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 442
 443         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 444         1.  Don't print scale factor on AT&T mode when index missing.
 445
 446 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 447
 448         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 449         when loaded into XR registers.
 450
 451 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 452
 453         * frv-desc.h: Regenerate.
 454         * frv-desc.c: Regenerate.
 455         * frv-opc.c: Regenerate.
 456
 457 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 458
 459         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 460
 461 2004-01-09  Paul Brook  <paul@codesourcery.com>
 462
 463         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 464         specific opcodes.
 465
 466 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 467
 468         * Makefile.am (libopcodes_la_DEPENDENCIES)
 469         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 470         comment about the problem.
 471         * Makefile.in: Regenerate.
 472
 473 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 474
 475         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 476         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 477         cut&paste errors in shifting/truncating numerical operands.
 478         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 479         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 480         (parse_uslo16): Likewise.
 481         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 482         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 483         (parse_s12): Likewise.
 484         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 485         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 486         (parse_uslo16): Likewise.
 487         (parse_uhi16): Parse gothi and gotfuncdeschi.
 488         (parse_d12): Parse got12 and gotfuncdesc12.
 489         (parse_s12): Likewise.
 490
 491 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 492
 493         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 494         instruction which looks similar to an 'rla' instruction.
 495
 496 For older changes see ChangeLog-0203
 497 \f
 498 Local Variables:
 499 mode: change-log
 500 left-margin: 8
 501 fill-column: 74
 502 version-control: never
 503 End: