opcodes/ChangeLog

   1 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
   4         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
   5         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
   6         sder32_el2, vncr_el2.
   7         (aarch64_sys_reg_supported_p): Likewise.
   8         (aarch64_pstatefields): Add dit register.
   9         (aarch64_pstatefield_supported_p): Likewise.
  10         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
  11         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
  12         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
  13         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
  14         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
  15         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
  16         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
  17
  18 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  19
  20         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
  21         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
  22         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
  23         (QL_STLW, QL_STLX): New.
  24
  25 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  26
  27         * aarch64-asm.h (ins_addr_offset): New.
  28         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
  29         (aarch64_ins_addr_offset): New.
  30         * aarch64-asm-2.c: Regenerate.
  31         * aarch64-dis.h (ext_addr_offset): New.
  32         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
  33         (aarch64_ext_addr_offset): New.
  34         * aarch64-dis-2.c: Regenerate.
  35         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
  36         FLD_imm4_2 and FLD_SM3_imm2.
  37         * aarch64-opc.c (fields): Add FLD_imm6_2,
  38         FLD_imm4_2 and FLD_SM3_imm2.
  39         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
  40         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
  41         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
  42         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
  43         * aarch64-tbl.h
  44         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
  45
  46 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
  47
  48         * aarch64-tbl.h
  49         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
  50         (aarch64_feature_sm4, aarch64_feature_sha3): New.
  51         (aarch64_feature_fp_16_v8_2): New.
  52         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
  53         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
  54         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
  55
  56 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
  57
  58         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
  59         (aarch64_feature_sha2, aarch64_feature_aes): New.
  60         (SHA2, AES): New.
  61         (AES_INSN, SHA2_INSN): New.
  62         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
  63         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
  64          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
  65         Change to SHA2_INS.
  66
  67 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
  68             Tamar Christina <tamar.christina@arm.com>
  69
  70         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
  71         FP16 instructions, including vfmal.f16 and vfmsl.f16.
  72
  73 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
  74
  75         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
  76
  77 2017-11-07  Alan Modra  <amodra@gmail.com>
  78
  79         * opintl.h: Formatting, comment fixes.
  80         (gettext, ngettext): Redefine when ENABLE_NLS.
  81         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
  82         (_): Define using gettext.
  83         (textdomain, bindtextdomain): Use safer "do nothing".
  84
  85 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  86
  87         * arc-dis.c (print_hex): New variable.
  88         (parse_option): Check for hex option.
  89         (print_insn_arc): Use hexadecimal representation for short
  90         immediate values when requested.
  91         (print_arc_disassembler_options): Add hex option to the list.
  92
  93 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  94
  95         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
  96         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
  97         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
  98         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
  99         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 100         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 101         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 102         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 103         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 104         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 105         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 106         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 107         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 108         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 109         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 110         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 111         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 112         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 113         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 114         Changed opcodes.
 115         (prealloc, prefetch*): Place them before ld instruction.
 116         * arc-opc.c (skip_this_opcode): Add ARITH class.
 117
 118 2017-10-25  Alan Modra  <amodra@gmail.com>
 119
 120         PR 22348
 121         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 122         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 123         (imm4flag, size_changed): Likewise.
 124         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 125         (words, allWords, processing_argument_number): Likewise.
 126         (cst4flag, size_changed): Likewise.
 127         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 128         (crx_cst4_maps): Rename from cst4_maps.
 129         (crx_no_op_insn): Rename from no_op_insn.
 130
 131 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 132
 133         * riscv-opc.c (match_c_addi16sp) : New function.
 134         (match_c_addi4spn): New function.
 135         (match_c_lui): Don't allow 0-immediate encodings.
 136         (riscv_opcodes) <addi>: Use the above functions.
 137         <add>: Likewise.
 138         <c.addi4spn>: Likewise.
 139         <c.addi16sp>: Likewise.
 140
 141 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 142
 143         * i386-init.h: Regenerate
 144         * i386-tbl.h: Likewise
 145
 146 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 147
 148         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 149         (enum): Add EVEX_W_0F3854_P_2.
 150         * i386-dis-evex.h (evex_table): Updated.
 151         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 152         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 153         (cpu_flags): Add CpuAVX512_BITALG.
 154         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 155         (i386_cpu_flags): Add cpuavx512_bitalg..
 156         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 157         * i386-init.h: Regenerate.
 158         * i386-tbl.h: Likewise.
 159
 160 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 161
 162         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 163         * i386-dis-evex.h (evex_table): Updated.
 164         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 165         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 166         (cpu_flags): Add CpuAVX512_VNNI.
 167         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 168         (i386_cpu_flags): Add cpuavx512_vnni.
 169         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 170         * i386-init.h: Regenerate.
 171         * i386-tbl.h: Likewise.
 172
 173 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 174
 175         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 176         (enum): Remove VEX_LEN_0F3A44_P_2.
 177         (vex_len_table): Ditto.
 178         (enum): Remove VEX_W_0F3A44_P_2.
 179         (vew_w_table): Ditto.
 180         (prefix_table): Adjust instructions (see prefixes above).
 181         * i386-dis-evex.h (evex_table):
 182         Add new instructions (see prefixes above).
 183         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 184         (bitfield_cpu_flags): Ditto.
 185         * i386-opc.h (enum): Ditto.
 186         (i386_cpu_flags): Ditto.
 187         (CpuUnused): Comment out to avoid zero-width field problem.
 188         * i386-opc.tbl (vpclmulqdq): New instruction.
 189         * i386-init.h: Regenerate.
 190         * i386-tbl.h: Ditto.
 191
 192 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 193
 194         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 195         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 196         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 197         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 198         (vex_len_table): Ditto.
 199         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 200         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 201         (vew_w_table): Ditto.
 202         (prefix_table): Adjust instructions (see prefixes above).
 203         * i386-dis-evex.h (evex_table):
 204         Add new instructions (see prefixes above).
 205         * i386-gen.c (cpu_flag_init): Add VAES.
 206         (bitfield_cpu_flags): Ditto.
 207         * i386-opc.h (enum): Ditto.
 208         (i386_cpu_flags): Ditto.
 209         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 210         * i386-init.h: Regenerate.
 211         * i386-tbl.h: Ditto.
 212
 213 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 214
 215         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 216         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 217         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 218         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 219         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 220         (prefix_table): Updated (see prefixes above).
 221         (three_byte_table): Likewise.
 222         (vex_w_table): Likewise.
 223         * i386-dis-evex.h: Likewise.
 224         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 225         (cpu_flags): Add CpuGFNI.
 226         * i386-opc.h (enum): Add CpuGFNI.
 227         (i386_cpu_flags): Add cpugfni.
 228         * i386-opc.tbl: Add Intel GFNI instructions.
 229         * i386-init.h: Regenerate.
 230         * i386-tbl.h: Likewise.
 231
 232 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 233
 234         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 235         Define EXbScalar and EXwScalar for OP_EX.
 236         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 237         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 238         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 239         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 240         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 241         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 242         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 243         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 244         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 245         (OP_E_memory): Likewise.
 246         * i386-dis-evex.h: Updated.
 247         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 248         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 249         (cpu_flags): Add CpuAVX512_VBMI2.
 250         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 251         (i386_cpu_flags): Add cpuavx512_vbmi2.
 252         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 253         * i386-init.h: Regenerate.
 254         * i386-tbl.h: Likewise.
 255
 256 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 257
 258         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 259
 260 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 261
 262         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 263         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 264         K15. Add jmpix pattern.
 265
 266 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 267
 268         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 269
 270 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 271
 272         * s390-opc.c (INSTR_SI_RD): New macro.
 273         (INSTR_S_RD): Adjust example instruction.
 274         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 275         SI_RD.
 276
 277 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 278
 279         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 280         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 281         VLE multimple load/store instructions. Old e_ldm* variants are
 282         kept as aliases.
 283         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 284
 285 2017-09-27  Nick Clifton  <nickc@redhat.com>
 286
 287         PR 22179
 288         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 289         names for the fmv.x.s and fmv.s.x instructions respectively.
 290
 291 2017-09-26  do  <do@nerilex.org>
 292
 293         PR 22123
 294         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 295         be used on CPUs that have emacs support.
 296
 297 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 298
 299         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 300
 301 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 302
 303         * nds32-asm.c: Rename __BIT() to N32_BIT().
 304         * nds32-asm.h: Likewise.
 305         * nds32-dis.c: Likewise.
 306
 307 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 308
 309         * i386-dis.c (last_active_prefix): Removed.
 310         (ckprefix): Don't set last_active_prefix.
 311         (NOTRACK_Fixup): Don't check last_active_prefix.
 312
 313 2017-08-31  Nick Clifton  <nickc@redhat.com>
 314
 315         * po/fr.po: Updated French translation.
 316
 317 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 318
 319         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 320         fields.
 321
 322 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 323             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 324
 325         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 326         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 327         New entries efs2 and spe2.
 328         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 329         (SPE2_OPCD_SEGS): New macro.
 330         (spe2_opcd_indices): New.
 331         (disassemble_init_powerpc): Handle SPE2 opcodes.
 332         (lookup_spe2): New function.
 333         (print_insn_powerpc): call lookup_spe2.
 334         * ppc-opc.c (insert_evuimm1_ex0): New function.
 335         (extract_evuimm1_ex0): Likewise.
 336         (insert_evuimm_lt8): Likewise.
 337         (extract_evuimm_lt8): Likewise.
 338         (insert_off_spe2): Likewise.
 339         (extract_off_spe2): Likewise.
 340         (insert_Ddd): Likewise.
 341         (extract_Ddd): Likewise.
 342         (DD): New operand.
 343         (EVUIMM_LT8): Likewise.
 344         (EVUIMM_LT16): Adjust.
 345         (MMMM): New operand.
 346         (EVUIMM_1): Likewise.
 347         (EVUIMM_1_EX0): Likewise.
 348         (EVUIMM_2): Adjust.
 349         (NNN): New operand.
 350         (VX_OFF_SPE2): Likewise.
 351         (BBB): Likewise.
 352         (DDD): Likewise.
 353         (VX_MASK_DDD): New mask.
 354         (HH): New operand.
 355         (VX_RA_CONST): New macro.
 356         (VX_RA_CONST_MASK): Likewise.
 357         (VX_RB_CONST): Likewise.
 358         (VX_RB_CONST_MASK): Likewise.
 359         (VX_OFF_SPE2_MASK): Likewise.
 360         (VX_SPE_CRFD): Likewise.
 361         (VX_SPE_CRFD_MASK VX): Likewise.
 362         (VX_SPE2_CLR): Likewise.
 363         (VX_SPE2_CLR_MASK): Likewise.
 364         (VX_SPE2_SPLATB): Likewise.
 365         (VX_SPE2_SPLATB_MASK): Likewise.
 366         (VX_SPE2_OCTET): Likewise.
 367         (VX_SPE2_OCTET_MASK): Likewise.
 368         (VX_SPE2_DDHH): Likewise.
 369         (VX_SPE2_DDHH_MASK): Likewise.
 370         (VX_SPE2_HH): Likewise.
 371         (VX_SPE2_HH_MASK): Likewise.
 372         (VX_SPE2_EVMAR): Likewise.
 373         (VX_SPE2_EVMAR_MASK): Likewise.
 374         (PPCSPE2): Likewise.
 375         (PPCEFS2): Likewise.
 376         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 377         (powerpc_macros): Map old SPE instructions have new names
 378         with the same opcodes. Add SPE2 instructions which just are
 379         mapped to SPE2.
 380         (spe2_opcodes): Add SPE2 opcodes.
 381
 382 2017-08-23  Alan Modra  <amodra@gmail.com>
 383
 384         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 385         extract functions earlier, deleting forward declarations.
 386         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 387         RA_MASK.
 388
 389 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 390
 391         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 392
 393 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 394             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 395
 396         * ppc-opc.c (insert_evuimm2_ex0): New function.
 397         (extract_evuimm2_ex0): Likewise.
 398         (insert_evuimm4_ex0): Likewise.
 399         (extract_evuimm4_ex0): Likewise.
 400         (insert_evuimm8_ex0): Likewise.
 401         (extract_evuimm8_ex0): Likewise.
 402         (insert_evuimm_lt16): Likewise.
 403         (extract_evuimm_lt16): Likewise.
 404         (insert_rD_rS_even): Likewise.
 405         (extract_rD_rS_even): Likewise.
 406         (insert_off_lsp): Likewise.
 407         (extract_off_lsp): Likewise.
 408         (RD_EVEN): New operand.
 409         (RS_EVEN): Likewise.
 410         (RSQ): Adjust.
 411         (EVUIMM_LT16): New operand.
 412         (HTM_SI): Adjust.
 413         (EVUIMM_2_EX0): New operand.
 414         (EVUIMM_4): Adjust.
 415         (EVUIMM_4_EX0): New operand.
 416         (EVUIMM_8): Adjust.
 417         (EVUIMM_8_EX0): New operand.
 418         (WS): Adjust.
 419         (VX_OFF): New operand.
 420         (VX_LSP): New macro.
 421         (VX_LSP_MASK): Likewise.
 422         (VX_LSP_OFF_MASK): Likewise.
 423         (PPC_OPCODE_LSP): Likewise.
 424         (vle_opcodes): Add LSP opcodes.
 425         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 426
 427 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 428
 429         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 430         register operands in CRC instructions.
 431         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 432         comments.
 433
 434 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 435
 436         * disassemble.c (disassembler): Mark big and mach with
 437         ATTRIBUTE_UNUSED.
 438
 439 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 440
 441         * disassemble.c (disassembler): Remove arch/mach/endian
 442         assertions.
 443
 444 2017-07-25  Nick Clifton  <nickc@redhat.com>
 445
 446         PR 21739
 447         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 448         message.
 449         (insert_r0): Likewise.
 450         (insert_r1): Likewise.
 451         (insert_r2): Likewise.
 452         (insert_r3): Likewise.
 453         (insert_sp): Likewise.
 454         (insert_gp): Likewise.
 455         (insert_pcl): Likewise.
 456         (insert_blink): Likewise.
 457         (insert_ilink1): Likewise.
 458         (insert_ilink2): Likewise.
 459         (insert_ras): Likewise.
 460         (insert_rbs): Likewise.
 461         (insert_rcs): Likewise.
 462         (insert_simm3s): Likewise.
 463         (insert_rrange): Likewise.
 464         (insert_r13el): Likewise.
 465         (insert_fpel): Likewise.
 466         (insert_blinkel): Likewise.
 467         (insert_pclel): Likewise.
 468         (insert_nps_bitop_size_2b): Likewise.
 469         (insert_nps_imm_offset): Likewise.
 470         (insert_nps_imm_entry): Likewise.
 471         (insert_nps_size_16bit): Likewise.
 472         (insert_nps_##NAME##_pos): Likewise.
 473         (insert_nps_##NAME): Likewise.
 474         (insert_nps_bitop_ins_ext): Likewise.
 475         (insert_nps_##NAME): Likewise.
 476         (insert_nps_min_hofs): Likewise.
 477         (insert_nps_##NAME): Likewise.
 478         (insert_nps_rbdouble_64): Likewise.
 479         (insert_nps_misc_imm_offset): Likewise.
 480         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 481         option description.
 482
 483 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 484             Jiong Wang  <jiong.wang@arm.com>
 485
 486         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 487         correct the print.
 488         * aarch64-dis-2.c: Regenerated.
 489
 490 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 491
 492         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 493         table.
 494
 495 2017-07-20  Nick Clifton  <nickc@redhat.com>
 496
 497         * po/de.po: Updated German translation.
 498
 499 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 500
 501         * arc-regs.h (sec_stat): New aux register.
 502         (aux_kernel_sp): Likewise.
 503         (aux_sec_u_sp): Likewise.
 504         (aux_sec_k_sp): Likewise.
 505         (sec_vecbase_build): Likewise.
 506         (nsc_table_top): Likewise.
 507         (nsc_table_base): Likewise.
 508         (ersec_stat): Likewise.
 509         (aux_sec_except): Likewise.
 510
 511 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 512
 513         * arc-opc.c (extract_uimm12_20): New function.
 514         (UIMM12_20): New operand.
 515         (SIMM3_5_S): Adjust.
 516         * arc-tbl.h (sjli): Add new instruction.
 517
 518 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 519             John Eric Martin  <John.Martin@emmicro-us.com>
 520
 521         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 522         (UIMM3_23): Adjust accordingly.
 523         * arc-regs.h: Add/correct jli_base register.
 524         * arc-tbl.h (jli_s): Likewise.
 525
 526 2017-07-18  Nick Clifton  <nickc@redhat.com>
 527
 528         PR 21775
 529         * aarch64-opc.c: Fix spelling typos.
 530         * i386-dis.c: Likewise.
 531
 532 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 533
 534         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 535         max_addr_offset and octets variables to size_t.
 536
 537 2017-07-12  Alan Modra  <amodra@gmail.com>
 538
 539         * po/da.po: Update from translationproject.org/latest/opcodes/.
 540         * po/de.po: Likewise.
 541         * po/es.po: Likewise.
 542         * po/fi.po: Likewise.
 543         * po/fr.po: Likewise.
 544         * po/id.po: Likewise.
 545         * po/it.po: Likewise.
 546         * po/nl.po: Likewise.
 547         * po/pt_BR.po: Likewise.
 548         * po/ro.po: Likewise.
 549         * po/sv.po: Likewise.
 550         * po/tr.po: Likewise.
 551         * po/uk.po: Likewise.
 552         * po/vi.po: Likewise.
 553         * po/zh_CN.po: Likewise.
 554
 555 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 556             Alan Modra  <amodra@gmail.com>
 557
 558         * cgen.sh: Mark generated files read-only.
 559         * epiphany-asm.c: Regenerate.
 560         * epiphany-desc.c: Regenerate.
 561         * epiphany-desc.h: Regenerate.
 562         * epiphany-dis.c: Regenerate.
 563         * epiphany-ibld.c: Regenerate.
 564         * epiphany-opc.c: Regenerate.
 565         * epiphany-opc.h: Regenerate.
 566         * fr30-asm.c: Regenerate.
 567         * fr30-desc.c: Regenerate.
 568         * fr30-desc.h: Regenerate.
 569         * fr30-dis.c: Regenerate.
 570         * fr30-ibld.c: Regenerate.
 571         * fr30-opc.c: Regenerate.
 572         * fr30-opc.h: Regenerate.
 573         * frv-asm.c: Regenerate.
 574         * frv-desc.c: Regenerate.
 575         * frv-desc.h: Regenerate.
 576         * frv-dis.c: Regenerate.
 577         * frv-ibld.c: Regenerate.
 578         * frv-opc.c: Regenerate.
 579         * frv-opc.h: Regenerate.
 580         * ip2k-asm.c: Regenerate.
 581         * ip2k-desc.c: Regenerate.
 582         * ip2k-desc.h: Regenerate.
 583         * ip2k-dis.c: Regenerate.
 584         * ip2k-ibld.c: Regenerate.
 585         * ip2k-opc.c: Regenerate.
 586         * ip2k-opc.h: Regenerate.
 587         * iq2000-asm.c: Regenerate.
 588         * iq2000-desc.c: Regenerate.
 589         * iq2000-desc.h: Regenerate.
 590         * iq2000-dis.c: Regenerate.
 591         * iq2000-ibld.c: Regenerate.
 592         * iq2000-opc.c: Regenerate.
 593         * iq2000-opc.h: Regenerate.
 594         * lm32-asm.c: Regenerate.
 595         * lm32-desc.c: Regenerate.
 596         * lm32-desc.h: Regenerate.
 597         * lm32-dis.c: Regenerate.
 598         * lm32-ibld.c: Regenerate.
 599         * lm32-opc.c: Regenerate.
 600         * lm32-opc.h: Regenerate.
 601         * lm32-opinst.c: Regenerate.
 602         * m32c-asm.c: Regenerate.
 603         * m32c-desc.c: Regenerate.
 604         * m32c-desc.h: Regenerate.
 605         * m32c-dis.c: Regenerate.
 606         * m32c-ibld.c: Regenerate.
 607         * m32c-opc.c: Regenerate.
 608         * m32c-opc.h: Regenerate.
 609         * m32r-asm.c: Regenerate.
 610         * m32r-desc.c: Regenerate.
 611         * m32r-desc.h: Regenerate.
 612         * m32r-dis.c: Regenerate.
 613         * m32r-ibld.c: Regenerate.
 614         * m32r-opc.c: Regenerate.
 615         * m32r-opc.h: Regenerate.
 616         * m32r-opinst.c: Regenerate.
 617         * mep-asm.c: Regenerate.
 618         * mep-desc.c: Regenerate.
 619         * mep-desc.h: Regenerate.
 620         * mep-dis.c: Regenerate.
 621         * mep-ibld.c: Regenerate.
 622         * mep-opc.c: Regenerate.
 623         * mep-opc.h: Regenerate.
 624         * mt-asm.c: Regenerate.
 625         * mt-desc.c: Regenerate.
 626         * mt-desc.h: Regenerate.
 627         * mt-dis.c: Regenerate.
 628         * mt-ibld.c: Regenerate.
 629         * mt-opc.c: Regenerate.
 630         * mt-opc.h: Regenerate.
 631         * or1k-asm.c: Regenerate.
 632         * or1k-desc.c: Regenerate.
 633         * or1k-desc.h: Regenerate.
 634         * or1k-dis.c: Regenerate.
 635         * or1k-ibld.c: Regenerate.
 636         * or1k-opc.c: Regenerate.
 637         * or1k-opc.h: Regenerate.
 638         * or1k-opinst.c: Regenerate.
 639         * xc16x-asm.c: Regenerate.
 640         * xc16x-desc.c: Regenerate.
 641         * xc16x-desc.h: Regenerate.
 642         * xc16x-dis.c: Regenerate.
 643         * xc16x-ibld.c: Regenerate.
 644         * xc16x-opc.c: Regenerate.
 645         * xc16x-opc.h: Regenerate.
 646         * xstormy16-asm.c: Regenerate.
 647         * xstormy16-desc.c: Regenerate.
 648         * xstormy16-desc.h: Regenerate.
 649         * xstormy16-dis.c: Regenerate.
 650         * xstormy16-ibld.c: Regenerate.
 651         * xstormy16-opc.c: Regenerate.
 652         * xstormy16-opc.h: Regenerate.
 653
 654 2017-07-07  Alan Modra  <amodra@gmail.com>
 655
 656         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 657         * m32c-dis.c: Regenerate.
 658         * mep-dis.c: Regenerate.
 659
 660 2017-07-05  Borislav Petkov  <bp@suse.de>
 661
 662         * i386-dis.c: Enable ModRM.reg /6 aliases.
 663
 664 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 665
 666         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 667         with vmrs and vmsr.
 668
 669 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 670
 671         * configure: Regenerate.
 672
 673 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 674
 675         * po/opcodes.pot: Regenerate.
 676
 677 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 678
 679         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 680         entries to the MSA ASE instruction block.
 681
 682 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 683             Maciej W. Rozycki  <macro@imgtec.com>
 684
 685         * micromips-opc.c (XPA, XPAVZ): New macros.
 686         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 687         "mthgc0".
 688
 689 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 690             Maciej W. Rozycki  <macro@imgtec.com>
 691
 692         * micromips-opc.c (I36): New macro.
 693         (micromips_opcodes): Add "eretnc".
 694
 695 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 696             Andrew Bennett  <andrew.bennett@imgtec.com>
 697
 698         * mips-dis.c (mips_calculate_combination_ases): Handle the
 699         ASE_XPA_VIRT flag.
 700         (parse_mips_ase_option): New function.
 701         (parse_mips_dis_option): Factor out ASE option handling to the
 702         new function.  Call `mips_calculate_combination_ases'.
 703         * mips-opc.c (XPAVZ): New macro.
 704         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 705         "mfhgc0", "mthc0" and "mthgc0".
 706
 707 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 708
 709         * mips-dis.c (mips_calculate_combination_ases): New function.
 710         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 711         calculation to the new function.
 712         (set_default_mips_dis_options): Call the new function.
 713
 714 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 715
 716         * arc-dis.c (parse_disassembler_options): Use
 717         FOR_EACH_DISASSEMBLER_OPTION.
 718
 719 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 720
 721         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 722         disassembler option strings.
 723         (parse_cpu_option): Likewise.
 724
 725 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 726
 727         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 728         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 729         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 730         (aarch64_feature_dotprod, DOT_INSN): New.
 731         (udot, sdot): New.
 732         * aarch64-dis-2.c: Regenerated.
 733
 734 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 735
 736         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 737
 738 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 739             Matthew Fortune  <matthew.fortune@imgtec.com>
 740             Andrew Bennett  <andrew.bennett@imgtec.com>
 741
 742         * mips-formats.h (INT_BIAS): New macro.
 743         (INT_ADJ): Redefine in INT_BIAS terms.
 744         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 745         (mips_print_save_restore): New function.
 746         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 747         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 748         call.
 749         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 750         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 751         OP_SAVE_RESTORE_LIST handling, factored out from here.
 752         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 753         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 754         (mips_builtin_opcodes): Add "restore" and "save" entries.
 755         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 756         (IAMR2): New macro.
 757         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 758
 759 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 760
 761         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 762         alias; do not mark SLTI instruction as an alias.
 763
 764 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 765
 766         * i386-dis.c (RM_0FAE_REG_5): Removed.
 767         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 768         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 769         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 770         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 771         PREFIX_MOD_3_0F01_REG_5_RM_0.
 772         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 773         PREFIX_MOD_3_0FAE_REG_5.
 774         (mod_table): Update MOD_0FAE_REG_5.
 775         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 776         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 777         * i386-tbl.h: Regenerated.
 778
 779 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 780
 781         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 782         * i386-opc.tbl: Likewise.
 783         * i386-tbl.h: Regenerated.
 784
 785 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 786
 787         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 788         and "jmp{&|}".
 789         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 790         prefix.
 791
 792 2017-06-19  Nick Clifton  <nickc@redhat.com>
 793
 794         PR binutils/21614
 795         * score-dis.c (score_opcodes): Add sentinel.
 796
 797 2017-06-16  Alan Modra  <amodra@gmail.com>
 798
 799         * rx-decode.c: Regenerate.
 800
 801 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 802
 803         PR binutils/21594
 804         * i386-dis.c (OP_E_register): Check valid bnd register.
 805         (OP_G): Likewise.
 806
 807 2017-06-15  Nick Clifton  <nickc@redhat.com>
 808
 809         PR binutils/21595
 810         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 811         range value.
 812
 813 2017-06-15  Nick Clifton  <nickc@redhat.com>
 814
 815         PR binutils/21588
 816         * rl78-decode.opc (OP_BUF_LEN): Define.
 817         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 818         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 819         array.
 820         * rl78-decode.c: Regenerate.
 821
 822 2017-06-15  Nick Clifton  <nickc@redhat.com>
 823
 824         PR binutils/21586
 825         * bfin-dis.c (gregs): Clip index to prevent overflow.
 826         (regs): Likewise.
 827         (regs_lo): Likewise.
 828         (regs_hi): Likewise.
 829
 830 2017-06-14  Nick Clifton  <nickc@redhat.com>
 831
 832         PR binutils/21576
 833         * score7-dis.c (score_opcodes): Add sentinel.
 834
 835 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 836
 837         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 838         * arm-dis.c: Likewise.
 839         * ia64-dis.c: Likewise.
 840         * mips-dis.c: Likewise.
 841         * spu-dis.c: Likewise.
 842         * disassemble.h (print_insn_aarch64): New declaration, moved from
 843         include/dis-asm.h.
 844         (print_insn_big_arm, print_insn_big_mips): Likewise.
 845         (print_insn_i386, print_insn_ia64): Likewise.
 846         (print_insn_little_arm, print_insn_little_mips): Likewise.
 847
 848 2017-06-14  Nick Clifton  <nickc@redhat.com>
 849
 850         PR binutils/21587
 851         * rx-decode.opc: Include libiberty.h
 852         (GET_SCALE): New macro - validates access to SCALE array.
 853         (GET_PSCALE): New macro - validates access to PSCALE array.
 854         (DIs, SIs, S2Is, rx_disp): Use new macros.
 855         * rx-decode.c: Regenerate.
 856
 857 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 858
 859         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 860
 861 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 862
 863         * arc-dis.c (enforced_isa_mask): Declare.
 864         (cpu_types): Likewise.
 865         (parse_cpu_option): New function.
 866         (parse_disassembler_options): Use it.
 867         (print_insn_arc): Use enforced_isa_mask.
 868         (print_arc_disassembler_options): Document new options.
 869
 870 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 871
 872         * alpha-dis.c: Include disassemble.h, don't include
 873         dis-asm.h.
 874         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 875         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 876         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 877         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 878         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 879         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 880         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 881         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 882         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 883         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 884         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 885         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 886         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 887         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 888         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 889         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 890         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 891         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 892         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 893         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 894         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 895         * z80-dis.c, z8k-dis.c: Likewise.
 896         * disassemble.h: New file.
 897
 898 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 899
 900         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 901         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 902
 903 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 904
 905         * disassemble.c (disassembler): Add arguments a, big and mach.
 906         Use them.
 907
 908 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 909
 910         * i386-dis.c (NOTRACK_Fixup): New.
 911         (NOTRACK): Likewise.
 912         (NOTRACK_PREFIX): Likewise.
 913         (last_active_prefix): Likewise.
 914         (reg_table): Use NOTRACK on indirect call and jmp.
 915         (ckprefix): Set last_active_prefix.
 916         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 917         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 918         * i386-opc.h (NoTrackPrefixOk): New.
 919         (i386_opcode_modifier): Add notrackprefixok.
 920         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 921         Add notrack.
 922         * i386-tbl.h: Regenerated.
 923
 924 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 925
 926         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 927         (X_IMM2): Define.
 928         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 929         bfd_mach_sparc_v9m8.
 930         (print_insn_sparc): Handle new operand types.
 931         * sparc-opc.c (MASK_M8): Define.
 932         (v6): Add MASK_M8.
 933         (v6notlet): Likewise.
 934         (v7): Likewise.
 935         (v8): Likewise.
 936         (v9): Likewise.
 937         (v9a): Likewise.
 938         (v9b): Likewise.
 939         (v9c): Likewise.
 940         (v9d): Likewise.
 941         (v9e): Likewise.
 942         (v9v): Likewise.
 943         (v9m): Likewise.
 944         (v9andleon): Likewise.
 945         (m8): Define.
 946         (HWS_VM8): Define.
 947         (HWS2_VM8): Likewise.
 948         (sparc_opcode_archs): Add entry for "m8".
 949         (sparc_opcodes): Add OSA2017 and M8 instructions
 950         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 951         fpx{ll,ra,rl}64x,
 952         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 953         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 954         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 955         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 956         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 957         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 958         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 959         ASI_CORE_SELECT_COMMIT_NHT.
 960
 961 2017-05-18  Alan Modra  <amodra@gmail.com>
 962
 963         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 964         * aarch64-dis.c: Likewise.
 965         * aarch64-gen.c: Likewise.
 966         * aarch64-opc.c: Likewise.
 967
 968 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 969             Matthew Fortune  <matthew.fortune@imgtec.com>
 970
 971         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 972         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 973         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 974         (print_insn_arg) <OP_REG28>: Add handler.
 975         (validate_insn_args) <OP_REG28>: Handle.
 976         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 977         32-bit encoding and 9-bit immediates.
 978         (print_insn_mips16): Handle MIPS16 instructions that require
 979         32-bit encoding and MFC0/MTC0 operand decoding.
 980         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 981         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 982         (RD_C0, WR_C0, E2, E2MT): New macros.
 983         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 984         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 985         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 986         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 987         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 988         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 989         instructions, "swl", "swr", "sync" and its "sync_acquire",
 990         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 991         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 992         regular/extended entries for original MIPS16 ISA revision
 993         instructions whose extended forms are subdecoded in the MIPS16e2
 994         ISA revision: "li", "sll" and "srl".
 995
 996 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 997
 998         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 999         reference in CP0 move operand decoding.
1000
1001 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1002
1003         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1004         type to hexadecimal.
1005         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1006
1007 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1008
1009         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1010         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1011         "sync_rmb" and "sync_wmb" as aliases.
1012         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1013         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1014
1015 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1016
1017         * arc-dis.c (parse_option): Update quarkse_em option..
1018         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1019         QUARKSE1.
1020         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1021
1022 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1023
1024         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1025
1026 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1027
1028         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1029         register.
1030
1031 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1032
1033         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1034         and branches and not synthetic data instructions.
1035
1036 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1037
1038         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1039
1040 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1041
1042         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1043         * arc-opc.c (insert_r13el): New function.
1044         (R13_EL): Define.
1045         * arc-tbl.h: Add new enter/leave variants.
1046
1047 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1048
1049         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1050
1051 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1052
1053         * mips-dis.c (print_mips_disassembler_options): Add
1054         `no-aliases'.
1055
1056 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1057
1058         * mips16-opc.c (AL): New macro.
1059         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1060         of "ld" and "lw" as aliases.
1061
1062 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1063
1064         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1065         arguments.
1066
1067 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1068             Alan Modra  <amodra@gmail.com>
1069
1070         * ppc-opc.c (ELEV): Define.
1071         (vle_opcodes): Add se_rfgi and e_sc.
1072         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1073         for E200Z4.
1074
1075 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1076
1077         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1078
1079 2017-04-21  Nick Clifton  <nickc@redhat.com>
1080
1081         PR binutils/21380
1082         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1083         LD3R and LD4R.
1084
1085 2017-04-13  Alan Modra  <amodra@gmail.com>
1086
1087         * epiphany-desc.c: Regenerate.
1088         * fr30-desc.c: Regenerate.
1089         * frv-desc.c: Regenerate.
1090         * ip2k-desc.c: Regenerate.
1091         * iq2000-desc.c: Regenerate.
1092         * lm32-desc.c: Regenerate.
1093         * m32c-desc.c: Regenerate.
1094         * m32r-desc.c: Regenerate.
1095         * mep-desc.c: Regenerate.
1096         * mt-desc.c: Regenerate.
1097         * or1k-desc.c: Regenerate.
1098         * xc16x-desc.c: Regenerate.
1099         * xstormy16-desc.c: Regenerate.
1100
1101 2017-04-11  Alan Modra  <amodra@gmail.com>
1102
1103         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1104         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1105         PPC_OPCODE_TMR for e6500.
1106         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1107         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1108         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1109         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1110         (PPCHTM): Define as PPC_OPCODE_POWER8.
1111         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1112
1113 2017-04-10  Alan Modra  <amodra@gmail.com>
1114
1115         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1116         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1117         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1118         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1119
1120 2017-04-09  Pip Cet  <pipcet@gmail.com>
1121
1122         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1123         appropriate floating-point precision directly.
1124
1125 2017-04-07  Alan Modra  <amodra@gmail.com>
1126
1127         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1128         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1129         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1130         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1131         vector instructions with E6500 not PPCVEC2.
1132
1133 2017-04-06  Pip Cet  <pipcet@gmail.com>
1134
1135         * Makefile.am: Add wasm32-dis.c.
1136         * configure.ac: Add wasm32-dis.c to wasm32 target.
1137         * disassemble.c: Add wasm32 disassembler code.
1138         * wasm32-dis.c: New file.
1139         * Makefile.in: Regenerate.
1140         * configure: Regenerate.
1141         * po/POTFILES.in: Regenerate.
1142         * po/opcodes.pot: Regenerate.
1143
1144 2017-04-05  Pedro Alves  <palves@redhat.com>
1145
1146         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1147         * arm-dis.c (parse_arm_disassembler_options): Constify.
1148         * ppc-dis.c (powerpc_init_dialect): Constify local.
1149         * vax-dis.c (parse_disassembler_options): Constify.
1150
1151 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1152
1153         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1154         RISCV_GP_SYMBOL.
1155
1156 2017-03-30  Pip Cet  <pipcet@gmail.com>
1157
1158         * configure.ac: Add (empty) bfd_wasm32_arch target.
1159         * configure: Regenerate
1160         * po/opcodes.pot: Regenerate.
1161
1162 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1163
1164         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1165         OSA2015.
1166         * opcodes/sparc-opc.c (asi_table): New ASIs.
1167
1168 2017-03-29  Alan Modra  <amodra@gmail.com>
1169
1170         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1171         "raw" option.
1172         (lookup_powerpc): Don't special case -1 dialect.  Handle
1173         PPC_OPCODE_RAW.
1174         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1175         lookup_powerpc call, pass it on second.
1176
1177 2017-03-27  Alan Modra  <amodra@gmail.com>
1178
1179         PR 21303
1180         * ppc-dis.c (struct ppc_mopt): Comment.
1181         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1182
1183 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1184
1185         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1186         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1187         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1188         (insert_nps_misc_imm_offset): New function.
1189         (extract_nps_misc imm_offset): New function.
1190         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1191         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1192
1193 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1194
1195         * s390-mkopc.c (main): Remove vx2 check.
1196         * s390-opc.txt: Remove vx2 instruction flags.
1197
1198 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1199
1200         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1201         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1202         (insert_nps_imm_offset): New function.
1203         (extract_nps_imm_offset): New function.
1204         (insert_nps_imm_entry): New function.
1205         (extract_nps_imm_entry): New function.
1206
1207 2017-03-17  Alan Modra  <amodra@gmail.com>
1208
1209         PR 21248
1210         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1211         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1212         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1213
1214 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1215
1216         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1217         <c.andi>: Likewise.
1218         <c.addiw> Likewise.
1219
1220 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1221
1222         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1223
1224 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1225
1226         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1227         <srl> Likewise.
1228         <srai> Likewise.
1229         <sra> Likewise.
1230
1231 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1232
1233         * i386-gen.c (opcode_modifiers): Replace S with Load.
1234         * i386-opc.h (S): Removed.
1235         (Load): New.
1236         (i386_opcode_modifier): Replace s with load.
1237         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1238         and {evex}.  Replace S with Load.
1239         * i386-tbl.h: Regenerated.
1240
1241 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1242
1243         * i386-opc.tbl: Use CpuCET on rdsspq.
1244         * i386-tbl.h: Regenerated.
1245
1246 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1247
1248         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1249         <vsx>: Do not use PPC_OPCODE_VSX3;
1250
1251 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1252
1253         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1254
1255 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1256
1257         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1258         (MOD_0F1E_PREFIX_1): Likewise.
1259         (MOD_0F38F5_PREFIX_2): Likewise.
1260         (MOD_0F38F6_PREFIX_0): Likewise.
1261         (RM_0F1E_MOD_3_REG_7): Likewise.
1262         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1263         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1264         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1265         (PREFIX_0F1E): Likewise.
1266         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1267         (PREFIX_0F38F5): Likewise.
1268         (dis386_twobyte): Use PREFIX_0F1E.
1269         (reg_table): Add REG_0F1E_MOD_3.
1270         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1271         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1272         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1273         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1274         (three_byte_table): Use PREFIX_0F38F5.
1275         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1276         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1277         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1278         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1279         PREFIX_MOD_3_0F01_REG_5_RM_2.
1280         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1281         (cpu_flags): Add CpuCET.
1282         * i386-opc.h (CpuCET): New enum.
1283         (CpuUnused): Commented out.
1284         (i386_cpu_flags): Add cpucet.
1285         * i386-opc.tbl: Add Intel CET instructions.
1286         * i386-init.h: Regenerated.
1287         * i386-tbl.h: Likewise.
1288
1289 2017-03-06  Alan Modra  <amodra@gmail.com>
1290
1291         PR 21124
1292         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1293         (extract_raq, extract_ras, extract_rbx): New functions.
1294         (powerpc_operands): Use opposite corresponding insert function.
1295         (Q_MASK): Define.
1296         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1297         register restriction.
1298
1299 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1300
1301         * disassemble.c Include "safe-ctype.h".
1302         (disassemble_init_for_target): Handle s390 init.
1303         (remove_whitespace_and_extra_commas): New function.
1304         (disassembler_options_cmp): Likewise.
1305         * arm-dis.c: Include "libiberty.h".
1306         (NUM_ELEM): Delete.
1307         (regnames): Use long disassembler style names.
1308         Add force-thumb and no-force-thumb options.
1309         (NUM_ARM_REGNAMES): Rename from this...
1310         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1311         (get_arm_regname_num_options): Delete.
1312         (set_arm_regname_option): Likewise.
1313         (get_arm_regnames): Likewise.
1314         (parse_disassembler_options): Likewise.
1315         (parse_arm_disassembler_option): Rename from this...
1316         (parse_arm_disassembler_options): ...to this.  Make static.
1317         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1318         (print_insn): Use parse_arm_disassembler_options.
1319         (disassembler_options_arm): New function.
1320         (print_arm_disassembler_options): Handle updated regnames.
1321         * ppc-dis.c: Include "libiberty.h".
1322         (ppc_opts): Add "32" and "64" entries.
1323         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1324         (powerpc_init_dialect): Add break to switch statement.
1325         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1326         (disassembler_options_powerpc): New function.
1327         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1328         Remove printing of "32" and "64".
1329         * s390-dis.c: Include "libiberty.h".
1330         (init_flag): Remove unneeded variable.
1331         (struct s390_options_t): New structure type.
1332         (options): New structure.
1333         (init_disasm): Rename from this...
1334         (disassemble_init_s390): ...to this.  Add initializations for
1335         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1336         (print_insn_s390): Delete call to init_disasm.
1337         (disassembler_options_s390): New function.
1338         (print_s390_disassembler_options): Print using information from
1339         struct 'options'.
1340         * po/opcodes.pot: Regenerate.
1341
1342 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1343
1344         * i386-dis.c (PCMPESTR_Fixup): New.
1345         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1346         (prefix_table): Use PCMPESTR_Fixup.
1347         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1348         PCMPESTR_Fixup.
1349         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1350         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1351         Split 64-bit and non-64-bit variants.
1352         * opcodes/i386-tbl.h: Re-generate.
1353
1354 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1355
1356         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1357         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1358         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1359         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1360         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1361         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1362         (OP_SVE_V_HSD): New macros.
1363         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1364         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1365         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1366         (aarch64_opcode_table): Add new SVE instructions.
1367         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1368         for rotation operands.  Add new SVE operands.
1369         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1370         (ins_sve_quad_index): Likewise.
1371         (ins_imm_rotate): Split into...
1372         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1373         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1374         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1375         functions.
1376         (aarch64_ins_sve_addr_ri_s4): New function.
1377         (aarch64_ins_sve_quad_index): Likewise.
1378         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1379         * aarch64-asm-2.c: Regenerate.
1380         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1381         (ext_sve_quad_index): Likewise.
1382         (ext_imm_rotate): Split into...
1383         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1384         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1385         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1386         functions.
1387         (aarch64_ext_sve_addr_ri_s4): New function.
1388         (aarch64_ext_sve_quad_index): Likewise.
1389         (aarch64_ext_sve_index): Allow quad indices.
1390         (do_misc_decoding): Likewise.
1391         * aarch64-dis-2.c: Regenerate.
1392         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1393         aarch64_field_kinds.
1394         (OPD_F_OD_MASK): Widen by one bit.
1395         (OPD_F_NO_ZR): Bump accordingly.
1396         (get_operand_field_width): New function.
1397         * aarch64-opc.c (fields): Add new SVE fields.
1398         (operand_general_constraint_met_p): Handle new SVE operands.
1399         (aarch64_print_operand): Likewise.
1400         * aarch64-opc-2.c: Regenerate.
1401
1402 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1403
1404         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1405         (aarch64_feature_compnum): ...this.
1406         (SIMD_V8_3): Replace with...
1407         (COMPNUM): ...this.
1408         (CNUM_INSN): New macro.
1409         (aarch64_opcode_table): Use it for the complex number instructions.
1410
1411 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1412
1413         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1414
1415 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1416
1417         Add support for associating SPARC ASIs with an architecture level.
1418         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1419         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1420         decoding of SPARC ASIs.
1421
1422 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1423
1424         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1425         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1426
1427 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1428
1429         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1430         1 (instead of to itself). Correct typo.
1431
1432 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1433
1434         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1435         pseudoinstructions.
1436
1437 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1438
1439         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1440         (aarch64_sys_reg_supported_p): Handle them.
1441
1442 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1443
1444         * arc-opc.c (UIMM6_20R): Define.
1445         (SIMM12_20): Use above.
1446         (SIMM12_20R): Define.
1447         (SIMM3_5_S): Use above.
1448         (UIMM7_A32_11R_S): Define.
1449         (UIMM7_9_S): Use above.
1450         (UIMM3_13R_S): Define.
1451         (SIMM11_A32_7_S): Use above.
1452         (SIMM9_8R): Define.
1453         (UIMM10_A32_8_S): Use above.
1454         (UIMM8_8R_S): Define.
1455         (W6): Use above.
1456         (arc_relax_opcodes): Use all above defines.
1457
1458 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1459
1460         * arc-regs.h: Distinguish some of the registers different on
1461         ARC700 and HS38 cpus.
1462
1463 2017-02-14  Alan Modra  <amodra@gmail.com>
1464
1465         PR 21118
1466         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1467         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1468
1469 2017-02-11  Stafford Horne  <shorne@gmail.com>
1470             Alan Modra  <amodra@gmail.com>
1471
1472         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1473         Use insn_bytes_value and insn_int_value directly instead.  Don't
1474         free allocated memory until function exit.
1475
1476 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1477
1478         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1479
1480 2017-02-03  Nick Clifton  <nickc@redhat.com>
1481
1482         PR 21096
1483         * aarch64-opc.c (print_register_list): Ensure that the register
1484         list index will fir into the tb buffer.
1485         (print_register_offset_address): Likewise.
1486         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1487
1488 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1489
1490         PR 21056
1491         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1492         instructions when the previous fetch packet ends with a 32-bit
1493         instruction.
1494
1495 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1496
1497         * pru-opc.c: Remove vague reference to a future GDB port.
1498
1499 2017-01-20  Nick Clifton  <nickc@redhat.com>
1500
1501         * po/ga.po: Updated Irish translation.
1502
1503 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1504
1505         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1506
1507 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1508
1509         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1510         if FETCH_DATA returns 0.
1511         (m68k_scan_mask): Likewise.
1512         (print_insn_m68k): Update code to handle -1 return value.
1513
1514 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1515
1516         * m68k-dis.c (enum print_insn_arg_error): New.
1517         (NEXTBYTE): Replace -3 with
1518         PRINT_INSN_ARG_MEMORY_ERROR.
1519         (NEXTULONG): Likewise.
1520         (NEXTSINGLE): Likewise.
1521         (NEXTDOUBLE): Likewise.
1522         (NEXTDOUBLE): Likewise.
1523         (NEXTPACKED): Likewise.
1524         (FETCH_ARG): Likewise.
1525         (FETCH_DATA): Update comments.
1526         (print_insn_arg): Update comments. Replace magic numbers with
1527         enum.
1528         (match_insn_m68k): Likewise.
1529
1530 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1531
1532         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1533         * i386-dis-evex.h (evex_table): Updated.
1534         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1535         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1536         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1537         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1538         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1539         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1540         * i386-init.h: Regenerate.
1541         * i386-tbl.h: Ditto.
1542
1543 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1544
1545         * msp430-dis.c (msp430_singleoperand): Return -1 if
1546         msp430dis_opcode_signed returns false.
1547         (msp430_doubleoperand): Likewise.
1548         (msp430_branchinstr): Return -1 if
1549         msp430dis_opcode_unsigned returns false.
1550         (msp430x_calla_instr): Likewise.
1551         (print_insn_msp430): Likewise.
1552
1553 2017-01-05  Nick Clifton  <nickc@redhat.com>
1554
1555         PR 20946
1556         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1557         could not be matched.
1558         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1559         NULL.
1560
1561 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1562
1563         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1564         (aarch64_opcode_table): Use RCPC_INSN.
1565
1566 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1567
1568         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1569         extension.
1570         * riscv-opcodes/all-opcodes: Likewise.
1571
1572 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1573
1574         * riscv-dis.c (print_insn_args): Add fall through comment.
1575
1576 2017-01-03  Nick Clifton  <nickc@redhat.com>
1577
1578         * po/sr.po: New Serbian translation.
1579         * configure.ac (ALL_LINGUAS): Add sr.
1580         * configure: Regenerate.
1581
1582 2017-01-02  Alan Modra  <amodra@gmail.com>
1583
1584         * epiphany-desc.h: Regenerate.
1585         * epiphany-opc.h: Regenerate.
1586         * fr30-desc.h: Regenerate.
1587         * fr30-opc.h: Regenerate.
1588         * frv-desc.h: Regenerate.
1589         * frv-opc.h: Regenerate.
1590         * ip2k-desc.h: Regenerate.
1591         * ip2k-opc.h: Regenerate.
1592         * iq2000-desc.h: Regenerate.
1593         * iq2000-opc.h: Regenerate.
1594         * lm32-desc.h: Regenerate.
1595         * lm32-opc.h: Regenerate.
1596         * m32c-desc.h: Regenerate.
1597         * m32c-opc.h: Regenerate.
1598         * m32r-desc.h: Regenerate.
1599         * m32r-opc.h: Regenerate.
1600         * mep-desc.h: Regenerate.
1601         * mep-opc.h: Regenerate.
1602         * mt-desc.h: Regenerate.
1603         * mt-opc.h: Regenerate.
1604         * or1k-desc.h: Regenerate.
1605         * or1k-opc.h: Regenerate.
1606         * xc16x-desc.h: Regenerate.
1607         * xc16x-opc.h: Regenerate.
1608         * xstormy16-desc.h: Regenerate.
1609         * xstormy16-opc.h: Regenerate.
1610
1611 2017-01-02  Alan Modra  <amodra@gmail.com>
1612
1613         Update year range in copyright notice of all files.
1614
1615 For older changes see ChangeLog-2016
1616 \f
1617 Copyright (C) 2017 Free Software Foundation, Inc.
1618
1619 Copying and distribution of this file, with or without modification,
1620 are permitted in any medium without royalty provided the copyright
1621 notice and this notice are preserved.
1622
1623 Local Variables:
1624 mode: change-log
1625 left-margin: 8
1626 fill-column: 74
1627 version-control: never
1628 End: