opcodes/ChangeLog

   1 2016-10-06  Alan Modra  <amodra@gmail.com>
   2
   3         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
   4         * crx-dis.c (print_insn_crx): Likewise.
   5
   6 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         PR binutils/20657
   9         * i386-dis.c (putop): Don't assign alt twice.
  10
  11 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
  12
  13         PR target/20553
  14         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
  15
  16 2016-09-29  Alan Modra  <amodra@gmail.com>
  17
  18         * ppc-opc.c (L): Make compulsory.
  19         (LOPT): New, optional form of L.
  20         (HTM_R): Define as LOPT.
  21         (L0, L1): Delete.
  22         (L32OPT): New, optional for 32-bit L.
  23         (L2OPT): New, 2-bit L for dcbf.
  24         (SVC_LEC): Update.
  25         (L2): Define.
  26         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
  27         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
  28         <dcbf>: Use L2OPT.
  29         <tlbiel, tlbie>: Use LOPT.
  30         <wclr, wclrall>: Use L2.
  31
  32 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
  33
  34         * Makefile.in: Regenerate.
  35         * configure: Likewise.
  36
  37 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
  38
  39         * arc-ext-tbl.h (EXTINSN2OPF): Define.
  40         (EXTINSN2OP): Use EXTINSN2OPF.
  41         (bspeekm, bspop, modapp): New extension instructions.
  42         * arc-opc.c (F_DNZ_ND): Define.
  43         (F_DNZ_D): Likewise.
  44         (F_SIZEB1): Changed.
  45         (C_DNZ_D): Define.
  46         (C_HARD): Changed.
  47         * arc-tbl.h (dbnz): New instruction.
  48         (prealloc): Allow it for ARC EM.
  49         (xbfu): Likewise.
  50
  51 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  52
  53         * aarch64-opc.c (print_immediate_offset_address): Print spaces
  54         after commas in addresses.
  55         (aarch64_print_operand): Likewise.
  56
  57 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  58
  59         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
  60         rather than "should be" or "expected to be" in error messages.
  61
  62 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  63
  64         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
  65         (print_mnemonic_name): ...here.
  66         (print_comment): New function.
  67         (print_aarch64_insn): Call it.
  68         * aarch64-opc.c (aarch64_conds): Add SVE names.
  69         (aarch64_print_operand): Print alternative condition names in
  70         a comment.
  71
  72 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  73
  74         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
  75         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
  76         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
  77         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
  78         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
  79         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
  80         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
  81         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
  82         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
  83         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
  84         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
  85         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
  86         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
  87         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
  88         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
  89         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
  90         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
  91         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
  92         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
  93         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
  94         (OP_SVE_XWU, OP_SVE_XXU): New macros.
  95         (aarch64_feature_sve): New variable.
  96         (SVE): New macro.
  97         (_SVE_INSN): Likewise.
  98         (aarch64_opcode_table): Add SVE instructions.
  99         * aarch64-opc.h (extract_fields): Declare.
 100         * aarch64-opc-2.c: Regenerate.
 101         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 102         * aarch64-asm-2.c: Regenerate.
 103         * aarch64-dis.c (extract_fields): Make global.
 104         (do_misc_decoding): Handle the new SVE aarch64_ops.
 105         * aarch64-dis-2.c: Regenerate.
 106
 107 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 108
 109         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 110         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 111         aarch64_field_kinds.
 112         * aarch64-opc.c (fields): Add corresponding entries.
 113         * aarch64-asm.c (aarch64_get_variant): New function.
 114         (aarch64_encode_variant_using_iclass): Likewise.
 115         (aarch64_opcode_encode): Call it.
 116         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 117         (aarch64_opcode_decode): Call it.
 118
 119 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 120
 121         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 122         and FP register operands.
 123         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 124         (FLD_SVE_Vn): New aarch64_field_kinds.
 125         * aarch64-opc.c (fields): Add corresponding entries.
 126         (aarch64_print_operand): Handle the new SVE core and FP register
 127         operands.
 128         * aarch64-opc-2.c: Regenerate.
 129         * aarch64-asm-2.c: Likewise.
 130         * aarch64-dis-2.c: Likewise.
 131
 132 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 133
 134         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 135         immediate operands.
 136         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 137         * aarch64-opc.c (fields): Add corresponding entry.
 138         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 139         operands.
 140         (aarch64_print_operand): Likewise.
 141         * aarch64-opc-2.c: Regenerate.
 142         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 143         (ins_sve_float_zero_one): New inserters.
 144         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 145         (aarch64_ins_sve_float_half_two): Likewise.
 146         (aarch64_ins_sve_float_zero_one): Likewise.
 147         * aarch64-asm-2.c: Regenerate.
 148         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 149         (ext_sve_float_zero_one): New extractors.
 150         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 151         (aarch64_ext_sve_float_half_two): Likewise.
 152         (aarch64_ext_sve_float_zero_one): Likewise.
 153         * aarch64-dis-2.c: Regenerate.
 154
 155 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 156
 157         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 158         integer immediate operands.
 159         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 160         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 161         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 162         * aarch64-opc.c (fields): Add corresponding entries.
 163         (operand_general_constraint_met_p): Handle the new SVE integer
 164         immediate operands.
 165         (aarch64_print_operand): Likewise.
 166         (aarch64_sve_dupm_mov_immediate_p): New function.
 167         * aarch64-opc-2.c: Regenerate.
 168         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 169         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 170         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 171         (aarch64_ins_limm): ...here.
 172         (aarch64_ins_inv_limm): New function.
 173         (aarch64_ins_sve_aimm): Likewise.
 174         (aarch64_ins_sve_asimm): Likewise.
 175         (aarch64_ins_sve_limm_mov): Likewise.
 176         (aarch64_ins_sve_shlimm): Likewise.
 177         (aarch64_ins_sve_shrimm): Likewise.
 178         * aarch64-asm-2.c: Regenerate.
 179         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 180         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 181         * aarch64-dis.c (decode_limm): New function, split out from...
 182         (aarch64_ext_limm): ...here.
 183         (aarch64_ext_inv_limm): New function.
 184         (decode_sve_aimm): Likewise.
 185         (aarch64_ext_sve_aimm): Likewise.
 186         (aarch64_ext_sve_asimm): Likewise.
 187         (aarch64_ext_sve_limm_mov): Likewise.
 188         (aarch64_top_bit): Likewise.
 189         (aarch64_ext_sve_shlimm): Likewise.
 190         (aarch64_ext_sve_shrimm): Likewise.
 191         * aarch64-dis-2.c: Regenerate.
 192
 193 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 194
 195         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 196         operands.
 197         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 198         the AARCH64_MOD_MUL_VL entry.
 199         (value_aligned_p): Cope with non-power-of-two alignments.
 200         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 201         (print_immediate_offset_address): Likewise.
 202         (aarch64_print_operand): Likewise.
 203         * aarch64-opc-2.c: Regenerate.
 204         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 205         (ins_sve_addr_ri_s9xvl): New inserters.
 206         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 207         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 208         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 209         * aarch64-asm-2.c: Regenerate.
 210         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 211         (ext_sve_addr_ri_s9xvl): New extractors.
 212         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 213         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 214         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 215         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 216         * aarch64-dis-2.c: Regenerate.
 217
 218 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 219
 220         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 221         address operands.
 222         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 223         (FLD_SVE_xs_22): New aarch64_field_kinds.
 224         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 225         (get_operand_specific_data): New function.
 226         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 227         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 228         (operand_general_constraint_met_p): Handle the new SVE address
 229         operands.
 230         (sve_reg): New array.
 231         (get_addr_sve_reg_name): New function.
 232         (aarch64_print_operand): Handle the new SVE address operands.
 233         * aarch64-opc-2.c: Regenerate.
 234         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 235         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 236         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 237         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 238         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 239         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 240         (aarch64_ins_sve_addr_zi_u5): Likewise.
 241         (aarch64_ins_sve_addr_zz): Likewise.
 242         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 243         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 244         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 245         * aarch64-asm-2.c: Regenerate.
 246         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 247         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 248         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 249         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 250         (aarch64_ext_sve_addr_ri_u6): Likewise.
 251         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 252         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 253         (aarch64_ext_sve_addr_zi_u5): Likewise.
 254         (aarch64_ext_sve_addr_zz): Likewise.
 255         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 256         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 257         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 258         * aarch64-dis-2.c: Regenerate.
 259
 260 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 261
 262         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 263         AARCH64_OPND_SVE_PATTERN_SCALED.
 264         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 265         * aarch64-opc.c (fields): Add a corresponding entry.
 266         (set_multiplier_out_of_range_error): New function.
 267         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 268         (operand_general_constraint_met_p): Handle
 269         AARCH64_OPND_SVE_PATTERN_SCALED.
 270         (print_register_offset_address): Use PRIi64 to print the
 271         shift amount.
 272         (aarch64_print_operand): Likewise.  Handle
 273         AARCH64_OPND_SVE_PATTERN_SCALED.
 274         * aarch64-opc-2.c: Regenerate.
 275         * aarch64-asm.h (ins_sve_scale): New inserter.
 276         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 277         * aarch64-asm-2.c: Regenerate.
 278         * aarch64-dis.h (ext_sve_scale): New inserter.
 279         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 280         * aarch64-dis-2.c: Regenerate.
 281
 282 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 283
 284         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 285         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 286         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 287         (FLD_SVE_prfop): Likewise.
 288         * aarch64-opc.c: Include libiberty.h.
 289         (aarch64_sve_pattern_array): New variable.
 290         (aarch64_sve_prfop_array): Likewise.
 291         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 292         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 293         AARCH64_OPND_SVE_PRFOP.
 294         * aarch64-asm-2.c: Regenerate.
 295         * aarch64-dis-2.c: Likewise.
 296         * aarch64-opc-2.c: Likewise.
 297
 298 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 299
 300         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 301         AARCH64_OPND_QLF_P_[ZM].
 302         (aarch64_print_operand): Print /z and /m where appropriate.
 303
 304 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 305
 306         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 307         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 308         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 309         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 310         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 311         * aarch64-opc.c (fields): Add corresponding entries here.
 312         (operand_general_constraint_met_p): Check that SVE register lists
 313         have the correct length.  Check the ranges of SVE index registers.
 314         Check for cases where p8-p15 are used in 3-bit predicate fields.
 315         (aarch64_print_operand): Handle the new SVE operands.
 316         * aarch64-opc-2.c: Regenerate.
 317         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 318         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 319         (aarch64_ins_sve_reglist): Likewise.
 320         * aarch64-asm-2.c: Regenerate.
 321         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 322         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 323         (aarch64_ext_sve_reglist): Likewise.
 324         * aarch64-dis-2.c: Regenerate.
 325
 326 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 327
 328         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 329         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 330         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 331         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 332         tied operands.
 333
 334 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 335
 336         * aarch64-opc.c (get_offset_int_reg_name): New function.
 337         (print_immediate_offset_address): Likewise.
 338         (print_register_offset_address): Take the base and offset
 339         registers as parameters.
 340         (aarch64_print_operand): Update caller accordingly.  Use
 341         print_immediate_offset_address.
 342
 343 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 344
 345         * aarch64-opc.c (BANK): New macro.
 346         (R32, R64): Take a register number as argument
 347         (int_reg): Use BANK.
 348
 349 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 350
 351         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 352         (aarch64_print_operand): Update accordingly.
 353
 354 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 355
 356         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 357         for FPIMM.
 358         * aarch64-asm.h (ins_fpimm): New inserter.
 359         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 360         * aarch64-asm-2.c: Regenerate.
 361         * aarch64-dis.h (ext_fpimm): New extractor.
 362         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 363         (aarch64_ext_fpimm): New function.
 364         * aarch64-dis-2.c: Regenerate.
 365
 366 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 367
 368         * aarch64-asm.c: Include libiberty.h.
 369         (insert_fields): New function.
 370         (aarch64_ins_imm): Use it.
 371         * aarch64-dis.c (extract_fields): New function.
 372         (aarch64_ext_imm): Use it.
 373
 374 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 375
 376         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 377         with an esize parameter.
 378         (operand_general_constraint_met_p): Update accordingly.
 379         Fix misindented code.
 380         * aarch64-asm.c (aarch64_ins_limm): Update call to
 381         aarch64_logical_immediate_p.
 382
 383 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 384
 385         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 386
 387 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 388
 389         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 390
 391 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 392
 393         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 394
 395 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 396
 397         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 398         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 399         xor3>: Delete mnemonics.
 400         <cp_abort>: Rename mnemonic from ...
 401         <cpabort>: ...to this.
 402         <setb>: Change to a X form instruction.
 403         <sync>: Change to 1 operand form.
 404         <copy>: Delete mnemonic.
 405         <copy_first>: Rename mnemonic from ...
 406         <copy>: ...to this.
 407         <paste, paste.>: Delete mnemonics.
 408         <paste_last>: Rename mnemonic from ...
 409         <paste.>: ...to this.
 410
 411 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 412
 413         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 414
 415 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 416
 417         * s390-mkopc.c (main): Support alternate arch strings.
 418
 419 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 420
 421         * s390-opc.txt: Fix kmctr instruction type.
 422
 423 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 424
 425         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 426         * i386-init.h: Regenerated.
 427
 428 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 429
 430         * opcodes/arc-dis.c (print_insn_arc): Changed.
 431
 432 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 433
 434         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 435         camellia_fl.
 436
 437 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 438
 439         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 440         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 441         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 442
 443 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 446         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 447         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 448         PREFIX_MOD_3_0FAE_REG_4.
 449         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 450         PREFIX_MOD_3_0FAE_REG_4.
 451         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 452         (cpu_flags): Add CpuPTWRITE.
 453         * i386-opc.h (CpuPTWRITE): New.
 454         (i386_cpu_flags): Add cpuptwrite.
 455         * i386-opc.tbl: Add ptwrite instruction.
 456         * i386-init.h: Regenerated.
 457         * i386-tbl.h: Likewise.
 458
 459 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 460
 461         * arc-dis.h: Wrap around in extern "C".
 462
 463 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 464
 465         * aarch64-tbl.h (V8_2_INSN): New macro.
 466         (aarch64_opcode_table): Use it.
 467
 468 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 469
 470         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 471         CORE_INSN, __FP_INSN and SIMD_INSN.
 472
 473 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 474
 475         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 476         (aarch64_opcode_table): Update uses accordingly.
 477
 478 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 479         Kwok Cheung Yeung  <kcy@codesourcery.com>
 480
 481         opcodes/
 482         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 483         'e_cmplwi' to 'e_cmpli' instead.
 484         (OPVUPRT, OPVUPRT_MASK): Define.
 485         (powerpc_opcodes): Add E200Z4 insns.
 486         (vle_opcodes): Add context save/restore insns.
 487
 488 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 489
 490         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 491         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 492         "j".
 493
 494 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 495
 496         * arc-nps400-tbl.h: Change block comments to GNU format.
 497         * arc-dis.c: Add new globals addrtypenames,
 498         addrtypenames_max, and addtypeunknown.
 499         (get_addrtype): New function.
 500         (print_insn_arc): Print colons and address types when
 501         required.
 502         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 503         define insert and extract functions for all address types.
 504         (arc_operands): Add operands for colon and all address
 505         types.
 506         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 507         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 508         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 509         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 510         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 511         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 512
 513 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 514
 515         * configure: Regenerated.
 516
 517 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 518
 519         * arc-dis.c (skipclass): New structure.
 520         (decodelist): New variable.
 521         (is_compatible_p): New function.
 522         (new_element): Likewise.
 523         (skip_class_p): Likewise.
 524         (find_format_from_table): Use skip_class_p function.
 525         (find_format): Decode first the extension instructions.
 526         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 527         e_flags.
 528         (parse_option): New function.
 529         (parse_disassembler_options): Likewise.
 530         (print_arc_disassembler_options): Likewise.
 531         (print_insn_arc): Use parse_disassembler_options function.  Proper
 532         select ARCv2 cpu variant.
 533         * disassemble.c (disassembler_usage): Add ARC disassembler
 534         options.
 535
 536 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 537
 538         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 539         annotation from the "nal" entry and reorder it beyond "bltzal".
 540
 541 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 542
 543         * sparc-opc.c (ldtxa): New macro.
 544         (sparc_opcodes): Use the macro defined above to add entries for
 545         the LDTXA instructions.
 546         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 547         instruction.
 548
 549 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 550
 551         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 552         and "jmpc".
 553
 554 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 557         (movzb): Adjust to cover all permitted suffixes.
 558         (movzw): New.
 559         * i386-tbl.h: Re-generate.
 560
 561 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 562
 563         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 564         (lgdt): Remove Tbyte from non-64-bit variant.
 565         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 566         xsaves64, xsavec64): Remove Disp16.
 567         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 568         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 569         64-bit variants.
 570         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 571         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 572         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 573         64-bit variants.
 574         * i386-tbl.h: Re-generate.
 575
 576 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 577
 578         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 579         * i386-tbl.h: Re-generate.
 580
 581 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 582
 583         * arm-dis.c (print_insn): Fix typo in comment.
 584
 585 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 586
 587         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 588         range of ldst_elemlist operands.
 589         (print_register_list): Use PRIi64 to print the index.
 590         (aarch64_print_operand): Likewise.
 591
 592 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 593
 594         * mcore-opc.h: Remove sentinal.
 595         * mcore-dis.c (print_insn_mcore): Adjust.
 596
 597 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 598
 599         * arc-opc.c: Correct description of availability of NPS400
 600         features.
 601
 602 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 603
 604         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 605         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 606         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 607         xor3>: New mnemonics.
 608         <setb>: Change to a VX form instruction.
 609         (insert_sh6): Add support for rldixor.
 610         (extract_sh6): Likewise.
 611
 612 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 613
 614         * arc-ext.h: Wrap in extern C.
 615
 616 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 617
 618         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 619         Use same method for determining instruction length on ARC700 and
 620         NPS-400.
 621         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 622         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 623         with the NPS400 subclass.
 624         * arc-opc.c: Likewise.
 625
 626 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 627
 628         * sparc-opc.c (rdasr): New macro.
 629         (wrasr): Likewise.
 630         (rdpr): Likewise.
 631         (wrpr): Likewise.
 632         (rdhpr): Likewise.
 633         (wrhpr): Likewise.
 634         (sparc_opcodes): Use the macros above to fix and expand the
 635         definition of read/write instructions from/to
 636         asr/privileged/hyperprivileged instructions.
 637         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 638         %hva_mask_nz.  Prefer softint_set and softint_clear over
 639         set_softint and clear_softint.
 640         (print_insn_sparc): Support %ver in Rd.
 641
 642 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 643
 644         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 645         architecture according to the hardware capabilities they require.
 646
 647 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 648
 649         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 650         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 651         bfd_mach_sparc_v9{c,d,e,v,m}.
 652         * sparc-opc.c (MASK_V9C): Define.
 653         (MASK_V9D): Likewise.
 654         (MASK_V9E): Likewise.
 655         (MASK_V9V): Likewise.
 656         (MASK_V9M): Likewise.
 657         (v6): Add MASK_V9{C,D,E,V,M}.
 658         (v6notlet): Likewise.
 659         (v7): Likewise.
 660         (v8): Likewise.
 661         (v9): Likewise.
 662         (v9andleon): Likewise.
 663         (v9a): Likewise.
 664         (v9b): Likewise.
 665         (v9c): Define.
 666         (v9d): Likewise.
 667         (v9e): Likewise.
 668         (v9v): Likewise.
 669         (v9m): Likewise.
 670         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 671
 672 2016-06-15  Nick Clifton  <nickc@redhat.com>
 673
 674         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 675         constants to match expected behaviour.
 676         (nds32_parse_opcode): Likewise.  Also for whitespace.
 677
 678 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 679
 680         * arc-opc.c (extract_rhv1): Extract value from insn.
 681
 682 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 683
 684         * arc-nps400-tbl.h: Add ldbit instruction.
 685         * arc-opc.c: Add flag classes required for ldbit.
 686
 687 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 688
 689         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 690         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 691         support the above instructions.
 692
 693 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 694
 695         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 696         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 697         csma, cbba, zncv, and hofs.
 698         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 699         support the above instructions.
 700
 701 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 702
 703         * arc-nps400-tbl.h: Add andab and orab instructions.
 704
 705 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 706
 707         * arc-nps400-tbl.h: Add addl-like instructions.
 708
 709 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 710
 711         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 712
 713 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 714
 715         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 716         instructions.
 717
 718 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 719
 720         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 721         variable.
 722         (init_disasm): Handle new command line option "insnlength".
 723         (print_s390_disassembler_options): Mention new option in help
 724         output.
 725         (print_insn_s390): Use the encoded insn length when dumping
 726         unknown instructions.
 727
 728 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 729
 730         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 731          to the address and set as symbol address for LDS/ STS immediate operands.
 732
 733 2016-06-07  Alan Modra  <amodra@gmail.com>
 734
 735         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 736         cpu for "vle" to e500.
 737         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 738         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 739         (PPCNONE): Delete, substitute throughout.
 740         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 741         except for major opcode 4 and 31.
 742         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 743
 744 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 745
 746         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 747         ARM_EXT_RAS in relevant entries.
 748
 749 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 750
 751         PR binutils/20196
 752         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 753         opcodes for E6500.
 754
 755 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 756
 757         PR binutis/18386
 758         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 759         (indir_v_mode): New.
 760         Add comments for '&'.
 761         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 762         (putop): Handle '&'.
 763         (intel_operand_size): Handle indir_v_mode.
 764         (OP_E_register): Likewise.
 765         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 766         64-bit indirect call/jmp for AMD64.
 767         * i386-tbl.h: Regenerated
 768
 769 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 770
 771         * arc-dis.c (struct arc_operand_iterator): New structure.
 772         (find_format_from_table): All the old content from find_format,
 773         with some minor adjustments, and parameter renaming.
 774         (find_format_long_instructions): New function.
 775         (find_format): Rewritten.
 776         (arc_insn_length): Add LSB parameter.
 777         (extract_operand_value): New function.
 778         (operand_iterator_next): New function.
 779         (print_insn_arc): Use new functions to find opcode, and iterator
 780         over operands.
 781         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 782         (extract_nps_3bit_dst_short): New function.
 783         (insert_nps_3bit_src2_short): New function.
 784         (extract_nps_3bit_src2_short): New function.
 785         (insert_nps_bitop1_size): New function.
 786         (extract_nps_bitop1_size): New function.
 787         (insert_nps_bitop2_size): New function.
 788         (extract_nps_bitop2_size): New function.
 789         (insert_nps_bitop_mod4_msb): New function.
 790         (extract_nps_bitop_mod4_msb): New function.
 791         (insert_nps_bitop_mod4_lsb): New function.
 792         (extract_nps_bitop_mod4_lsb): New function.
 793         (insert_nps_bitop_dst_pos3_pos4): New function.
 794         (extract_nps_bitop_dst_pos3_pos4): New function.
 795         (insert_nps_bitop_ins_ext): New function.
 796         (extract_nps_bitop_ins_ext): New function.
 797         (arc_operands): Add new operands.
 798         (arc_long_opcodes): New global array.
 799         (arc_num_long_opcodes): New global.
 800         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 801
 802 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 803
 804         * nds32-asm.h: Add extern "C".
 805         * sh-opc.h: Likewise.
 806
 807 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 808
 809         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 810         0,b,limm to the rflt instruction.
 811
 812 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 813
 814         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 815         constant.
 816
 817 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 818
 819         PR gas/20145
 820         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 821         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 822         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 823         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 824         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 825         * i386-init.h: Regenerated.
 826
 827 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 828
 829         PR gas/20145
 830         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 831         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 832         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 833         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 834         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 835         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 836         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 837         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 838         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 839         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 840         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 841         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 842         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 843         CpuRegMask for AVX512.
 844         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 845         and CpuRegMask.
 846         (set_bitfield_from_cpu_flag_init): New function.
 847         (set_bitfield): Remove const on f.  Call
 848         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 849         * i386-opc.h (CpuRegMMX): New.
 850         (CpuRegXMM): Likewise.
 851         (CpuRegYMM): Likewise.
 852         (CpuRegZMM): Likewise.
 853         (CpuRegMask): Likewise.
 854         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 855         and cpuregmask.
 856         * i386-init.h: Regenerated.
 857         * i386-tbl.h: Likewise.
 858
 859 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 860
 861         PR gas/20154
 862         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 863         (opcode_modifiers): Add AMD64 and Intel64.
 864         (main): Properly verify CpuMax.
 865         * i386-opc.h (CpuAMD64): Removed.
 866         (CpuIntel64): Likewise.
 867         (CpuMax): Set to CpuNo64.
 868         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 869         (AMD64): New.
 870         (Intel64): Likewise.
 871         (i386_opcode_modifier): Add amd64 and intel64.
 872         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 873         on call and jmp.
 874         * i386-init.h: Regenerated.
 875         * i386-tbl.h: Likewise.
 876
 877 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 878
 879         PR gas/20154
 880         * i386-gen.c (main): Fail if CpuMax is incorrect.
 881         * i386-opc.h (CpuMax): Set to CpuIntel64.
 882         * i386-tbl.h: Regenerated.
 883
 884 2016-05-27  Nick Clifton  <nickc@redhat.com>
 885
 886         PR target/20150
 887         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 888         (msp430dis_opcode_unsigned): New function.
 889         (msp430dis_opcode_signed): New function.
 890         (msp430_singleoperand): Use the new opcode reading functions.
 891         Only disassenmble bytes if they were successfully read.
 892         (msp430_doubleoperand): Likewise.
 893         (msp430_branchinstr): Likewise.
 894         (msp430x_callx_instr): Likewise.
 895         (print_insn_msp430): Check that it is safe to read bytes before
 896         attempting disassembly.  Use the new opcode reading functions.
 897
 898 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 899
 900         * ppc-opc.c (CY): New define.  Document it.
 901         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 902
 903 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 904
 905         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 906         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 907         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 908         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 909         CPU_ANY_AVX_FLAGS.
 910         * i386-init.h: Regenerated.
 911
 912 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 913
 914         PR gas/20141
 915         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 916         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 917         * i386-init.h: Regenerated.
 918
 919 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 920
 921         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 922         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 923         * i386-init.h: Regenerated.
 924
 925 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 926
 927         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 928         information.
 929         (print_insn_arc): Set insn_type information.
 930         * arc-opc.c (C_CC): Add F_CLASS_COND.
 931         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 932         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 933         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 934         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 935         (brne, brne_s, jeq_s, jne_s): Likewise.
 936
 937 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 938
 939         * arc-tbl.h (neg): New instruction variant.
 940
 941 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 942
 943         * arc-dis.c (find_format, find_format, get_auxreg)
 944         (print_insn_arc): Changed.
 945         * arc-ext.h (INSERT_XOP): Likewise.
 946
 947 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 948
 949         * tic54x-dis.c (sprint_mmr): Adjust.
 950         * tic54x-opc.c: Likewise.
 951
 952 2016-05-19  Alan Modra  <amodra@gmail.com>
 953
 954         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 955
 956 2016-05-19  Alan Modra  <amodra@gmail.com>
 957
 958         * ppc-opc.c: Formatting.
 959         (NSISIGNOPT): Define.
 960         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 961
 962 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 963
 964         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 965         replacing references to `micromips_ase' throughout.
 966         (_print_insn_mips): Don't use file-level microMIPS annotation to
 967         determine the disassembly mode with the symbol table.
 968
 969 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 970
 971         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 972
 973 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 974
 975         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 976         mips64r6.
 977         * mips-opc.c (D34): New macro.
 978         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 979
 980 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 981
 982         * i386-dis.c (prefix_table): Add RDPID instruction.
 983         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 984         (cpu_flags): Add RDPID bitfield.
 985         * i386-opc.h (enum): Add RDPID element.
 986         (i386_cpu_flags): Add RDPID field.
 987         * i386-opc.tbl: Add RDPID instruction.
 988         * i386-init.h: Regenerate.
 989         * i386-tbl.h: Regenerate.
 990
 991 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 992
 993         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 994         branch type of a symbol.
 995         (print_insn): Likewise.
 996
 997 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 998
 999         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1000         Mainline Security Extensions instructions.
1001         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1002         Extensions instructions.
1003         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1004         instructions.
1005         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1006         special registers.
1007
1008 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1009
1010         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1011
1012 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1013
1014         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1015         (arcExtMap_genOpcode): Likewise.
1016         * arc-opc.c (arg_32bit_rc): Define new variable.
1017         (arg_32bit_u6): Likewise.
1018         (arg_32bit_limm): Likewise.
1019
1020 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1021
1022         * aarch64-gen.c (VERIFIER): Define.
1023         * aarch64-opc.c (VERIFIER): Define.
1024         (verify_ldpsw): Use static linkage.
1025         * aarch64-opc.h (verify_ldpsw): Remove.
1026         * aarch64-tbl.h: Use VERIFIER for verifiers.
1027
1028 2016-04-28  Nick Clifton  <nickc@redhat.com>
1029
1030         PR target/19722
1031         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1032         * aarch64-opc.c (verify_ldpsw): New function.
1033         * aarch64-opc.h (verify_ldpsw): New prototype.
1034         * aarch64-tbl.h: Add initialiser for verifier field.
1035         (LDPSW): Set verifier to verify_ldpsw.
1036
1037 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1038
1039         PR binutils/19983
1040         PR binutils/19984
1041         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1042         smaller than address size.
1043
1044 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1045
1046         * alpha-dis.c: Regenerate.
1047         * crx-dis.c: Likewise.
1048         * disassemble.c: Likewise.
1049         * epiphany-opc.c: Likewise.
1050         * fr30-opc.c: Likewise.
1051         * frv-opc.c: Likewise.
1052         * ip2k-opc.c: Likewise.
1053         * iq2000-opc.c: Likewise.
1054         * lm32-opc.c: Likewise.
1055         * lm32-opinst.c: Likewise.
1056         * m32c-opc.c: Likewise.
1057         * m32r-opc.c: Likewise.
1058         * m32r-opinst.c: Likewise.
1059         * mep-opc.c: Likewise.
1060         * mt-opc.c: Likewise.
1061         * or1k-opc.c: Likewise.
1062         * or1k-opinst.c: Likewise.
1063         * tic80-opc.c: Likewise.
1064         * xc16x-opc.c: Likewise.
1065         * xstormy16-opc.c: Likewise.
1066
1067 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1068
1069         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1070         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1071         calcsd, and calcxd instructions.
1072         * arc-opc.c (insert_nps_bitop_size): Delete.
1073         (extract_nps_bitop_size): Delete.
1074         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1075         (extract_nps_qcmp_m3): Define.
1076         (extract_nps_qcmp_m2): Define.
1077         (extract_nps_qcmp_m1): Define.
1078         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1079         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1080         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1081         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1082         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1083         NPS_QCMP_M3.
1084
1085 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1086
1087         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1088
1089 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1090
1091         * Makefile.in: Regenerated with automake 1.11.6.
1092         * aclocal.m4: Likewise.
1093
1094 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1095
1096         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1097         instructions.
1098         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1099         (extract_nps_cmem_uimm16): New function.
1100         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1101
1102 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1103
1104         * arc-dis.c (arc_insn_length): New function.
1105         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1106         (find_format): Change insnLen parameter to unsigned.
1107
1108 2016-04-13  Nick Clifton  <nickc@redhat.com>
1109
1110         PR target/19937
1111         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1112         the LD.B and LD.BU instructions.
1113
1114 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1115
1116         * arc-dis.c (find_format): Check for extension flags.
1117         (print_flags): New function.
1118         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1119         .extAuxRegister.
1120         * arc-ext.c (arcExtMap_coreRegName): Use
1121         LAST_EXTENSION_CORE_REGISTER.
1122         (arcExtMap_coreReadWrite): Likewise.
1123         (dump_ARC_extmap): Update printing.
1124         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1125         (arc_aux_regs): Add cpu field.
1126         * arc-regs.h: Add cpu field, lower case name aux registers.
1127
1128 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1129
1130         * arc-tbl.h: Add rtsc, sleep with no arguments.
1131
1132 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1133
1134         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1135         Initialize.
1136         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1137         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1138         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1139         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1140         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1141         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1142         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1143         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1144         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1145         (arc_opcode arc_opcodes): Null terminate the array.
1146         (arc_num_opcodes): Remove.
1147         * arc-ext.h (INSERT_XOP): Define.
1148         (extInstruction_t): Likewise.
1149         (arcExtMap_instName): Delete.
1150         (arcExtMap_insn): New function.
1151         (arcExtMap_genOpcode): Likewise.
1152         * arc-ext.c (ExtInstruction): Remove.
1153         (create_map): Zero initialize instruction fields.
1154         (arcExtMap_instName): Remove.
1155         (arcExtMap_insn): New function.
1156         (dump_ARC_extmap): More info while debuging.
1157         (arcExtMap_genOpcode): New function.
1158         * arc-dis.c (find_format): New function.
1159         (print_insn_arc): Use find_format.
1160         (arc_get_disassembler): Enable dump_ARC_extmap only when
1161         debugging.
1162
1163 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1164
1165         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1166         instruction bits out.
1167
1168 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1169
1170         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1171         * arc-opc.c (arc_flag_operands): Add new flags.
1172         (arc_flag_classes): Add new classes.
1173
1174 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1175
1176         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1177
1178 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1179
1180         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1181         encode1, rflt, crc16, and crc32 instructions.
1182         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1183         (arc_flag_classes): Add C_NPS_R.
1184         (insert_nps_bitop_size_2b): New function.
1185         (extract_nps_bitop_size_2b): Likewise.
1186         (insert_nps_bitop_uimm8): Likewise.
1187         (extract_nps_bitop_uimm8): Likewise.
1188         (arc_operands): Add new operand entries.
1189
1190 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1191
1192         * arc-regs.h: Add a new subclass field.  Add double assist
1193         accumulator register values.
1194         * arc-tbl.h: Use DPA subclass to mark the double assist
1195         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1196         * arc-opc.c (RSP): Define instead of SP.
1197         (arc_aux_regs): Add the subclass field.
1198
1199 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1200
1201         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1202
1203 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1204
1205         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1206         NPS_R_SRC1.
1207
1208 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1209
1210         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1211         issues.  No functional changes.
1212
1213 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1214
1215         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1216         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1217         (RTT): Remove duplicate.
1218         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1219         (PCT_CONFIG*): Remove.
1220         (D1L, D1H, D2H, D2L): Define.
1221
1222 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1223
1224         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1225
1226 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1227
1228         * arc-tbl.h (invld07): Remove.
1229         * arc-ext-tbl.h: New file.
1230         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1231         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1232
1233 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1234
1235         Fix -Wstack-usage warnings.
1236         * aarch64-dis.c (print_operands): Substitute size.
1237         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1238
1239 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1240
1241         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1242         to get a proper diagnostic when an invalid ASR register is used.
1243
1244 2016-03-22  Nick Clifton  <nickc@redhat.com>
1245
1246         * configure: Regenerate.
1247
1248 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1249
1250         * arc-nps400-tbl.h: New file.
1251         * arc-opc.c: Add top level comment.
1252         (insert_nps_3bit_dst): New function.
1253         (extract_nps_3bit_dst): New function.
1254         (insert_nps_3bit_src2): New function.
1255         (extract_nps_3bit_src2): New function.
1256         (insert_nps_bitop_size): New function.
1257         (extract_nps_bitop_size): New function.
1258         (arc_flag_operands): Add nps400 entries.
1259         (arc_flag_classes): Add nps400 entries.
1260         (arc_operands): Add nps400 entries.
1261         (arc_opcodes): Add nps400 include.
1262
1263 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1264
1265         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1266         the new class enum values.
1267
1268 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1269
1270         * arc-dis.c (print_insn_arc): Handle nps400.
1271
1272 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1273
1274         * arc-opc.c (BASE): Delete.
1275
1276 2016-03-18  Nick Clifton  <nickc@redhat.com>
1277
1278         PR target/19721
1279         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1280         of MOV insn that aliases an ORR insn.
1281
1282 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1283
1284         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1285
1286 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1287
1288         * mcore-opc.h: Add const qualifiers.
1289         * microblaze-opc.h (struct op_code_struct): Likewise.
1290         * sh-opc.h: Likewise.
1291         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1292         (tic4x_print_op): Likewise.
1293
1294 2016-03-02  Alan Modra  <amodra@gmail.com>
1295
1296         * or1k-desc.h: Regenerate.
1297         * fr30-ibld.c: Regenerate.
1298         * rl78-decode.c: Regenerate.
1299
1300 2016-03-01  Nick Clifton  <nickc@redhat.com>
1301
1302         PR target/19747
1303         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1304
1305 2016-02-24  Renlin Li  <renlin.li@arm.com>
1306
1307         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1308         (print_insn_coprocessor): Support fp16 instructions.
1309
1310 2016-02-24  Renlin Li  <renlin.li@arm.com>
1311
1312         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1313         vminnm, vrint(mpna).
1314
1315 2016-02-24  Renlin Li  <renlin.li@arm.com>
1316
1317         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1318         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1319
1320 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1321
1322         * i386-dis.c (print_insn): Parenthesize expression to prevent
1323         truncated addresses.
1324         (OP_J): Likewise.
1325
1326 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1327             Janek van Oirschot  <jvanoirs@synopsys.com>
1328
1329         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1330         variable.
1331
1332 2016-02-04  Nick Clifton  <nickc@redhat.com>
1333
1334         PR target/19561
1335         * msp430-dis.c (print_insn_msp430): Add a special case for
1336         decoding an RRC instruction with the ZC bit set in the extension
1337         word.
1338
1339 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1340
1341         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1342         * epiphany-ibld.c: Regenerate.
1343         * fr30-ibld.c: Regenerate.
1344         * frv-ibld.c: Regenerate.
1345         * ip2k-ibld.c: Regenerate.
1346         * iq2000-ibld.c: Regenerate.
1347         * lm32-ibld.c: Regenerate.
1348         * m32c-ibld.c: Regenerate.
1349         * m32r-ibld.c: Regenerate.
1350         * mep-ibld.c: Regenerate.
1351         * mt-ibld.c: Regenerate.
1352         * or1k-ibld.c: Regenerate.
1353         * xc16x-ibld.c: Regenerate.
1354         * xstormy16-ibld.c: Regenerate.
1355
1356 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1357
1358         * epiphany-dis.c: Regenerated from latest cpu files.
1359
1360 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1361
1362         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1363         test bit.
1364
1365 2016-01-25  Renlin Li  <renlin.li@arm.com>
1366
1367         * arm-dis.c (mapping_symbol_for_insn): New function.
1368         (find_ifthen_state): Call mapping_symbol_for_insn().
1369
1370 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1371
1372         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1373         of MSR UAO immediate operand.
1374
1375 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1376
1377         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1378         instruction support.
1379
1380 2016-01-17  Alan Modra  <amodra@gmail.com>
1381
1382         * configure: Regenerate.
1383
1384 2016-01-14  Nick Clifton  <nickc@redhat.com>
1385
1386         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1387         instructions that can support stack pointer operations.
1388         * rl78-decode.c: Regenerate.
1389         * rl78-dis.c: Fix display of stack pointer in MOVW based
1390         instructions.
1391
1392 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1393
1394         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1395         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1396         erxtatus_el1 and erxaddr_el1.
1397
1398 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1399
1400         * arm-dis.c (arm_opcodes): Add "esb".
1401         (thumb_opcodes): Likewise.
1402
1403 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1404
1405         * ppc-opc.c <xscmpnedp>: Delete.
1406         <xvcmpnedp>: Likewise.
1407         <xvcmpnedp.>: Likewise.
1408         <xvcmpnesp>: Likewise.
1409         <xvcmpnesp.>: Likewise.
1410
1411 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1412
1413         PR gas/13050
1414         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1415         addition to ISA_A.
1416
1417 2016-01-01  Alan Modra  <amodra@gmail.com>
1418
1419         Update year range in copyright notice of all files.
1420
1421 For older changes see ChangeLog-2015
1422 \f
1423 Copyright (C) 2016 Free Software Foundation, Inc.
1424
1425 Copying and distribution of this file, with or without modification,
1426 are permitted in any medium without royalty provided the copyright
1427 notice and this notice are preserved.
1428
1429 Local Variables:
1430 mode: change-log
1431 left-margin: 8
1432 fill-column: 74
1433 version-control: never
1434 End: