1 2017-11-16 Tamar Christina <tamar.christina@arm.com>
3 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
4 and AARCH64_FEATURE_F16.
6 2017-11-16 Tamar Christina <tamar.christina@arm.com>
8 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
9 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
10 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
11 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
12 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
13 (ldapur, ldapursw, stlur): New.
14 * aarch64-dis-2.c: Regenerate.
16 2017-11-16 Jan Beulich <jbeulich@suse.com>
18 (get_valid_dis386): Never flag bad opcode when
19 vex.register_specifier is beyond 7. Always store all four
20 bits of it. Move 16-/32-bit override in EVEX handling after
21 all to be overridden bits have been set.
22 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
23 Use rex to determine GPR register set.
24 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
25 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
27 2017-11-15 Jan Beulich <jbeulich@suse.com>
29 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
30 determine GPR register set.
32 2017-11-15 Jan Beulich <jbeulich@suse.com>
34 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
35 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
36 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
38 (OP_REG_VexI4): Drop low 4 bits check.
40 2017-11-15 Jan Beulich <jbeulich@suse.com>
42 * i386-reg.tbl (axl): Remove Acc and Byte.
43 * i386-tbl.h: Re-generate.
45 2017-11-14 Jan Beulich <jbeulich@suse.com>
47 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
48 (vex_len_table): Use VPCOM.
50 2017-11-14 Jan Beulich <jbeulich@suse.com>
52 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
53 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
54 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
56 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
57 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
58 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
59 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
61 * i386-tbl.h: Re-generate.
63 2017-11-14 Jan Beulich <jbeulich@suse.com>
65 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
66 smov, ssca, stos, ssto, xlat): Drop Disp*.
67 * i386-tbl.h: Re-generate.
69 2017-11-13 Jan Beulich <jbeulich@suse.com>
71 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
72 xsaveopt64): Add No_qSuf.
73 * i386-tbl.h: Re-generate.
75 2017-11-09 Tamar Christina <tamar.christina@arm.com>
77 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
78 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
79 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
81 (aarch64_sys_reg_supported_p): Likewise.
82 (aarch64_pstatefields): Add dit register.
83 (aarch64_pstatefield_supported_p): Likewise.
84 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
85 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
86 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
87 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
88 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
89 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
90 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
92 2017-11-09 Tamar Christina <tamar.christina@arm.com>
94 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
95 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
96 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
97 (QL_STLW, QL_STLX): New.
99 2017-11-09 Tamar Christina <tamar.christina@arm.com>
101 * aarch64-asm.h (ins_addr_offset): New.
102 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
103 (aarch64_ins_addr_offset): New.
104 * aarch64-asm-2.c: Regenerate.
105 * aarch64-dis.h (ext_addr_offset): New.
106 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
107 (aarch64_ext_addr_offset): New.
108 * aarch64-dis-2.c: Regenerate.
109 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
110 FLD_imm4_2 and FLD_SM3_imm2.
111 * aarch64-opc.c (fields): Add FLD_imm6_2,
112 FLD_imm4_2 and FLD_SM3_imm2.
113 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
114 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
115 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
116 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
118 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
120 2017-11-09 Tamar Christina <tamar.christina@arm.com>
123 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
124 (aarch64_feature_sm4, aarch64_feature_sha3): New.
125 (aarch64_feature_fp_16_v8_2): New.
126 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
127 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
128 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
130 2017-11-08 Tamar Christina <tamar.christina@arm.com>
132 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
133 (aarch64_feature_sha2, aarch64_feature_aes): New.
135 (AES_INSN, SHA2_INSN): New.
136 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
137 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
138 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
141 2017-11-08 Jiong Wang <jiong.wang@arm.com>
142 Tamar Christina <tamar.christina@arm.com>
144 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
145 FP16 instructions, including vfmal.f16 and vfmsl.f16.
147 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
149 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
151 2017-11-07 Alan Modra <amodra@gmail.com>
153 * opintl.h: Formatting, comment fixes.
154 (gettext, ngettext): Redefine when ENABLE_NLS.
155 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
156 (_): Define using gettext.
157 (textdomain, bindtextdomain): Use safer "do nothing".
159 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
161 * arc-dis.c (print_hex): New variable.
162 (parse_option): Check for hex option.
163 (print_insn_arc): Use hexadecimal representation for short
164 immediate values when requested.
165 (print_arc_disassembler_options): Add hex option to the list.
167 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
169 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
170 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
171 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
172 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
173 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
174 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
175 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
176 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
177 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
178 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
179 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
180 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
181 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
182 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
183 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
184 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
185 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
186 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
187 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
189 (prealloc, prefetch*): Place them before ld instruction.
190 * arc-opc.c (skip_this_opcode): Add ARITH class.
192 2017-10-25 Alan Modra <amodra@gmail.com>
195 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
196 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
197 (imm4flag, size_changed): Likewise.
198 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
199 (words, allWords, processing_argument_number): Likewise.
200 (cst4flag, size_changed): Likewise.
201 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
202 (crx_cst4_maps): Rename from cst4_maps.
203 (crx_no_op_insn): Rename from no_op_insn.
205 2017-10-24 Andrew Waterman <andrew@sifive.com>
207 * riscv-opc.c (match_c_addi16sp) : New function.
208 (match_c_addi4spn): New function.
209 (match_c_lui): Don't allow 0-immediate encodings.
210 (riscv_opcodes) <addi>: Use the above functions.
212 <c.addi4spn>: Likewise.
213 <c.addi16sp>: Likewise.
215 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
217 * i386-init.h: Regenerate
218 * i386-tbl.h: Likewise
220 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
222 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
223 (enum): Add EVEX_W_0F3854_P_2.
224 * i386-dis-evex.h (evex_table): Updated.
225 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
226 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
227 (cpu_flags): Add CpuAVX512_BITALG.
228 * i386-opc.h (enum): Add CpuAVX512_BITALG.
229 (i386_cpu_flags): Add cpuavx512_bitalg..
230 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
231 * i386-init.h: Regenerate.
232 * i386-tbl.h: Likewise.
234 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
236 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
237 * i386-dis-evex.h (evex_table): Updated.
238 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
239 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
240 (cpu_flags): Add CpuAVX512_VNNI.
241 * i386-opc.h (enum): Add CpuAVX512_VNNI.
242 (i386_cpu_flags): Add cpuavx512_vnni.
243 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
244 * i386-init.h: Regenerate.
245 * i386-tbl.h: Likewise.
247 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
249 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
250 (enum): Remove VEX_LEN_0F3A44_P_2.
251 (vex_len_table): Ditto.
252 (enum): Remove VEX_W_0F3A44_P_2.
253 (vew_w_table): Ditto.
254 (prefix_table): Adjust instructions (see prefixes above).
255 * i386-dis-evex.h (evex_table):
256 Add new instructions (see prefixes above).
257 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
258 (bitfield_cpu_flags): Ditto.
259 * i386-opc.h (enum): Ditto.
260 (i386_cpu_flags): Ditto.
261 (CpuUnused): Comment out to avoid zero-width field problem.
262 * i386-opc.tbl (vpclmulqdq): New instruction.
263 * i386-init.h: Regenerate.
266 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
268 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
269 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
270 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
271 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
272 (vex_len_table): Ditto.
273 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
274 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
275 (vew_w_table): Ditto.
276 (prefix_table): Adjust instructions (see prefixes above).
277 * i386-dis-evex.h (evex_table):
278 Add new instructions (see prefixes above).
279 * i386-gen.c (cpu_flag_init): Add VAES.
280 (bitfield_cpu_flags): Ditto.
281 * i386-opc.h (enum): Ditto.
282 (i386_cpu_flags): Ditto.
283 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
284 * i386-init.h: Regenerate.
287 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
289 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
290 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
291 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
292 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
293 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
294 (prefix_table): Updated (see prefixes above).
295 (three_byte_table): Likewise.
296 (vex_w_table): Likewise.
297 * i386-dis-evex.h: Likewise.
298 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
299 (cpu_flags): Add CpuGFNI.
300 * i386-opc.h (enum): Add CpuGFNI.
301 (i386_cpu_flags): Add cpugfni.
302 * i386-opc.tbl: Add Intel GFNI instructions.
303 * i386-init.h: Regenerate.
304 * i386-tbl.h: Likewise.
306 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
308 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
309 Define EXbScalar and EXwScalar for OP_EX.
310 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
311 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
312 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
313 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
314 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
315 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
316 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
317 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
318 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
319 (OP_E_memory): Likewise.
320 * i386-dis-evex.h: Updated.
321 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
322 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
323 (cpu_flags): Add CpuAVX512_VBMI2.
324 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
325 (i386_cpu_flags): Add cpuavx512_vbmi2.
326 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
327 * i386-init.h: Regenerate.
328 * i386-tbl.h: Likewise.
330 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
332 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
334 2017-10-12 James Bowman <james.bowman@ftdichip.com>
336 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
337 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
338 K15. Add jmpix pattern.
340 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
342 * s390-opc.txt (prno, tpei, irbm): New instructions added.
344 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
346 * s390-opc.c (INSTR_SI_RD): New macro.
347 (INSTR_S_RD): Adjust example instruction.
348 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
351 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
353 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
354 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
355 VLE multimple load/store instructions. Old e_ldm* variants are
357 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
359 2017-09-27 Nick Clifton <nickc@redhat.com>
362 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
363 names for the fmv.x.s and fmv.s.x instructions respectively.
365 2017-09-26 do <do@nerilex.org>
368 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
369 be used on CPUs that have emacs support.
371 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
373 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
375 2017-09-09 Kamil Rytarowski <n54@gmx.com>
377 * nds32-asm.c: Rename __BIT() to N32_BIT().
378 * nds32-asm.h: Likewise.
379 * nds32-dis.c: Likewise.
381 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
383 * i386-dis.c (last_active_prefix): Removed.
384 (ckprefix): Don't set last_active_prefix.
385 (NOTRACK_Fixup): Don't check last_active_prefix.
387 2017-08-31 Nick Clifton <nickc@redhat.com>
389 * po/fr.po: Updated French translation.
391 2017-08-31 James Bowman <james.bowman@ftdichip.com>
393 * ft32-dis.c (print_insn_ft32): Correct display of non-address
396 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
397 Edmar Wienskoski <edmar.wienskoski@nxp.com>
399 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
400 PPC_OPCODE_EFS2 flag to "e200z4" entry.
401 New entries efs2 and spe2.
402 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
403 (SPE2_OPCD_SEGS): New macro.
404 (spe2_opcd_indices): New.
405 (disassemble_init_powerpc): Handle SPE2 opcodes.
406 (lookup_spe2): New function.
407 (print_insn_powerpc): call lookup_spe2.
408 * ppc-opc.c (insert_evuimm1_ex0): New function.
409 (extract_evuimm1_ex0): Likewise.
410 (insert_evuimm_lt8): Likewise.
411 (extract_evuimm_lt8): Likewise.
412 (insert_off_spe2): Likewise.
413 (extract_off_spe2): Likewise.
414 (insert_Ddd): Likewise.
415 (extract_Ddd): Likewise.
417 (EVUIMM_LT8): Likewise.
418 (EVUIMM_LT16): Adjust.
420 (EVUIMM_1): Likewise.
421 (EVUIMM_1_EX0): Likewise.
424 (VX_OFF_SPE2): Likewise.
427 (VX_MASK_DDD): New mask.
429 (VX_RA_CONST): New macro.
430 (VX_RA_CONST_MASK): Likewise.
431 (VX_RB_CONST): Likewise.
432 (VX_RB_CONST_MASK): Likewise.
433 (VX_OFF_SPE2_MASK): Likewise.
434 (VX_SPE_CRFD): Likewise.
435 (VX_SPE_CRFD_MASK VX): Likewise.
436 (VX_SPE2_CLR): Likewise.
437 (VX_SPE2_CLR_MASK): Likewise.
438 (VX_SPE2_SPLATB): Likewise.
439 (VX_SPE2_SPLATB_MASK): Likewise.
440 (VX_SPE2_OCTET): Likewise.
441 (VX_SPE2_OCTET_MASK): Likewise.
442 (VX_SPE2_DDHH): Likewise.
443 (VX_SPE2_DDHH_MASK): Likewise.
444 (VX_SPE2_HH): Likewise.
445 (VX_SPE2_HH_MASK): Likewise.
446 (VX_SPE2_EVMAR): Likewise.
447 (VX_SPE2_EVMAR_MASK): Likewise.
450 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
451 (powerpc_macros): Map old SPE instructions have new names
452 with the same opcodes. Add SPE2 instructions which just are
454 (spe2_opcodes): Add SPE2 opcodes.
456 2017-08-23 Alan Modra <amodra@gmail.com>
458 * ppc-opc.c: Formatting and comment fixes. Move insert and
459 extract functions earlier, deleting forward declarations.
460 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
463 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
465 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
467 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
468 Edmar Wienskoski <edmar.wienskoski@nxp.com>
470 * ppc-opc.c (insert_evuimm2_ex0): New function.
471 (extract_evuimm2_ex0): Likewise.
472 (insert_evuimm4_ex0): Likewise.
473 (extract_evuimm4_ex0): Likewise.
474 (insert_evuimm8_ex0): Likewise.
475 (extract_evuimm8_ex0): Likewise.
476 (insert_evuimm_lt16): Likewise.
477 (extract_evuimm_lt16): Likewise.
478 (insert_rD_rS_even): Likewise.
479 (extract_rD_rS_even): Likewise.
480 (insert_off_lsp): Likewise.
481 (extract_off_lsp): Likewise.
482 (RD_EVEN): New operand.
485 (EVUIMM_LT16): New operand.
487 (EVUIMM_2_EX0): New operand.
489 (EVUIMM_4_EX0): New operand.
491 (EVUIMM_8_EX0): New operand.
493 (VX_OFF): New operand.
495 (VX_LSP_MASK): Likewise.
496 (VX_LSP_OFF_MASK): Likewise.
497 (PPC_OPCODE_LSP): Likewise.
498 (vle_opcodes): Add LSP opcodes.
499 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
501 2017-08-09 Jiong Wang <jiong.wang@arm.com>
503 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
504 register operands in CRC instructions.
505 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
508 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
510 * disassemble.c (disassembler): Mark big and mach with
513 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
515 * disassemble.c (disassembler): Remove arch/mach/endian
518 2017-07-25 Nick Clifton <nickc@redhat.com>
521 * arc-opc.c (insert_rhv2): Use lower case first letter in error
523 (insert_r0): Likewise.
524 (insert_r1): Likewise.
525 (insert_r2): Likewise.
526 (insert_r3): Likewise.
527 (insert_sp): Likewise.
528 (insert_gp): Likewise.
529 (insert_pcl): Likewise.
530 (insert_blink): Likewise.
531 (insert_ilink1): Likewise.
532 (insert_ilink2): Likewise.
533 (insert_ras): Likewise.
534 (insert_rbs): Likewise.
535 (insert_rcs): Likewise.
536 (insert_simm3s): Likewise.
537 (insert_rrange): Likewise.
538 (insert_r13el): Likewise.
539 (insert_fpel): Likewise.
540 (insert_blinkel): Likewise.
541 (insert_pclel): Likewise.
542 (insert_nps_bitop_size_2b): Likewise.
543 (insert_nps_imm_offset): Likewise.
544 (insert_nps_imm_entry): Likewise.
545 (insert_nps_size_16bit): Likewise.
546 (insert_nps_##NAME##_pos): Likewise.
547 (insert_nps_##NAME): Likewise.
548 (insert_nps_bitop_ins_ext): Likewise.
549 (insert_nps_##NAME): Likewise.
550 (insert_nps_min_hofs): Likewise.
551 (insert_nps_##NAME): Likewise.
552 (insert_nps_rbdouble_64): Likewise.
553 (insert_nps_misc_imm_offset): Likewise.
554 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
557 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
558 Jiong Wang <jiong.wang@arm.com>
560 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
562 * aarch64-dis-2.c: Regenerated.
564 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
566 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
569 2017-07-20 Nick Clifton <nickc@redhat.com>
571 * po/de.po: Updated German translation.
573 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
575 * arc-regs.h (sec_stat): New aux register.
576 (aux_kernel_sp): Likewise.
577 (aux_sec_u_sp): Likewise.
578 (aux_sec_k_sp): Likewise.
579 (sec_vecbase_build): Likewise.
580 (nsc_table_top): Likewise.
581 (nsc_table_base): Likewise.
582 (ersec_stat): Likewise.
583 (aux_sec_except): Likewise.
585 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
587 * arc-opc.c (extract_uimm12_20): New function.
588 (UIMM12_20): New operand.
590 * arc-tbl.h (sjli): Add new instruction.
592 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
593 John Eric Martin <John.Martin@emmicro-us.com>
595 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
596 (UIMM3_23): Adjust accordingly.
597 * arc-regs.h: Add/correct jli_base register.
598 * arc-tbl.h (jli_s): Likewise.
600 2017-07-18 Nick Clifton <nickc@redhat.com>
603 * aarch64-opc.c: Fix spelling typos.
604 * i386-dis.c: Likewise.
606 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
608 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
609 max_addr_offset and octets variables to size_t.
611 2017-07-12 Alan Modra <amodra@gmail.com>
613 * po/da.po: Update from translationproject.org/latest/opcodes/.
614 * po/de.po: Likewise.
615 * po/es.po: Likewise.
616 * po/fi.po: Likewise.
617 * po/fr.po: Likewise.
618 * po/id.po: Likewise.
619 * po/it.po: Likewise.
620 * po/nl.po: Likewise.
621 * po/pt_BR.po: Likewise.
622 * po/ro.po: Likewise.
623 * po/sv.po: Likewise.
624 * po/tr.po: Likewise.
625 * po/uk.po: Likewise.
626 * po/vi.po: Likewise.
627 * po/zh_CN.po: Likewise.
629 2017-07-11 Yao Qi <yao.qi@linaro.org>
630 Alan Modra <amodra@gmail.com>
632 * cgen.sh: Mark generated files read-only.
633 * epiphany-asm.c: Regenerate.
634 * epiphany-desc.c: Regenerate.
635 * epiphany-desc.h: Regenerate.
636 * epiphany-dis.c: Regenerate.
637 * epiphany-ibld.c: Regenerate.
638 * epiphany-opc.c: Regenerate.
639 * epiphany-opc.h: Regenerate.
640 * fr30-asm.c: Regenerate.
641 * fr30-desc.c: Regenerate.
642 * fr30-desc.h: Regenerate.
643 * fr30-dis.c: Regenerate.
644 * fr30-ibld.c: Regenerate.
645 * fr30-opc.c: Regenerate.
646 * fr30-opc.h: Regenerate.
647 * frv-asm.c: Regenerate.
648 * frv-desc.c: Regenerate.
649 * frv-desc.h: Regenerate.
650 * frv-dis.c: Regenerate.
651 * frv-ibld.c: Regenerate.
652 * frv-opc.c: Regenerate.
653 * frv-opc.h: Regenerate.
654 * ip2k-asm.c: Regenerate.
655 * ip2k-desc.c: Regenerate.
656 * ip2k-desc.h: Regenerate.
657 * ip2k-dis.c: Regenerate.
658 * ip2k-ibld.c: Regenerate.
659 * ip2k-opc.c: Regenerate.
660 * ip2k-opc.h: Regenerate.
661 * iq2000-asm.c: Regenerate.
662 * iq2000-desc.c: Regenerate.
663 * iq2000-desc.h: Regenerate.
664 * iq2000-dis.c: Regenerate.
665 * iq2000-ibld.c: Regenerate.
666 * iq2000-opc.c: Regenerate.
667 * iq2000-opc.h: Regenerate.
668 * lm32-asm.c: Regenerate.
669 * lm32-desc.c: Regenerate.
670 * lm32-desc.h: Regenerate.
671 * lm32-dis.c: Regenerate.
672 * lm32-ibld.c: Regenerate.
673 * lm32-opc.c: Regenerate.
674 * lm32-opc.h: Regenerate.
675 * lm32-opinst.c: Regenerate.
676 * m32c-asm.c: Regenerate.
677 * m32c-desc.c: Regenerate.
678 * m32c-desc.h: Regenerate.
679 * m32c-dis.c: Regenerate.
680 * m32c-ibld.c: Regenerate.
681 * m32c-opc.c: Regenerate.
682 * m32c-opc.h: Regenerate.
683 * m32r-asm.c: Regenerate.
684 * m32r-desc.c: Regenerate.
685 * m32r-desc.h: Regenerate.
686 * m32r-dis.c: Regenerate.
687 * m32r-ibld.c: Regenerate.
688 * m32r-opc.c: Regenerate.
689 * m32r-opc.h: Regenerate.
690 * m32r-opinst.c: Regenerate.
691 * mep-asm.c: Regenerate.
692 * mep-desc.c: Regenerate.
693 * mep-desc.h: Regenerate.
694 * mep-dis.c: Regenerate.
695 * mep-ibld.c: Regenerate.
696 * mep-opc.c: Regenerate.
697 * mep-opc.h: Regenerate.
698 * mt-asm.c: Regenerate.
699 * mt-desc.c: Regenerate.
700 * mt-desc.h: Regenerate.
701 * mt-dis.c: Regenerate.
702 * mt-ibld.c: Regenerate.
703 * mt-opc.c: Regenerate.
704 * mt-opc.h: Regenerate.
705 * or1k-asm.c: Regenerate.
706 * or1k-desc.c: Regenerate.
707 * or1k-desc.h: Regenerate.
708 * or1k-dis.c: Regenerate.
709 * or1k-ibld.c: Regenerate.
710 * or1k-opc.c: Regenerate.
711 * or1k-opc.h: Regenerate.
712 * or1k-opinst.c: Regenerate.
713 * xc16x-asm.c: Regenerate.
714 * xc16x-desc.c: Regenerate.
715 * xc16x-desc.h: Regenerate.
716 * xc16x-dis.c: Regenerate.
717 * xc16x-ibld.c: Regenerate.
718 * xc16x-opc.c: Regenerate.
719 * xc16x-opc.h: Regenerate.
720 * xstormy16-asm.c: Regenerate.
721 * xstormy16-desc.c: Regenerate.
722 * xstormy16-desc.h: Regenerate.
723 * xstormy16-dis.c: Regenerate.
724 * xstormy16-ibld.c: Regenerate.
725 * xstormy16-opc.c: Regenerate.
726 * xstormy16-opc.h: Regenerate.
728 2017-07-07 Alan Modra <amodra@gmail.com>
730 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
731 * m32c-dis.c: Regenerate.
732 * mep-dis.c: Regenerate.
734 2017-07-05 Borislav Petkov <bp@suse.de>
736 * i386-dis.c: Enable ModRM.reg /6 aliases.
738 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
740 * opcodes/arm-dis.c: Support MVFR2 in disassembly
743 2017-07-04 Tristan Gingold <gingold@adacore.com>
745 * configure: Regenerate.
747 2017-07-03 Tristan Gingold <gingold@adacore.com>
749 * po/opcodes.pot: Regenerate.
751 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
753 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
754 entries to the MSA ASE instruction block.
756 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
757 Maciej W. Rozycki <macro@imgtec.com>
759 * micromips-opc.c (XPA, XPAVZ): New macros.
760 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
763 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
764 Maciej W. Rozycki <macro@imgtec.com>
766 * micromips-opc.c (I36): New macro.
767 (micromips_opcodes): Add "eretnc".
769 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
770 Andrew Bennett <andrew.bennett@imgtec.com>
772 * mips-dis.c (mips_calculate_combination_ases): Handle the
774 (parse_mips_ase_option): New function.
775 (parse_mips_dis_option): Factor out ASE option handling to the
776 new function. Call `mips_calculate_combination_ases'.
777 * mips-opc.c (XPAVZ): New macro.
778 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
779 "mfhgc0", "mthc0" and "mthgc0".
781 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
783 * mips-dis.c (mips_calculate_combination_ases): New function.
784 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
785 calculation to the new function.
786 (set_default_mips_dis_options): Call the new function.
788 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
790 * arc-dis.c (parse_disassembler_options): Use
791 FOR_EACH_DISASSEMBLER_OPTION.
793 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
795 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
796 disassembler option strings.
797 (parse_cpu_option): Likewise.
799 2017-06-28 Tamar Christina <tamar.christina@arm.com>
801 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
802 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
803 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
804 (aarch64_feature_dotprod, DOT_INSN): New.
806 * aarch64-dis-2.c: Regenerated.
808 2017-06-28 Jiong Wang <jiong.wang@arm.com>
810 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
812 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
813 Matthew Fortune <matthew.fortune@imgtec.com>
814 Andrew Bennett <andrew.bennett@imgtec.com>
816 * mips-formats.h (INT_BIAS): New macro.
817 (INT_ADJ): Redefine in INT_BIAS terms.
818 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
819 (mips_print_save_restore): New function.
820 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
821 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
823 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
824 (print_mips16_insn_arg): Call `mips_print_save_restore' for
825 OP_SAVE_RESTORE_LIST handling, factored out from here.
826 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
827 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
828 (mips_builtin_opcodes): Add "restore" and "save" entries.
829 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
831 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
833 2017-06-23 Andrew Waterman <andrew@sifive.com>
835 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
836 alias; do not mark SLTI instruction as an alias.
838 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
840 * i386-dis.c (RM_0FAE_REG_5): Removed.
841 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
842 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
843 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
844 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
845 PREFIX_MOD_3_0F01_REG_5_RM_0.
846 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
847 PREFIX_MOD_3_0FAE_REG_5.
848 (mod_table): Update MOD_0FAE_REG_5.
849 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
850 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
851 * i386-tbl.h: Regenerated.
853 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
855 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
856 * i386-opc.tbl: Likewise.
857 * i386-tbl.h: Regenerated.
859 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
861 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
863 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
866 2017-06-19 Nick Clifton <nickc@redhat.com>
869 * score-dis.c (score_opcodes): Add sentinel.
871 2017-06-16 Alan Modra <amodra@gmail.com>
873 * rx-decode.c: Regenerate.
875 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
878 * i386-dis.c (OP_E_register): Check valid bnd register.
881 2017-06-15 Nick Clifton <nickc@redhat.com>
884 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
887 2017-06-15 Nick Clifton <nickc@redhat.com>
890 * rl78-decode.opc (OP_BUF_LEN): Define.
891 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
892 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
894 * rl78-decode.c: Regenerate.
896 2017-06-15 Nick Clifton <nickc@redhat.com>
899 * bfin-dis.c (gregs): Clip index to prevent overflow.
904 2017-06-14 Nick Clifton <nickc@redhat.com>
907 * score7-dis.c (score_opcodes): Add sentinel.
909 2017-06-14 Yao Qi <yao.qi@linaro.org>
911 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
912 * arm-dis.c: Likewise.
913 * ia64-dis.c: Likewise.
914 * mips-dis.c: Likewise.
915 * spu-dis.c: Likewise.
916 * disassemble.h (print_insn_aarch64): New declaration, moved from
918 (print_insn_big_arm, print_insn_big_mips): Likewise.
919 (print_insn_i386, print_insn_ia64): Likewise.
920 (print_insn_little_arm, print_insn_little_mips): Likewise.
922 2017-06-14 Nick Clifton <nickc@redhat.com>
925 * rx-decode.opc: Include libiberty.h
926 (GET_SCALE): New macro - validates access to SCALE array.
927 (GET_PSCALE): New macro - validates access to PSCALE array.
928 (DIs, SIs, S2Is, rx_disp): Use new macros.
929 * rx-decode.c: Regenerate.
931 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
933 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
935 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
937 * arc-dis.c (enforced_isa_mask): Declare.
938 (cpu_types): Likewise.
939 (parse_cpu_option): New function.
940 (parse_disassembler_options): Use it.
941 (print_insn_arc): Use enforced_isa_mask.
942 (print_arc_disassembler_options): Document new options.
944 2017-05-24 Yao Qi <yao.qi@linaro.org>
946 * alpha-dis.c: Include disassemble.h, don't include
948 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
949 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
950 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
951 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
952 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
953 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
954 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
955 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
956 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
957 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
958 * moxie-dis.c, msp430-dis.c, mt-dis.c:
959 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
960 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
961 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
962 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
963 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
964 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
965 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
966 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
967 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
968 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
969 * z80-dis.c, z8k-dis.c: Likewise.
970 * disassemble.h: New file.
972 2017-05-24 Yao Qi <yao.qi@linaro.org>
974 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
975 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
977 2017-05-24 Yao Qi <yao.qi@linaro.org>
979 * disassemble.c (disassembler): Add arguments a, big and mach.
982 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
984 * i386-dis.c (NOTRACK_Fixup): New.
986 (NOTRACK_PREFIX): Likewise.
987 (last_active_prefix): Likewise.
988 (reg_table): Use NOTRACK on indirect call and jmp.
989 (ckprefix): Set last_active_prefix.
990 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
991 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
992 * i386-opc.h (NoTrackPrefixOk): New.
993 (i386_opcode_modifier): Add notrackprefixok.
994 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
996 * i386-tbl.h: Regenerated.
998 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1000 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1002 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1003 bfd_mach_sparc_v9m8.
1004 (print_insn_sparc): Handle new operand types.
1005 * sparc-opc.c (MASK_M8): Define.
1007 (v6notlet): Likewise.
1018 (v9andleon): Likewise.
1021 (HWS2_VM8): Likewise.
1022 (sparc_opcode_archs): Add entry for "m8".
1023 (sparc_opcodes): Add OSA2017 and M8 instructions
1024 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1026 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1027 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1028 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1029 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1030 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1031 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1032 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1033 ASI_CORE_SELECT_COMMIT_NHT.
1035 2017-05-18 Alan Modra <amodra@gmail.com>
1037 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1038 * aarch64-dis.c: Likewise.
1039 * aarch64-gen.c: Likewise.
1040 * aarch64-opc.c: Likewise.
1042 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1043 Matthew Fortune <matthew.fortune@imgtec.com>
1045 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1046 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1047 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1048 (print_insn_arg) <OP_REG28>: Add handler.
1049 (validate_insn_args) <OP_REG28>: Handle.
1050 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1051 32-bit encoding and 9-bit immediates.
1052 (print_insn_mips16): Handle MIPS16 instructions that require
1053 32-bit encoding and MFC0/MTC0 operand decoding.
1054 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1055 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1056 (RD_C0, WR_C0, E2, E2MT): New macros.
1057 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1058 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1059 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1060 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1061 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1062 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1063 instructions, "swl", "swr", "sync" and its "sync_acquire",
1064 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1065 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1066 regular/extended entries for original MIPS16 ISA revision
1067 instructions whose extended forms are subdecoded in the MIPS16e2
1068 ISA revision: "li", "sll" and "srl".
1070 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1072 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1073 reference in CP0 move operand decoding.
1075 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1077 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1078 type to hexadecimal.
1079 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1081 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1083 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1084 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1085 "sync_rmb" and "sync_wmb" as aliases.
1086 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1087 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1089 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1091 * arc-dis.c (parse_option): Update quarkse_em option..
1092 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1094 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1096 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1098 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1100 2017-05-01 Michael Clark <michaeljclark@mac.com>
1102 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1105 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1107 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1108 and branches and not synthetic data instructions.
1110 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1112 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1114 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1116 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1117 * arc-opc.c (insert_r13el): New function.
1119 * arc-tbl.h: Add new enter/leave variants.
1121 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1123 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1125 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1127 * mips-dis.c (print_mips_disassembler_options): Add
1130 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1132 * mips16-opc.c (AL): New macro.
1133 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1134 of "ld" and "lw" as aliases.
1136 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1138 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1141 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1142 Alan Modra <amodra@gmail.com>
1144 * ppc-opc.c (ELEV): Define.
1145 (vle_opcodes): Add se_rfgi and e_sc.
1146 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1149 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1151 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1153 2017-04-21 Nick Clifton <nickc@redhat.com>
1156 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1159 2017-04-13 Alan Modra <amodra@gmail.com>
1161 * epiphany-desc.c: Regenerate.
1162 * fr30-desc.c: Regenerate.
1163 * frv-desc.c: Regenerate.
1164 * ip2k-desc.c: Regenerate.
1165 * iq2000-desc.c: Regenerate.
1166 * lm32-desc.c: Regenerate.
1167 * m32c-desc.c: Regenerate.
1168 * m32r-desc.c: Regenerate.
1169 * mep-desc.c: Regenerate.
1170 * mt-desc.c: Regenerate.
1171 * or1k-desc.c: Regenerate.
1172 * xc16x-desc.c: Regenerate.
1173 * xstormy16-desc.c: Regenerate.
1175 2017-04-11 Alan Modra <amodra@gmail.com>
1177 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1178 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1179 PPC_OPCODE_TMR for e6500.
1180 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1181 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1182 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1183 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1184 (PPCHTM): Define as PPC_OPCODE_POWER8.
1185 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1187 2017-04-10 Alan Modra <amodra@gmail.com>
1189 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1190 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1191 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1192 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1194 2017-04-09 Pip Cet <pipcet@gmail.com>
1196 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1197 appropriate floating-point precision directly.
1199 2017-04-07 Alan Modra <amodra@gmail.com>
1201 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1202 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1203 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1204 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1205 vector instructions with E6500 not PPCVEC2.
1207 2017-04-06 Pip Cet <pipcet@gmail.com>
1209 * Makefile.am: Add wasm32-dis.c.
1210 * configure.ac: Add wasm32-dis.c to wasm32 target.
1211 * disassemble.c: Add wasm32 disassembler code.
1212 * wasm32-dis.c: New file.
1213 * Makefile.in: Regenerate.
1214 * configure: Regenerate.
1215 * po/POTFILES.in: Regenerate.
1216 * po/opcodes.pot: Regenerate.
1218 2017-04-05 Pedro Alves <palves@redhat.com>
1220 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1221 * arm-dis.c (parse_arm_disassembler_options): Constify.
1222 * ppc-dis.c (powerpc_init_dialect): Constify local.
1223 * vax-dis.c (parse_disassembler_options): Constify.
1225 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1227 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1230 2017-03-30 Pip Cet <pipcet@gmail.com>
1232 * configure.ac: Add (empty) bfd_wasm32_arch target.
1233 * configure: Regenerate
1234 * po/opcodes.pot: Regenerate.
1236 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1238 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1240 * opcodes/sparc-opc.c (asi_table): New ASIs.
1242 2017-03-29 Alan Modra <amodra@gmail.com>
1244 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1246 (lookup_powerpc): Don't special case -1 dialect. Handle
1248 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1249 lookup_powerpc call, pass it on second.
1251 2017-03-27 Alan Modra <amodra@gmail.com>
1254 * ppc-dis.c (struct ppc_mopt): Comment.
1255 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1257 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1259 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1260 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1261 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1262 (insert_nps_misc_imm_offset): New function.
1263 (extract_nps_misc imm_offset): New function.
1264 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1265 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1267 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1269 * s390-mkopc.c (main): Remove vx2 check.
1270 * s390-opc.txt: Remove vx2 instruction flags.
1272 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1274 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1275 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1276 (insert_nps_imm_offset): New function.
1277 (extract_nps_imm_offset): New function.
1278 (insert_nps_imm_entry): New function.
1279 (extract_nps_imm_entry): New function.
1281 2017-03-17 Alan Modra <amodra@gmail.com>
1284 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1285 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1286 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1288 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1290 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1294 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1296 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1298 2017-03-13 Andrew Waterman <andrew@sifive.com>
1300 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1305 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1307 * i386-gen.c (opcode_modifiers): Replace S with Load.
1308 * i386-opc.h (S): Removed.
1310 (i386_opcode_modifier): Replace s with load.
1311 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1312 and {evex}. Replace S with Load.
1313 * i386-tbl.h: Regenerated.
1315 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1317 * i386-opc.tbl: Use CpuCET on rdsspq.
1318 * i386-tbl.h: Regenerated.
1320 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1322 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1323 <vsx>: Do not use PPC_OPCODE_VSX3;
1325 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1327 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1329 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1331 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1332 (MOD_0F1E_PREFIX_1): Likewise.
1333 (MOD_0F38F5_PREFIX_2): Likewise.
1334 (MOD_0F38F6_PREFIX_0): Likewise.
1335 (RM_0F1E_MOD_3_REG_7): Likewise.
1336 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1337 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1338 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1339 (PREFIX_0F1E): Likewise.
1340 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1341 (PREFIX_0F38F5): Likewise.
1342 (dis386_twobyte): Use PREFIX_0F1E.
1343 (reg_table): Add REG_0F1E_MOD_3.
1344 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1345 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1346 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1347 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1348 (three_byte_table): Use PREFIX_0F38F5.
1349 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1350 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1351 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1352 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1353 PREFIX_MOD_3_0F01_REG_5_RM_2.
1354 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1355 (cpu_flags): Add CpuCET.
1356 * i386-opc.h (CpuCET): New enum.
1357 (CpuUnused): Commented out.
1358 (i386_cpu_flags): Add cpucet.
1359 * i386-opc.tbl: Add Intel CET instructions.
1360 * i386-init.h: Regenerated.
1361 * i386-tbl.h: Likewise.
1363 2017-03-06 Alan Modra <amodra@gmail.com>
1366 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1367 (extract_raq, extract_ras, extract_rbx): New functions.
1368 (powerpc_operands): Use opposite corresponding insert function.
1370 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1371 register restriction.
1373 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1375 * disassemble.c Include "safe-ctype.h".
1376 (disassemble_init_for_target): Handle s390 init.
1377 (remove_whitespace_and_extra_commas): New function.
1378 (disassembler_options_cmp): Likewise.
1379 * arm-dis.c: Include "libiberty.h".
1381 (regnames): Use long disassembler style names.
1382 Add force-thumb and no-force-thumb options.
1383 (NUM_ARM_REGNAMES): Rename from this...
1384 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1385 (get_arm_regname_num_options): Delete.
1386 (set_arm_regname_option): Likewise.
1387 (get_arm_regnames): Likewise.
1388 (parse_disassembler_options): Likewise.
1389 (parse_arm_disassembler_option): Rename from this...
1390 (parse_arm_disassembler_options): ...to this. Make static.
1391 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1392 (print_insn): Use parse_arm_disassembler_options.
1393 (disassembler_options_arm): New function.
1394 (print_arm_disassembler_options): Handle updated regnames.
1395 * ppc-dis.c: Include "libiberty.h".
1396 (ppc_opts): Add "32" and "64" entries.
1397 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1398 (powerpc_init_dialect): Add break to switch statement.
1399 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1400 (disassembler_options_powerpc): New function.
1401 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1402 Remove printing of "32" and "64".
1403 * s390-dis.c: Include "libiberty.h".
1404 (init_flag): Remove unneeded variable.
1405 (struct s390_options_t): New structure type.
1406 (options): New structure.
1407 (init_disasm): Rename from this...
1408 (disassemble_init_s390): ...to this. Add initializations for
1409 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1410 (print_insn_s390): Delete call to init_disasm.
1411 (disassembler_options_s390): New function.
1412 (print_s390_disassembler_options): Print using information from
1414 * po/opcodes.pot: Regenerate.
1416 2017-02-28 Jan Beulich <jbeulich@suse.com>
1418 * i386-dis.c (PCMPESTR_Fixup): New.
1419 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1420 (prefix_table): Use PCMPESTR_Fixup.
1421 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1423 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1424 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1425 Split 64-bit and non-64-bit variants.
1426 * opcodes/i386-tbl.h: Re-generate.
1428 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1430 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1431 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1432 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1433 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1434 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1435 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1436 (OP_SVE_V_HSD): New macros.
1437 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1438 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1439 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1440 (aarch64_opcode_table): Add new SVE instructions.
1441 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1442 for rotation operands. Add new SVE operands.
1443 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1444 (ins_sve_quad_index): Likewise.
1445 (ins_imm_rotate): Split into...
1446 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1447 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1448 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1450 (aarch64_ins_sve_addr_ri_s4): New function.
1451 (aarch64_ins_sve_quad_index): Likewise.
1452 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1453 * aarch64-asm-2.c: Regenerate.
1454 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1455 (ext_sve_quad_index): Likewise.
1456 (ext_imm_rotate): Split into...
1457 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1458 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1459 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1461 (aarch64_ext_sve_addr_ri_s4): New function.
1462 (aarch64_ext_sve_quad_index): Likewise.
1463 (aarch64_ext_sve_index): Allow quad indices.
1464 (do_misc_decoding): Likewise.
1465 * aarch64-dis-2.c: Regenerate.
1466 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1467 aarch64_field_kinds.
1468 (OPD_F_OD_MASK): Widen by one bit.
1469 (OPD_F_NO_ZR): Bump accordingly.
1470 (get_operand_field_width): New function.
1471 * aarch64-opc.c (fields): Add new SVE fields.
1472 (operand_general_constraint_met_p): Handle new SVE operands.
1473 (aarch64_print_operand): Likewise.
1474 * aarch64-opc-2.c: Regenerate.
1476 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1478 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1479 (aarch64_feature_compnum): ...this.
1480 (SIMD_V8_3): Replace with...
1482 (CNUM_INSN): New macro.
1483 (aarch64_opcode_table): Use it for the complex number instructions.
1485 2017-02-24 Jan Beulich <jbeulich@suse.com>
1487 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1489 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1491 Add support for associating SPARC ASIs with an architecture level.
1492 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1493 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1494 decoding of SPARC ASIs.
1496 2017-02-23 Jan Beulich <jbeulich@suse.com>
1498 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1499 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1501 2017-02-21 Jan Beulich <jbeulich@suse.com>
1503 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1504 1 (instead of to itself). Correct typo.
1506 2017-02-14 Andrew Waterman <andrew@sifive.com>
1508 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1511 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1513 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1514 (aarch64_sys_reg_supported_p): Handle them.
1516 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1518 * arc-opc.c (UIMM6_20R): Define.
1519 (SIMM12_20): Use above.
1520 (SIMM12_20R): Define.
1521 (SIMM3_5_S): Use above.
1522 (UIMM7_A32_11R_S): Define.
1523 (UIMM7_9_S): Use above.
1524 (UIMM3_13R_S): Define.
1525 (SIMM11_A32_7_S): Use above.
1527 (UIMM10_A32_8_S): Use above.
1528 (UIMM8_8R_S): Define.
1530 (arc_relax_opcodes): Use all above defines.
1532 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1534 * arc-regs.h: Distinguish some of the registers different on
1535 ARC700 and HS38 cpus.
1537 2017-02-14 Alan Modra <amodra@gmail.com>
1540 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1541 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1543 2017-02-11 Stafford Horne <shorne@gmail.com>
1544 Alan Modra <amodra@gmail.com>
1546 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1547 Use insn_bytes_value and insn_int_value directly instead. Don't
1548 free allocated memory until function exit.
1550 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1552 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1554 2017-02-03 Nick Clifton <nickc@redhat.com>
1557 * aarch64-opc.c (print_register_list): Ensure that the register
1558 list index will fir into the tb buffer.
1559 (print_register_offset_address): Likewise.
1560 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1562 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1565 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1566 instructions when the previous fetch packet ends with a 32-bit
1569 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1571 * pru-opc.c: Remove vague reference to a future GDB port.
1573 2017-01-20 Nick Clifton <nickc@redhat.com>
1575 * po/ga.po: Updated Irish translation.
1577 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1579 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1581 2017-01-13 Yao Qi <yao.qi@linaro.org>
1583 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1584 if FETCH_DATA returns 0.
1585 (m68k_scan_mask): Likewise.
1586 (print_insn_m68k): Update code to handle -1 return value.
1588 2017-01-13 Yao Qi <yao.qi@linaro.org>
1590 * m68k-dis.c (enum print_insn_arg_error): New.
1591 (NEXTBYTE): Replace -3 with
1592 PRINT_INSN_ARG_MEMORY_ERROR.
1593 (NEXTULONG): Likewise.
1594 (NEXTSINGLE): Likewise.
1595 (NEXTDOUBLE): Likewise.
1596 (NEXTDOUBLE): Likewise.
1597 (NEXTPACKED): Likewise.
1598 (FETCH_ARG): Likewise.
1599 (FETCH_DATA): Update comments.
1600 (print_insn_arg): Update comments. Replace magic numbers with
1602 (match_insn_m68k): Likewise.
1604 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1606 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1607 * i386-dis-evex.h (evex_table): Updated.
1608 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1609 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1610 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1611 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1612 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1613 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1614 * i386-init.h: Regenerate.
1615 * i386-tbl.h: Ditto.
1617 2017-01-12 Yao Qi <yao.qi@linaro.org>
1619 * msp430-dis.c (msp430_singleoperand): Return -1 if
1620 msp430dis_opcode_signed returns false.
1621 (msp430_doubleoperand): Likewise.
1622 (msp430_branchinstr): Return -1 if
1623 msp430dis_opcode_unsigned returns false.
1624 (msp430x_calla_instr): Likewise.
1625 (print_insn_msp430): Likewise.
1627 2017-01-05 Nick Clifton <nickc@redhat.com>
1630 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1631 could not be matched.
1632 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1635 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1637 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1638 (aarch64_opcode_table): Use RCPC_INSN.
1640 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1642 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1644 * riscv-opcodes/all-opcodes: Likewise.
1646 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1648 * riscv-dis.c (print_insn_args): Add fall through comment.
1650 2017-01-03 Nick Clifton <nickc@redhat.com>
1652 * po/sr.po: New Serbian translation.
1653 * configure.ac (ALL_LINGUAS): Add sr.
1654 * configure: Regenerate.
1656 2017-01-02 Alan Modra <amodra@gmail.com>
1658 * epiphany-desc.h: Regenerate.
1659 * epiphany-opc.h: Regenerate.
1660 * fr30-desc.h: Regenerate.
1661 * fr30-opc.h: Regenerate.
1662 * frv-desc.h: Regenerate.
1663 * frv-opc.h: Regenerate.
1664 * ip2k-desc.h: Regenerate.
1665 * ip2k-opc.h: Regenerate.
1666 * iq2000-desc.h: Regenerate.
1667 * iq2000-opc.h: Regenerate.
1668 * lm32-desc.h: Regenerate.
1669 * lm32-opc.h: Regenerate.
1670 * m32c-desc.h: Regenerate.
1671 * m32c-opc.h: Regenerate.
1672 * m32r-desc.h: Regenerate.
1673 * m32r-opc.h: Regenerate.
1674 * mep-desc.h: Regenerate.
1675 * mep-opc.h: Regenerate.
1676 * mt-desc.h: Regenerate.
1677 * mt-opc.h: Regenerate.
1678 * or1k-desc.h: Regenerate.
1679 * or1k-opc.h: Regenerate.
1680 * xc16x-desc.h: Regenerate.
1681 * xc16x-opc.h: Regenerate.
1682 * xstormy16-desc.h: Regenerate.
1683 * xstormy16-opc.h: Regenerate.
1685 2017-01-02 Alan Modra <amodra@gmail.com>
1687 Update year range in copyright notice of all files.
1689 For older changes see ChangeLog-2016
1691 Copyright (C) 2017 Free Software Foundation, Inc.
1693 Copying and distribution of this file, with or without modification,
1694 are permitted in any medium without royalty provided the copyright
1695 notice and this notice are preserved.
1701 version-control: never