opcodes/ChangeLog

   1 2011-09-08  Mark Fortescue <mark@mtfhpc.demon.co.uk>
   2
   3         The changes below bring 'mov' and 'ticc' instructions into line
   4         with the V8 SPARC Architecture Manual.
   5         * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
   6         * sparc-opc.c (sparc_opcodes): Add alias entries for
   7         'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
   8         'mov regrs2,%wim' and 'mov regrs2,%tbr'.
   9         * sparc-opc.c (sparc_opcodes): Move/Change entries for
  10         'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
  11         and 'mov imm,%tbr'.
  12         * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
  13         mov aliases.
  14
  15 2011-09-08  David S. Miller  <davem@davemloft.net>
  16
  17         * sparc-opc.c (pdistn): Destination is integer not float register.
  18
  19 2011-09-07  Andreas Schwab  <schwab@linux-m68k.org>
  20
  21         * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
  22
  23 2011-08-26  Nick Clifton  <nickc@redhat.com>
  24
  25         * po/es.po: Updated Spanish translation.
  26
  27 2011-08-22  Nick Clifton  <nickc@redhat.com>
  28
  29         * Makefile.am (CPUDIR): Redfine to point to top level cpu
  30         directory.
  31         (stamp-frv): Use CPUDIR.
  32         (stamp-iq2000): Likewise.
  33         (stamp-lm32): Likewise.
  34         (stamp-m32c): Likewise.
  35         (stamp-mt): Likewise.
  36         (stamp-xc16x): Likewise.
  37         * Makefile.in: Regenerate.
  38
  39 2011-08-09  Chao-ying Fu  <fu@mips.com>
  40             Maciej W. Rozycki  <macro@codesourcery.com>
  41
  42         * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
  43         and "mips64r2".
  44         (print_insn_args, print_insn_micromips): Handle MCU.
  45         * micromips-opc.c (MC): New macro.
  46         (micromips_opcodes): Add "aclr", "aset" and "iret".
  47         * mips-opc.c (MC): New macro.
  48         (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
  49
  50 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
  51
  52         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
  53         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
  54         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
  55         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
  56         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
  57         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
  58         (WR_s): Update macro.
  59         (micromips_opcodes): Update register use flags of: "addiu",
  60         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
  61         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
  62         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
  63         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
  64         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
  65         "swm" and "xor" instructions.
  66
  67 2011-08-05  David S. Miller  <davem@davemloft.net>
  68
  69         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
  70         (X_RS3): New macro.
  71         (print_insn_sparc): Handle '4', '5', and '(' format codes.
  72         Accept %asr numbers below 28.
  73         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
  74         instructions.
  75
  76 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
  77
  78         * i386-dis.c (xop_table): Remove spurious bextr insn.
  79
  80 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
  81
  82         PR ld/13048
  83         * i386-dis.c (print_insn): Optimize info->mach check.
  84
  85 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
  86
  87         PR gas/13046
  88         * i386-opc.tbl: Add Disp32S to 64bit call.
  89         * i386-tbl.h: Regenerated.
  90
  91 2011-07-24  Chao-ying Fu  <fu@mips.com>
  92             Maciej W. Rozycki  <macro@codesourcery.com>
  93
  94         * micromips-opc.c: New file.
  95         * mips-dis.c (micromips_to_32_reg_b_map): New array.
  96         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
  97         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
  98         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
  99         (micromips_to_32_reg_q_map): Likewise.
 100         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
 101         (micromips_ase): New variable.
 102         (is_micromips): New function.
 103         (set_default_mips_dis_options): Handle microMIPS ASE.
 104         (print_insn_micromips): New function.
 105         (is_compressed_mode_p): Likewise.
 106         (_print_insn_mips): Handle microMIPS instructions.
 107         * Makefile.am (CFILES): Add micromips-opc.c.
 108         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
 109         * Makefile.in: Regenerate.
 110         * configure: Regenerate.
 111
 112         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
 113         (micromips_to_32_reg_i_map): Likewise.
 114         (micromips_to_32_reg_m_map): Likewise.
 115         (micromips_to_32_reg_n_map): New macro.
 116
 117 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 118
 119         * mips-opc.c (NODS): New macro.
 120         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 121         (DSP_VOLA): Likewise.
 122         (mips_builtin_opcodes): Add NODS annotation to "deret" and
 123         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
 124         place of TRAP for "wait", "waiti" and "yield".
 125         * mips16-opc.c (NODS): New macro.
 126         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 127         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
 128         "restore" and "save".
 129
 130 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 131
 132         * configure.in: Handle bfd_k1om_arch.
 133         * configure: Regenerated.
 134
 135         * disassemble.c (disassembler): Handle bfd_k1om_arch.
 136
 137         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
 138         bfd_mach_k1om_intel_syntax.
 139
 140         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
 141         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
 142         (cpu_flags): Add CpuK1OM.
 143
 144         * i386-opc.h (CpuK1OM): New.
 145         (i386_cpu_flags): Add cpuk1om.
 146
 147         * i386-init.h: Regenerated.
 148         * i386-tbl.h: Likewise.
 149
 150 2011-07-12  Nick Clifton  <nickc@redhat.com>
 151
 152         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 153         accidental change.
 154
 155 2011-07-01  Nick Clifton  <nickc@redhat.com>
 156
 157         PR binutils/12329
 158         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 159         insns using post-increment addressing.
 160
 161 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 162
 163         * i386-dis.c (vex_len_table): Update rorxS.
 164
 165 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 166
 167         AVX Programming Reference (June, 2011)
 168         * i386-dis.c (vex_len_table): Correct rorxS.
 169
 170         * i386-opc.tbl: Correct rorx.
 171         * i386-tbl.h: Regenerated.
 172
 173 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 174
 175         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 176         * tilepro-opc.c (find_opcode): Likewise.
 177
 178 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 179
 180         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 181
 182 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 185         PREFIX_VEX_0F388E.
 186
 187 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 188
 189         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 190         (MOSTLYCLEANFILES): ... here.
 191         * Makefile.in: Regenerate.
 192
 193 2011-06-14  Alan Modra  <amodra@gmail.com>
 194
 195         * Makefile.in: Regenerate.
 196
 197 2011-06-13  Walter Lee  <walt@tilera.com>
 198
 199         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 200         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 201         * Makefile.in: Regenerate.
 202         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 203         * configure: Regenerate.
 204         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 205         * po/POTFILES.in: Regenerate.
 206         * tilegx-dis.c: New file.
 207         * tilegx-opc.c: New file.
 208         * tilepro-dis.c: New file.
 209         * tilepro-opc.c: New file.
 210
 211 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 212
 213         AVX Programming Reference (June, 2011)
 214         * i386-dis.c (XMGatherQ): New.
 215         * i386-dis.c (EXxmm_mb): New.
 216         (EXxmm_mb): Likewise.
 217         (EXxmm_mw): Likewise.
 218         (EXxmm_md): Likewise.
 219         (EXxmm_mq): Likewise.
 220         (EXxmmdw): Likewise.
 221         (EXxmmqd): Likewise.
 222         (VexGatherQ): Likewise.
 223         (MVexVSIBDWpX): Likewise.
 224         (MVexVSIBQWpX): Likewise.
 225         (xmm_mb_mode): Likewise.
 226         (xmm_mw_mode): Likewise.
 227         (xmm_md_mode): Likewise.
 228         (xmm_mq_mode): Likewise.
 229         (xmmdw_mode): Likewise.
 230         (xmmqd_mode): Likewise.
 231         (ymmxmm_mode): Likewise.
 232         (vex_vsib_d_w_dq_mode): Likewise.
 233         (vex_vsib_q_w_dq_mode): Likewise.
 234         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 235         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 236         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 237         (PREFIX_0F3882): Likewise.
 238         (PREFIX_VEX_0F3816): Likewise.
 239         (PREFIX_VEX_0F3836): Likewise.
 240         (PREFIX_VEX_0F3845): Likewise.
 241         (PREFIX_VEX_0F3846): Likewise.
 242         (PREFIX_VEX_0F3847): Likewise.
 243         (PREFIX_VEX_0F3858): Likewise.
 244         (PREFIX_VEX_0F3859): Likewise.
 245         (PREFIX_VEX_0F385A): Likewise.
 246         (PREFIX_VEX_0F3878): Likewise.
 247         (PREFIX_VEX_0F3879): Likewise.
 248         (PREFIX_VEX_0F388C): Likewise.
 249         (PREFIX_VEX_0F388E): Likewise.
 250         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 251         (PREFIX_VEX_0F38F5): Likewise.
 252         (PREFIX_VEX_0F38F6): Likewise.
 253         (PREFIX_VEX_0F3A00): Likewise.
 254         (PREFIX_VEX_0F3A01): Likewise.
 255         (PREFIX_VEX_0F3A02): Likewise.
 256         (PREFIX_VEX_0F3A38): Likewise.
 257         (PREFIX_VEX_0F3A39): Likewise.
 258         (PREFIX_VEX_0F3A46): Likewise.
 259         (PREFIX_VEX_0F3AF0): Likewise.
 260         (VEX_LEN_0F3816_P_2): Likewise.
 261         (VEX_LEN_0F3819_P_2): Likewise.
 262         (VEX_LEN_0F3836_P_2): Likewise.
 263         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 264         (VEX_LEN_0F38F5_P_0): Likewise.
 265         (VEX_LEN_0F38F5_P_1): Likewise.
 266         (VEX_LEN_0F38F5_P_3): Likewise.
 267         (VEX_LEN_0F38F6_P_3): Likewise.
 268         (VEX_LEN_0F38F7_P_1): Likewise.
 269         (VEX_LEN_0F38F7_P_2): Likewise.
 270         (VEX_LEN_0F38F7_P_3): Likewise.
 271         (VEX_LEN_0F3A00_P_2): Likewise.
 272         (VEX_LEN_0F3A01_P_2): Likewise.
 273         (VEX_LEN_0F3A38_P_2): Likewise.
 274         (VEX_LEN_0F3A39_P_2): Likewise.
 275         (VEX_LEN_0F3A46_P_2): Likewise.
 276         (VEX_LEN_0F3AF0_P_3): Likewise.
 277         (VEX_W_0F3816_P_2): Likewise.
 278         (VEX_W_0F3818_P_2): Likewise.
 279         (VEX_W_0F3819_P_2): Likewise.
 280         (VEX_W_0F3836_P_2): Likewise.
 281         (VEX_W_0F3846_P_2): Likewise.
 282         (VEX_W_0F3858_P_2): Likewise.
 283         (VEX_W_0F3859_P_2): Likewise.
 284         (VEX_W_0F385A_P_2_M_0): Likewise.
 285         (VEX_W_0F3878_P_2): Likewise.
 286         (VEX_W_0F3879_P_2): Likewise.
 287         (VEX_W_0F3A00_P_2): Likewise.
 288         (VEX_W_0F3A01_P_2): Likewise.
 289         (VEX_W_0F3A02_P_2): Likewise.
 290         (VEX_W_0F3A38_P_2): Likewise.
 291         (VEX_W_0F3A39_P_2): Likewise.
 292         (VEX_W_0F3A46_P_2): Likewise.
 293         (MOD_VEX_0F3818_PREFIX_2): Removed.
 294         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 295         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 296         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 297         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 298         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 299         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 300         (VEX_LEN_0F3A0E_P_2): Likewise.
 301         (VEX_LEN_0F3A0F_P_2): Likewise.
 302         (VEX_LEN_0F3A42_P_2): Likewise.
 303         (VEX_LEN_0F3A4C_P_2): Likewise.
 304         (VEX_W_0F3818_P_2_M_0): Likewise.
 305         (VEX_W_0F3819_P_2_M_0): Likewise.
 306         (prefix_table): Updated.
 307         (three_byte_table): Likewise.
 308         (vex_table): Likewise.
 309         (vex_len_table): Likewise.
 310         (vex_w_table): Likewise.
 311         (mod_table): Likewise.
 312         (putop): Handle "LW".
 313         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 314         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 315         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 316         (OP_EX): Likewise.
 317         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 318         vex_vsib_q_w_dq_mode.
 319         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 320         (OP_VEX): Likewise.
 321
 322         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 323         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 324         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 325         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 326         (opcode_modifiers): Add VecSIB.
 327
 328         * i386-opc.h (CpuAVX2): New.
 329         (CpuBMI2): Likewise.
 330         (CpuLZCNT): Likewise.
 331         (CpuINVPCID): Likewise.
 332         (VecSIB128): Likewise.
 333         (VecSIB256): Likewise.
 334         (VecSIB): Likewise.
 335         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 336         (i386_opcode_modifier): Add vecsib.
 337
 338         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 339         * i386-init.h: Regenerated.
 340         * i386-tbl.h: Likewise.
 341
 342 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 343
 344         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 345         * i386-init.h: Regenerated.
 346
 347 2011-06-03  Nick Clifton  <nickc@redhat.com>
 348
 349         PR binutils/12752
 350         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 351         computing address offsets.
 352         (print_arm_address): Likewise.
 353         (print_insn_arm): Likewise.
 354         (print_insn_thumb16): Likewise.
 355         (print_insn_thumb32): Likewise.
 356
 357 2011-06-02  Jie Zhang <jie@codesourcery.com>
 358             Nathan Sidwell <nathan@codesourcery.com>
 359             Maciej Rozycki <macro@codesourcery.com>
 360
 361         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 362         as address offset.
 363         (print_arm_address): Likewise. Elide positive #0 appropriately.
 364         (print_insn_arm): Likewise.
 365
 366 2011-06-02  Nick Clifton  <nickc@redhat.com>
 367
 368         PR gas/12752
 369         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 370         passed to print_address_func.
 371
 372 2011-06-02  Nick Clifton  <nickc@redhat.com>
 373
 374         * arm-dis.c: Fix spelling mistakes.
 375         * op/opcodes.pot: Regenerate.
 376
 377 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 378
 379         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 380         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 381         * s390-opc.txt: Fix cxr instruction type.
 382
 383 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 384
 385         * s390-opc.c: Add new instruction types marking register pair
 386         operands.
 387         * s390-opc.txt: Match instructions having register pair operands
 388         to the new instruction types.
 389
 390 2011-05-19  Nick Clifton  <nickc@redhat.com>
 391
 392         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 393         operands.
 394
 395 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 396
 397         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 398         * i386-init.h: Regenerated.
 399
 400 2011-04-27  Nick Clifton  <nickc@redhat.com>
 401
 402         * po/da.po: Updated Danish translation.
 403
 404 2011-04-26  Anton Blanchard  <anton@samba.org>
 405
 406         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 407
 408 2011-04-21  DJ Delorie  <dj@redhat.com>
 409
 410         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 411         * rx-decode.c: Regenerate.
 412
 413 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * i386-init.h: Regenerated.
 416
 417 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 418
 419         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 420         from bdver1 flags.
 421
 422 2011-04-13  Nick Clifton  <nickc@redhat.com>
 423
 424         * v850-dis.c (disassemble): Always print a closing square brace if
 425         an opening square brace was printed.
 426
 427 2011-04-12  Nick Clifton  <nickc@redhat.com>
 428
 429         PR binutils/12534
 430         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 431         patterns.
 432         (print_insn_thumb32): Handle %L.
 433
 434 2011-04-11  Julian Brown  <julian@codesourcery.com>
 435
 436         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 437         (print_insn_thumb32): Add APSR bitmask support.
 438
 439 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 440
 441         * arm-dis.c (print_insn): init vars moved into private_data structure.
 442
 443 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 444
 445         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 446
 447 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 448
 449         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 450         post-increment to support LPM Z+ instruction. Add support for 'E'
 451         constraint for DES instruction.
 452         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 453
 454 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 455
 456         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 457
 458 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 459
 460         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 461         Use branch types instead.
 462         (print_insn): Likewise.
 463
 464 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 465
 466         * mips-opc.c (mips_builtin_opcodes): Correct register use
 467         annotation of "alnv.ps".
 468
 469 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 470
 471         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 472
 473 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 474
 475         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 476
 477 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 478
 479         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 480
 481 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 482
 483         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 484         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 485         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 486         exception, end_of_registers, msize, memory, bfd_mach.
 487         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 488         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 489         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 490         (get_allreg): Change to new defines.  Fallback to abort().
 491
 492 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 493
 494         * bfin-dis.c: Add whitespace/parenthesis where needed.
 495
 496 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 497
 498         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 499         than 7.
 500
 501 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 502
 503         * configure: Regenerate.
 504
 505 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 506
 507         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 508
 509 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 510
 511         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 512         dregs only when P is set, and dregs_lo otherwise.
 513
 514 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 515
 516         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 517
 518 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 519
 520         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 521
 522 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 523
 524         * bfin-dis.c (machine_registers): Delete REG_GP.
 525         (reg_names): Delete "GP".
 526         (decode_allregs): Change REG_GP to REG_LASTREG.
 527
 528 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 529
 530         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 531         M_IH, M_IU): Delete.
 532
 533 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 534
 535         * bfin-dis.c (reg_names): Add const.
 536         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 537         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 538         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 539         decode_counters, decode_allregs): Likewise.
 540
 541 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 542
 543         * i386-dis.c (OP_J): Parenthesize expression to prevent
 544         truncated addresses.
 545         (print_insn): Fix indentation off-by-one.
 546
 547 2011-02-01  Nick Clifton  <nickc@redhat.com>
 548
 549         * po/da.po: Updated Danish translation.
 550
 551 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 552
 553         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 554
 555 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 556
 557         * i386-dis.c (sIbT): New.
 558         (b_T_mode): Likewise.
 559         (dis386): Replace sIb with sIbT on "pushT".
 560         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 561         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 562
 563 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 564
 565         * i386-init.h: Regenerated.
 566         * i386-tbl.h: Regenerated
 567
 568 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 569
 570         * i386-dis.c (REG_XOP_TBM_01): New.
 571         (REG_XOP_TBM_02): New.
 572         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 573         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 574         entries, and add bextr instruction.
 575
 576         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 577         (cpu_flags): Add CpuTBM.
 578
 579         * i386-opc.h (CpuTBM) New.
 580         (i386_cpu_flags): Add bit cputbm.
 581
 582         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 583         blcs, blsfill, blsic, t1mskc, and tzmsk.
 584
 585 2011-01-12  DJ Delorie  <dj@redhat.com>
 586
 587         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 588
 589 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 590
 591         * mips-dis.c (print_insn_args): Adjust the value to print the real
 592         offset for "+c" argument.
 593
 594 2011-01-10  Nick Clifton  <nickc@redhat.com>
 595
 596         * po/da.po: Updated Danish translation.
 597
 598 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 599
 600         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 601
 602 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 603
 604         * i386-dis.c (REG_VEX_38F3): New.
 605         (PREFIX_0FBC): Likewise.
 606         (PREFIX_VEX_38F2): Likewise.
 607         (PREFIX_VEX_38F3_REG_1): Likewise.
 608         (PREFIX_VEX_38F3_REG_2): Likewise.
 609         (PREFIX_VEX_38F3_REG_3): Likewise.
 610         (PREFIX_VEX_38F7): Likewise.
 611         (VEX_LEN_38F2_P_0): Likewise.
 612         (VEX_LEN_38F3_R_1_P_0): Likewise.
 613         (VEX_LEN_38F3_R_2_P_0): Likewise.
 614         (VEX_LEN_38F3_R_3_P_0): Likewise.
 615         (VEX_LEN_38F7_P_0): Likewise.
 616         (dis386_twobyte): Use PREFIX_0FBC.
 617         (reg_table): Add REG_VEX_38F3.
 618         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 619         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 620         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 621         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 622         PREFIX_VEX_38F7.
 623         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 624         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 625         VEX_LEN_38F7_P_0.
 626
 627         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 628         (cpu_flags): Add CpuBMI.
 629
 630         * i386-opc.h (CpuBMI): New.
 631         (i386_cpu_flags): Add cpubmi.
 632
 633         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 634         * i386-init.h: Regenerated.
 635         * i386-tbl.h: Likewise.
 636
 637 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 638
 639         * i386-dis.c (VexGdq): New.
 640         (OP_VEX): Handle dq_mode.
 641
 642 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         * i386-gen.c (process_copyright): Update copyright to 2011.
 645
 646 For older changes see ChangeLog-2010
 647 \f
 648 Local Variables:
 649 mode: change-log
 650 left-margin: 8
 651 fill-column: 74
 652 version-control: never
 653 End: